JP5826234B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device on which a power semiconductor element is mounted and a method for manufacturing the semiconductor device.

In an inverter device, an uninterruptible power supply device, a machine tool, an industrial robot, and the like, a semiconductor device (general-purpose module) is used independently of the main body device.
For example, a semiconductor device of a package type in which a metal base plate having a predetermined thickness is used as a base and a power semiconductor element is mounted on the metal base plate is disclosed (for example, see Patent Document 1). The structure is shown in FIG.

FIG. 20 is a schematic diagram of a main part of a package type semiconductor device.
The semiconductor device 100 has a metal base plate 101 as a base, and a metal foil 102 is bonded onto the metal base plate 101 via a solder layer. An insulating plate 103 is bonded onto the metal foil 102, and a metal foil 104 is bonded onto the insulating plate 103. Further, a semiconductor element 106 is bonded onto the metal foil 104 via a solder layer 105. Here, the semiconductor element 106 corresponds to, for example, an IGBT (Insulated Gate Bipolar Transistor) element.

  Also, a molded resin case 107 is fixed from the upper end edges on both sides of the metal base plate 101 so as to surround the semiconductor element 106. The resin case 107 located on the upper edge of the metal base plate 101 is provided with lead frames 108, 109, 110. The lead frame 108 includes a main electrode (for example, an emitter electrode) of the semiconductor element 106, The lead frame 110 is electrically connected to the metal foil 104 conducted to the main electrode (for example, collector electrode) of the semiconductor element 106 via metal wires 111 and 112, respectively. The lead frame 109 is electrically connected to a control electrode (for example, a gate electrode) of the semiconductor element 106 through a metal wire 113.

  Further, a gel 114 made of a silicone material is sealed in the resin case 107 in order to prevent the metal wires 111, 112, and 113 from contacting each other and to protect the semiconductor element 106 from moisture, moisture, and dust. ing. A cooling fin (not shown) is joined under the metal base plate 101 via grease.

  However, in such a semiconductor device 100, the main electrode and the control electrode of the semiconductor element 106 and the lead frames 108, 109, 110 are connected by wire bonding using a large number of metal wires 111, 112, 113. Yes.

Therefore, there is a problem that the manufacturing process required for bonding cannot be shortened.
In recent years, a metal wireless semiconductor device 200 has been disclosed to deal with such problems (for example, see Patent Document 2).

FIG. 21 is a schematic diagram of a semiconductor device having a metal wireless structure.
The illustrated semiconductor device 200 includes a metal base plate 201, an insulating plate 202 bonded onto the metal base plate 201, and conductor patterns 203a, 203b, 203c, and 203d patterned on the insulating plate 202, and the conductor pattern 203b. A semiconductor element 205 is bonded to the top via a solder layer 204b.

  In addition, elements such as a transformer 206, a capacitor 207, and a resistor 208 are electrically connected to the conductor pattern 203d via a solder layer 204d. Also, an external lead-out terminal 209 that is led out of the semiconductor device 200 is electrically connected to the conductor pattern 203a via the solder layer 204a.

Here, the semiconductor element 205 has a structure having electrodes on both sides of the chip, and the back electrode thereof is connected to the conductor pattern 203b via the solder layer 204b.
The printed circuit board 210 located on each chip element and the external lead-out terminal 209 is provided with a through hole 210a and a patterned conductor pattern 211. In the semiconductor device 200, the conductive post 212a is joined to the upper surface electrode of the semiconductor element 205 via the solder layer 204e. Further, another conductive post 212b is joined to the conductor pattern 211 arranged at a predetermined position.

  A control IC 214 is mounted on the conductor pattern 213 disposed on the printed circuit board 210. The surface of the printed circuit board 210 on which the control IC 214 is mounted is disposed so as to face the main surface of the insulating plate 202 on which the semiconductor element 205 and the like are mounted.

  Further, the conductive posts 212 a and 212 b are connected through the through holes 210 a of the printed circuit board 210. In particular, the conductive post 212b is joined to the conductor pattern 203c via the solder layer 204c. Therefore, the upper surface electrode of the semiconductor element 205 and the conductor pattern 203c are electrically drawn onto the printed circuit board 210 via the conductive posts 212a and 212b without depending on the metal wire. A resin 220 is filled between the printed board 210 and the insulating plate 202.

  Thus, the semiconductor device 200 has a structure that does not use metal wires. Further, the metal base plate 201 and the printed board 210 are integrated by resin sealing, and a chip element or the like is arranged between them.

JP 2003-289130 A JP 2004-228403 A

  By the way, in recent IGBTs, the increase in power has further progressed, and a large current flows between the main electrodes of the IGBT during operation. A considerable amount of heat is generated by energizing the large current.

Also in the semiconductor device shown in FIG. 21, when a large current flows, the conductive post or the like may be deformed due to thermal expansion or the like, and the reliability as the semiconductor device may be reduced.
The present invention has been made in view of these points, and further provides a semiconductor device having high reliability, excellent operating characteristics, and high productivity, and a method for manufacturing such a semiconductor device. The purpose is to do.

In the present invention, in order to solve the above problems, an insulating plate, wherein a metal foil formed on the first main surface of the insulating plate, one of the at no less formed in said second main surface of the insulating plate Another metal foil, at least one semiconductor element bonded on the other metal foil, and a printed circuit board arranged to face the second main surface of the insulating plate on which the semiconductor element is arranged A metal foil formed on the first main surface of the printed circuit board, at least one other metal foil formed on the second main surface of the printed circuit board, and at least one main electrode of the semiconductor element A plurality of post electrodes formed on the printed circuit board so as to be electrically connected to each other and fixed to a through hole provided in the inner wall. A semiconductor device characterized by It is subjected.

Moreover, in this invention, the 1st metal foil selectively arrange | positioned on the 1st main surface of a resin layer, The 2nd metal foil selectively arrange | positioned on the 2nd main surface of the said resin layer, A through-hole in which a cylindrical plating layer is provided on the inner wall, and a plurality of posts having a long and narrow shape that are infused and fixed halfway through the through-hole and are electrically connected to the first metal foil and the second metal foil. Preparing a printed circuit board comprising electrodes, disposing the printed circuit board and the semiconductor element such that a lower end of the post electrode faces the first main electrode of the semiconductor element, and a lower end of the post electrode; Electrically connecting the first main electrode; an insulating plate; a third metal foil formed on the first main surface of the insulating plate; and a second main surface of the insulating plate. And an insulating substrate provided with at least one fourth metal foil formed. And placing the semiconductor element on the fourth metal foil so that the second main electrode side of the semiconductor element is in contact, and electrically connecting the fourth metal foil and the second main electrode. And a step of connecting to the semiconductor device.
In the present invention, the insulating plate, the metal foil formed on the first main surface of the insulating plate, at least one other metal foil formed on the second main surface of the insulating plate, At least one semiconductor element bonded on another metal foil; a printed circuit board disposed to face the second main surface of the insulating plate on which the semiconductor element is disposed; A metal foil formed on one main surface, at least one other metal foil formed on a second main surface of the printed circuit board, and at least one main electrode of the semiconductor element are electrically connected. And a plurality of post electrodes having a diameter of 0.3 to 0.6 mm, in which a cylindrical plating layer formed on the printed board is injected and fixed halfway into a through hole provided on an inner wall. A semiconductor device is provided.

  As described above, a semiconductor device having high reliability, excellent operation characteristics, and high productivity and a method for manufacturing such a semiconductor device are realized.

It is a principal part schematic diagram explaining the structure of a semiconductor device. It is a principal part cross-sectional schematic diagram explaining the structure of a semiconductor device. It is a principal part figure explaining the whole structure of a printed circuit board. It is a principal part figure explaining the structure of the surface side of a printed circuit board. FIG. 3 is a schematic cross-sectional view of a relevant part for explaining one step in the method for manufacturing a semiconductor device (part 1); It is a principal part cross-sectional schematic diagram explaining 1 process of the manufacturing method of a semiconductor device (the 2). FIG. 10 is a schematic cross-sectional view of the relevant part for explaining one step in the method for manufacturing a semiconductor device (part 3); FIG. 10 is a schematic cross-sectional view of the relevant part for explaining one step in the method for manufacturing a semiconductor device (part 4); FIG. 10 is a schematic cross-sectional view of the relevant part for explaining one step in the method for manufacturing a semiconductor device (part 5); FIG. 10 is a schematic cross-sectional view of the relevant part for explaining one step in the method for manufacturing a semiconductor device (part 6); FIG. 10 is a schematic cross-sectional view of the relevant part for explaining one step in the method of manufacturing a semiconductor device (part 7); FIG. 10 is a schematic cross-sectional view of the relevant part for explaining one step in the method for manufacturing a semiconductor device (part 8); FIG. 9 is a schematic cross-sectional view of the relevant part for explaining one step in the method of manufacturing a semiconductor device (No. 9). FIG. 10 is a schematic cross-sectional view of the relevant part for explaining one step in the method of manufacturing a semiconductor device (part 10); It is a principal part cross-sectional schematic diagram explaining 1 process of the manufacturing method of a semiconductor device (the 11). FIG. 6 is a schematic cross-sectional view of a relevant part for explaining a modification of the structure of the semiconductor device (part 1); FIG. 10 is a schematic cross-sectional view of a relevant part for explaining a modification of the structure of the semiconductor device (part 2); It is a principal part schematic diagram explaining the modification of the structure of a semiconductor device (the 1). FIG. 10 is a schematic diagram of a main part for explaining a modification of the structure of the semiconductor device (part 2); It is a principal part schematic diagram of a package type semiconductor device. It is a schematic diagram of the semiconductor device of a metal wireless structure.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, the structure of the semiconductor device in this embodiment will be described.
FIG. 1 is a schematic view of a main part for explaining the structure of a semiconductor device. Here, FIG. 1A is a top view of a main part of the semiconductor device, and FIG. Moreover, in FIG. (B), sectional drawing in the position of AB of FIG. (A) is shown.

  The illustrated semiconductor device 1 has a structure in which an insulating substrate 10 and a printed circuit board 30 opposed to the insulating substrate 10 are integrated by sealing an underfill material 40, and a plurality of insulating substrates 10 are formed on the insulating substrate 10. Semiconductor elements 20 and 21 are mounted. Further, the semiconductor device 1 is packaged by a resin case (not shown) and functions as, for example, a general-purpose IGBT module.

  The insulating substrate 10 includes an insulating plate 10a, a metal foil 10b formed by a DCB (Direct Copper Bonding) method on the lower surface of the insulating plate 10a, and a plurality of metal foils also formed on the upper surface of the insulating plate 10a by the DCB method. 10c, 10d. These metal foils 10c and 10d are selectively patterned on the upper surface of the insulating plate 10a.

  Furthermore, on the metal foils 10c and 10d, the main electrode side (for example, collector electrode) of at least one semiconductor element 20 or the like via a tin (Sn) -silver (Ag) lead-free solder layer 11 or The cathode side of the semiconductor element 21 is joined.

  Here, the semiconductor element 20 corresponds to, for example, a vertical power semiconductor element such as an IGBT element or a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The semiconductor element 21 corresponds to a power diode element such as an FWD (Free Wheeling Diode) element.

The insulating plate 10a is made of, for example, alumina (Al ₂ O ₃ ) sintered body, ceramic such as silicon nitride (SiN), and the metal foils 10b, 10c, and 10d are mainly composed of copper (Cu). Consists of metal.

The insulating plate 10a has a thickness of 0.3 to 0.7 mm, and the metal foils 10b, 10c, and 10d have a thickness of 0.2 to 0.6 mm, for example.
In the semiconductor device 1, an implant printed circuit board (hereinafter referred to as a printed circuit board) 30 is disposed above the semiconductor elements 20 and 21 so as to face the insulating substrate 10.

  The printed circuit board 30 has a multilayer structure, for example, a resin layer 30a is disposed at the center, and at least one metal foil 30b is selectively patterned on the upper surface thereof. Further, at least one metal foil 30c is selectively patterned on the lower surface.

  Here, the material of the resin layer 30a is, for example, a polyimide resin, an epoxy resin, or the like. Moreover, you may impregnate the inside of the resin layer 30a with the glass cloth comprised by the glass fiber as needed. Moreover, the metal foils 30b and 30c are made of, for example, copper as a main component.

The rigidity of the printed circuit board 30 may be a hard type having a predetermined rigidity, or may be flexible so that the entire printed circuit board 30 can be distorted.
A resin protective layer 31 is formed on the outermost surface of the printed circuit board 30. In FIG. (A), the protective layer 31 is not shown in order to clearly describe the pattern shape of the metal foil 30b.

  In the semiconductor device 1, a plurality of through holes 30 d are provided on the printed circuit board 30 immediately above the region where the main electrode (for example, emitter electrode) of the semiconductor element 20 is located so as to be approximately line symmetric. A thin cylindrical plating layer (not shown) is provided in the through hole 30d, and a cylindrical post electrode 30e is injected (implanted) through the cylindrical plating layer in the through hole 30d. .

  Each post electrode 30e is soldered in the through hole 30d and is electrically connected to the metal foils 30b and 30c disposed on the main surface of the printed circuit board 30. When placing metal foil on both sides of the printed circuit board, injecting post electrodes through the cylindrical plating layer and soldering in this way ensures good electrical connection and mechanical strength. can do. In the case of forming a relatively thick metal foil on one surface of the printed board and injecting the post electrode as in a second modification described later, the cylindrical plating layer and soldering may be omitted.

  Here, in the arrangement of the post electrodes 30e, for example, immediately after the emitter electrode region of the semiconductor element 20, a set of five post electrodes 30e constitutes a row, and the two are arranged in line symmetry. Arranged in columns. The pitch of the post electrodes 30e is configured to be uniform. In addition, the lower end of each post electrode 30 e is electrically connected to the emitter electrode of the semiconductor element 20 via the solder layer 12.

  Further, immediately after the anode side region of the semiconductor element 21, a set of four post electrodes 30e form a row and are arranged in two rows so that they are line symmetric. The pitch of the post electrodes 30e is configured to be uniform. In addition, the lower end of each post electrode 30e is electrically connected to the anode side of the semiconductor element 21 via a solder layer.

  Thereby, in the semiconductor device 1, electrical connection between the emitter electrode of the semiconductor element 20 and the anode side of the semiconductor element 21 is ensured via the post electrode 30e and the metal foil 30b.

The electrical connection between the collector electrode of the semiconductor element 20 and the cathode side of the semiconductor element 21 is ensured via the metal foils 10c and 10d.
The material of the post electrode 30e is mainly composed of, for example, copper, aluminum (Al), tin-silver based lead-free solder material, or an alloy made of these metals. Further, the length of each post electrode 30e is uniform.

  In the above example, the number of post electrodes 30e bonded to the emitter electrode of the semiconductor element 20 is limited to ten. However, the number of post electrodes 30e bonded to one semiconductor element 20 is set to this number. It is not limited. For example, when the diameter of the post electrode 30e is 0.3 to 0.6 mm, a current of 8 to 20 A can be applied to one post electrode 30e. Therefore, the number of post electrodes 30e to be joined to the semiconductor element 20 may be determined from the current value according to the capacity of the semiconductor element 20 and arranged in that number.

  Due to the arrangement of the plurality of post electrodes 30e, for example, in the semiconductor element 20, even when a large current is passed between the main electrodes, the large current is distributed to the main electrodes via the respective post electrodes 30e.・ Energize.

  Further, in the printed circuit board 30, a through hole 30f is separately provided above the outside of the emitter electrode region of the semiconductor element 20, and a cylindrical post electrode 30g is injected and joined also into the through hole 30f. . The post electrode 30g is electrically connected to a control electrode (for example, a gate electrode) of the semiconductor element 20 via a solder layer.

Thus, the main electrode or control electrode arranged on the main surface of the semiconductor element 20 and the anode side of the semiconductor element 21 are joined to the post electrodes 30e and 30g.
The structure of the post electrodes 30e and 30g described above is not limited to a rod shape, but may be a pipe shape having a hollow inside.

  Furthermore, in the semiconductor device 1, the underfill material 40 is filled in the gap between the insulating substrate 10 and the printed circuit board 30. Thereby, the semiconductor device 1 is integrated by the insulating substrate 10 and the printed circuit board 30.

  The semiconductor device 1 is provided with a resin case made of, for example, PPS (poly phenylene sulfide) so as to surround the semiconductor elements 20 and 21 (not shown). The inner surface of the resin case is filled with a sealing material made of, for example, a gel containing silicone as a main component or an epoxy resin (not shown) for the purpose of protecting elements, circuits, and the like.

  Alternatively, without using a resin case (not shown), an epoxy resin may be potted or transfer molded so as to surround the semiconductor device 1 using a metal mold (not shown).

  Further, although not particularly shown in FIG. 1, a plurality of lead frames as external connection terminals penetrate vertically through the printed circuit board 30, and these are connected to the respective electrodes of the semiconductor elements 20 and 21. Electrical connection is ensured.

  Although not particularly shown in FIG. 1, a metal base plate having a larger area than the insulating substrate 10 may be used as the base of the semiconductor device 1. For example, a metal base plate having a thickness of several millimeters may be bonded under the metal foil 10b via a solder layer. A heat spreader known as a heat radiator may be installed on the semiconductor elements 20 and 21.

  Next, in order to deepen the understanding of the detailed structure of the semiconductor device 1, the structure of the semiconductor device 1 will be described with reference to a further enlarged view of FIG. In the following drawings, the same members as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 2 is a schematic cross-sectional view of the relevant part for explaining the structure of the semiconductor device. In this figure, an enlarged view of the periphery of the post electrode 30e disposed in the semiconductor device 1 and the semiconductor element 20 joined to the post electrode 30e is mainly shown.

As described above, in the semiconductor device 1, the main electrode (collector electrode) of the semiconductor element 20 is joined to the metal foil 10 d via the solder layer 11.
A printed circuit board 30 is disposed above the semiconductor element 20, and a plurality of through holes 30 d are formed in the printed circuit board 30. A cylindrical plating layer 30h made of, for example, copper is disposed on the inner wall of the through hole 30d.

  Also, patterned metal foils 30 b and 30 c are disposed on the upper and lower main surfaces of the printed circuit board 30. These metal foils 30b and 30c are covered with a cylindrical plating layer 30h and are electrically connected to the cylindrical plating layer.

  Further, the post electrode 30e described above is injected halfway into the cylindrical plating layer 30h, and is fixed to the cylindrical plating layer 30h by the solder layer 30i. Thereby, the electrical connection between the post electrode 30e and the metal foils 30b and 30c and the mechanical strength at the joint are ensured.

  Further, the lower ends of the plurality of post electrodes 30 e are electrically connected to another main electrode (emitter electrode) of the semiconductor element 20 via the solder layer 12. Thereby, for example, when the control electrode of the semiconductor element 20 is in the ON state and the emitter-collector electrode of the semiconductor element 20 is energized, the respective post electrodes 30e are interposed between the metal foils 30b and 30c and the metal foil 10d. A large current.

Note that the side surface of the solder layer 12 forms a fillet structure, and the bonding between the lower end of the post electrode 30 e and the main electrode of the semiconductor element 20 is strengthened.
Further, in the semiconductor device 1, an underfill material 40 is filled in a gap between the printed circuit board 30 and the insulating substrate 10. The underfill material 40 includes, for example, a filler material composed of an inorganic material, which is mainly composed of an epoxy resin, a cyanate resin, or a silicon resin. As the filler material, for example, an inorganic material having high thermal conductivity such as boron nitride (BN), aluminum nitride (AlN), silicon nitride, or the like is used.

  According to such a configuration of the semiconductor device 1, no metal wire is required. Accordingly, the L component of the energization path communicating from the external connection terminal of the semiconductor device 1 to the main electrode or anode side of the semiconductor elements 20 and 21 is greatly reduced.

  Further, when the semiconductor device 1 is operated, the temperature in the vicinity of the semiconductor element 20 is repeatedly raised and lowered due to heat generation and cooling by the semiconductor element 20. Excessive stress is not applied to the solder layer 12 that joins the electrode and the post electrode 30e.

  For example, in the vicinity of the semiconductor element 20, the shape of the post electrode 30 e is elongated and the junction area between the main electrode of the semiconductor element 20 and the post electrode 30 e is reduced. For this reason, even if the linear expansion of the post electrode 30e itself increases and the temperature is repeated, the post electrode 30e does not greatly expand or contract in the lateral direction (direction perpendicular to the length direction). Accordingly, excessive stress is not applied to the solder layer 12 during the operation of the semiconductor device 1.

  Furthermore, since such a post electrode 30e is bonded to the main electrode of the semiconductor element 20 in a plurality of pieces, even if stress is applied to the solder layer 12, it is evenly distributed under each post electrode 30e. Is done. Therefore, the stress applied to each solder layer 12 is dispersed and reduced as much as possible.

  Further, even when the printed circuit board 30 or the semiconductor elements 20 and 21 are distorted or deformed by temperature increase / decrease during the operation of the semiconductor device 1, the post electrode 30e has an elongated shape. Alternatively, the post electrode 30e itself can be bent (deformed) in accordance with the deformation of the semiconductor elements 20 and 21. As a result, the stress applied to each solder layer 12 is greatly reduced.

In addition, since the plurality of post electrodes 30e are distributed on the main electrode or anode side of the semiconductor elements 20 and 21 as described above, the heat dissipation is remarkably improved.
For example, in the semiconductor element 20, since a large current flows from the emitter electrode by being dispersed by the plurality of post electrodes 30 e, a local temperature rise does not occur in the semiconductor element 20. Further, even if the semiconductor element 20 generates heat, the heat is conducted through the respective post electrodes 30 e and dispersed and radiated to the printed circuit board 30.

  Further, since the bonding area between the post electrode 30e and the main electrode or anode side of the semiconductor elements 20 and 21 is small, no voids remain in the solder layer 12. When the area of the joint between the conductive post and the semiconductor element is large, voids existing in the solder material may remain in the solder material during reflow, and voids may be formed in the solder layer.

  However, in the semiconductor device 1, the junction area between the post electrode 30 e and the main electrodes and anode sides of the semiconductor elements 20 and 21 is reduced. Therefore, the voids existing in the solder material can easily escape from the gap between the semiconductor elements 20, 21 and the post electrode 30 e during reflow, and voids do not remain in the solder layer 12. As a result, the solder layer 12 is densely filled in the gap between the main electrode and anode side of the semiconductor elements 20 and 21 and the post electrode 30e, so that contact failure of the solder layer 12 does not occur.

  Further, when the semiconductor device 1 is operated at a high operating frequency, a skin effect may occur on the surface of the electrode joined to the main electrode or the anode side of the semiconductor elements 20 and 21. However, in the semiconductor device 1, a plurality of rod-like or pipe-like post electrodes 30e are dispersedly arranged on the emitter electrode and anode sides of the semiconductor elements 20 and 21, and the total surface area thereof is increased.

Therefore, even if the skin effect occurs, the large current flows in a distributed manner from the emitter electrode through the surfaces of the plurality of post electrodes 30e.
As a result, even at a high operating frequency, a local temperature rise does not occur in the semiconductor element 20, and the heat dissipation is greatly improved.

  The main electrodes and anode sides of the semiconductor elements 20 and 21 and the post electrode 30e may be joined by direct joining such as ultrasonic joining or pressure welding in addition to the solder joining described above. Good (not shown). Thereby, the main electrode or anode side of the semiconductor elements 20 and 21 and the post electrode 30e are more firmly joined.

  Further, the semiconductor device 1 has a structure in which the gap between the printed board 30 and the insulating board 10 is sealed with the underfill material 40 and the insulating board 10 and the printed board 30 are integrated. Thereby, the mechanical strength of the whole semiconductor device 1 is ensured.

  In addition, since the underfill material 40 contains a filler material having a high thermal conductivity, even if the high-power semiconductor element 20 is mounted on the insulating substrate 10, heat generation from the semiconductor element 20 is sufficient. The heat can be dissipated.

From the above results, the semiconductor device 1 has high reliability and good operating characteristics. In addition, the power cycle tolerance of the semiconductor device 1 is further improved.
Next, the entire structure of the printed circuit board 30 disposed above the semiconductor elements 20 and 21 will be described in detail.

  FIG. 3 is a main part diagram for explaining the entire structure of the printed circuit board. Here, FIG. (A) is a principal part rear view of a printed circuit board. That is, FIG. 1A shows the main surface of the printed circuit board viewed from the insulating substrate 10 side shown in FIG. Moreover, FIG. (B) is principal part sectional drawing of a printed circuit board, and sectional drawing in the position of AB of FIG. (A) is shown.

  As an example, the printed circuit board 30 shown in the figure has a structure corresponding to a semiconductor device (6 in 1 structure) that stores six sets of IGBT and FWD parallel connection circuits constituting an inverter circuit in one package.

  As described above, a plurality of metal foils 30 c and 30 j are patterned on any main surface of the resin layer 30 a constituting the printed circuit board 30. Further, a protective layer 31 is formed on the resin layer 30a and the metal foils 30c and 30j. In FIG. 2A, the protective layer 31 formed on the outermost surface of the printed circuit board 30 is not shown in order to clearly show the pattern shapes of the metal foils 30c and 30j.

  Such metal foils 30 c and 30 j are arranged so that a part thereof is located on the emitter electrode of the semiconductor element 20 and the region on the anode side of the semiconductor element 21. Then, a plurality of post electrodes 30e are arranged for that amount.

  For example, in the metal foils 30c and 30j located immediately above the emitter electrode of the semiconductor element 20 and the anode side region of the semiconductor element 21, a plurality of post electrodes 30e are arranged in line symmetry.

  Specifically, the metal foils 30c and 30j on the emitter electrode region of the semiconductor element 20 are arranged in groups of five, and two sets of post electrodes 30e are arranged in two rows in line symmetry. Accordingly, a total of ten post electrodes 30 e are arranged on the metal foils 30 c and 30 j on the emitter electrode region of the semiconductor element 20.

  The metal foils 30c and 30j on the anode side region of the semiconductor element 21 are arranged in groups of four, and two sets of post electrodes are arranged in two rows in line symmetry. Accordingly, a total of eight post electrodes 30 e are arranged on the metal foils 30 c and 30 j on the anode side region of the semiconductor element 21.

Note that the pitch of the post electrodes 30e arranged in the same row is uniform.
Further, in the above example, specific numerical values are exemplified for the number of post electrodes 30e arranged, but the number of post electrodes 30e bonded to each one of the semiconductor elements 20 and 21 is as described above. It is not limited.

  Furthermore, in addition to the metal foils 30c and 30j described above, the metal foils 30k and 30l having a narrow line width are formed in a pattern on the printed board 30, and a part of the pattern is a region of a control electrode (for example, a gate electrode) of the semiconductor element 20 It arrange | positions so that it may be located on. Further, a post electrode 30g is disposed in the metal foils 30k and 30l located on the control electrode region of the semiconductor element 20.

  Further, as shown in this figure, the metal foils 30ja, 30jb, and 30jc are extended from the metal foil 30j to a wide area of the printed circuit board 30 other than immediately above the semiconductor element 20 and 21 mounting area. As described above, the metal foil 30j is electrically connected to the emitter electrode or the anode side of the semiconductor elements 20 and 21.

  When such metal foils 30ja, 30jb, and 30jc are present in the printed circuit board 30, electromagnetic shielding is promoted, and noise during operation of the semiconductor device 1 (for example, radiation noise generated by switching of the semiconductor element 20). Can be reduced. That is, the metal foils 30ja, 30jb, and 30jc function as metal foils for electromagnetic shielding.

  For example, when the printed circuit board 30 on which the metal foils 30ja, 30jb, and 30jc are patterned is mounted on the semiconductor device 1 as compared with a printed circuit board that does not include the metal foils 30ja, 30jb, and 30jc, the radiation noise has a predetermined frequency. It is reduced by 5 dB in the band.

Note that the metal foils 30ja, 30jb, and 30jc may be selectively disposed not only on the back surface of the printed board 30 but also on the main surface side.
Further, a plurality of through holes 32 are formed outside the region where the metal foils 30c, 30ja, 30jb, 30jc, 30k, 30l are formed. These through holes 32 are injection ports for allowing the underfill material 40 shown in FIG. 2 to flow into the gap between the insulating substrate 10 and the printed circuit board 30. By providing a plurality of such injection ports in the printed circuit board 30, the paste-like underfill material can smoothly flow into the gap between the printed circuit board 30 and the insulating substrate 10. As a result, after the underfill material that has flowed into the gap is cured, the underfill material 40 is placed in the gap between the insulating substrate 10 and the printed board 30 without any voids remaining in the underfill material 40. It can be filled tightly.

Next, the structure on the upper surface side of the printed circuit board will be described.
FIG. 4 is a main part view for explaining the structure of the surface side of the printed board. Further, in this drawing, the protective layer 31 formed on the outermost surface of the printed board 30 is not shown in order to clearly show the pattern shapes of the metal foils 30b and 30m.

Metal foils 30b and 30m and through holes 32 are arranged so that the structure on the upper surface side of the printed circuit board 30 corresponds to the structure on the back surface side of the printed circuit board 30 shown in FIG.
A solder layer 30i is buried in each through hole 30d into which the post electrode 30e is injected.

Here, in this printed circuit board 30, as shown in the figure, an IC circuit section 33, a capacitor section 34, and a resistance section 35 are provided in a region other than the metal foils 30b and 30m.
By disposing such an IC circuit unit 33, capacitor unit 34, and resistor unit 35 on the main surface of the printed circuit board 30, a temperature sensor circuit, an overvoltage / overcurrent protection circuit, and the like are incorporated in the semiconductor device 1. A compact and thin intelligent power module is realized.

Next, a method for manufacturing the semiconductor device 1 will be described. Here, the semiconductor device 1 is manufactured by two manufacturing methods.
First, the first manufacturing method will be described.

<First manufacturing method>
FIG. 5 is a schematic cross-sectional view of the relevant part for explaining one process of the method for manufacturing a semiconductor device.
First, as shown in this figure, an insulating substrate 10 which is a base of the semiconductor device 1 is prepared. Specifically, the metal foil 10b is bonded to the lower surface side of the insulating plate 10a by the DCB method, and the patterned at least one metal foil 10c, 10d, 10e is applied to the upper surface side of the insulating plate 10a by the DCB method. It is made to join by. In addition, when there are a plurality of metal foils 10c, their patterns are the same as viewed from above the insulating substrate 10. The same applies to the metal foils 10d and 10e. And either metal foil 10c or metal foil 10d and metal foil 10e are electrically connected.

  Subsequently, a paste-like solder material 11a is selectively printed on the metal foils 10c, 10d, and 10e. Note that the solder material 11a is made of, for example, tin-silver-based lead-free. In addition, the solder material 11a may be placed on the metal foils 10c and 10d instead of a paste.

FIG. 6 is a schematic cross-sectional view of the relevant part for explaining one process of the method for manufacturing a semiconductor device.
Next, the semiconductor element 20 is mounted on the solder material 11a so that the back electrode (for example, collector electrode) side of the semiconductor element 20 is in contact with the solder material 11a. Then, a paste-like solder material 12 a is selectively printed on a main electrode (for example, an emitter electrode) disposed on the upper surface side of the semiconductor element 20. Also, a paste-like solder material 12a is selectively printed on a control electrode (for example, a gate electrode) (not shown). In addition, the material of the solder material 12a is comprised by the tin-silver type lead free, for example. In addition, the solder material 12a may be placed on the semiconductor element 20 instead of a paste.

FIG. 7 is a schematic cross-sectional view of the relevant part for explaining one process of the method for manufacturing a semiconductor device.
Next, the insulating substrate 10 on which the semiconductor element 20 or the like is mounted is placed in the carbon lower jig 50. Then, the above-described printed circuit board 30 is disposed so as to face the insulating substrate 10.

  Specifically, the main surface from which the post electrode 30e of the printed circuit board 30 protrudes is opposed to the insulating substrate 10, and the lower end of the post electrode 30e is connected to the main electrode or control electrode (non-conductive) of the semiconductor element 20 via the solder material 12a. Arranged so as to be in contact with the figure.

  The printed circuit board 30 is provided with at least one through hole 36 at a predetermined position for allowing the lead frame for the external connection terminal to pass therethrough. A metal foil 37 is disposed on the resin layer 30a in the vicinity of the through hole 36. Then, a paste-like solder material 13 a is also selectively disposed on the upper edge of the through hole 36. The material of the solder material 13a is made of, for example, tin-silver based lead-free solder. Moreover, in the solder material 13a, you may place a sheet-like thing on the said upper end edge instead of a paste form.

  Here, the outer peripheral ends of the insulating substrate 10 and the printed circuit board 30 are fixed by the lower jig 50. Therefore, the positions of the lower ends of the plurality of post electrodes 30 e are fixed by placing the insulating substrate 10 and the printed board 30 on the lower jig 50.

  Note that the insulating substrate 10 and the printed circuit board 30 may be placed together in the lower jig 50 after the printed circuit board 30 faces the insulating substrate 10 and the printed circuit board 30 is disposed on the insulating substrate 10.

FIG. 8 is a schematic cross-sectional view of the relevant part for explaining one process of the method for manufacturing a semiconductor device.
Next, the upper jig 51 made of carbon is fitted into the lower jig 50. Then, the lead frame 60 for external connection terminals is inserted into the through hole 38 provided in the upper jig 51, and the lead frame 60 is further passed through the through hole 36 of the printed circuit board 30, and one end of the lead frame 60 is made of metal. It is made to contact on the solder material 11a arrange | positioned on the foil 10e.

  Subsequently, the insulating substrate 10, the printed circuit board 30 and the like sandwiched between the upper jig 51 and the lower jig 50 are placed in a heating furnace (not shown) together with the upper jig 51 and the lower jig 50, and the solder materials 11a and 12a. , 13a is heated and melted to perform solder joining. That is, reflow processing is performed.

FIG. 9 is a schematic cross-sectional view of the relevant part for explaining one process of the method for manufacturing a semiconductor device.
Next, the insulating substrate 10 and the printed circuit board 30 are taken out from the upper jig 51 and the lower jig 50.

  In this state, between the semiconductor element 20 and the metal foils 10c and 10d, between the post electrode 30e and the main electrode and control electrode (not shown) of the semiconductor element 20, and between the lead frame 60 and the metal foil 10e. The solder layers 11, 12, and 13 are formed and electrically connected to each other.

  Subsequently, a paste-like underfill material flows into the gap between the insulating substrate 10 and the printed circuit board 30. The paste-like underfill material may flow from the through hole 32 or may flow from the gap between the end portions of the insulating substrate 10 and the printed circuit board 30. Further, bubbles in the paste-like underfill material may be removed from the through holes 32. Subsequently, the underfill material is cured, and the gap between the insulating substrate 10 and the printed circuit board 30 is sealed with the underfill material 40. The through-hole 32 can be formed in any region except for the metal foil 30c and the like of the printed board 30. Such an arrangement of the through holes 32 effectively utilizes the area of the printed circuit board.

  Further, through holes may be provided between the plurality of post electrodes 30e in the region such as the metal foil 30c so that the underfill material 40 is easily injected into a narrow space around the post electrode 30e. In addition, after the underfill material 40 is injected, the underfill material can be injected without a gap into a narrow portion around the post electrode 30e by placing the insulating substrate 10 or the like under reduced pressure.

Further, after that, the integrated insulating substrate 10 and the printed circuit board 30 are packaged by the resin case with the underfill material 40.
FIG. 10 is a schematic cross-sectional view of the relevant part for explaining one process of the method for manufacturing a semiconductor device.

  For example, the integrated insulating substrate 10 and the printed circuit board 30 are accommodated in the resin case 70 made of PPS by the underfill material 40, and, for example, a gel mainly composed of silicone is formed on the inner surface of the resin case 70. Alternatively, the sealing material 41 made of epoxy resin is filled and solidified.

Thereby, the semiconductor module 2 in which the insulating substrate 10, the semiconductor elements 20, 21 and the printed circuit board 30 are packaged by the resin case 70 is completed.
According to such a manufacturing method, the solder material 11a, 12a, 13a is reflowed once, and the semiconductor element 20, the metal foils 10c, 10d, the post electrode 30e, the main electrode of the semiconductor element 20, and the control electrode (illustrated). Not)), one end of the lead frame 60 and the metal foil 10e are joined via the solder layers 11, 12, and 13. Therefore, the manufacturing process of the semiconductor device can be greatly shortened.

  In particular, in the manufacturing method of the present embodiment, as shown in FIG. 8, the outer peripheral ends of the printed circuit board 30 and the insulating substrate 10 are fixed by the lower jig 50 and positioned on the main electrode and the control electrode of the semiconductor element 20. The solder material 11a, 12a, 13a is reflowed while fixing the electrode 30e.

  At this time, as described above, a plurality of post electrodes 30e positioned on the main electrode of the semiconductor element 20 constitute a row and are arranged in a line-symmetric manner. Therefore, even if the solder material 12a located under each post electrode 30e is melted by reflow, the solder material 12a is uniformly aggregated and solidified at the position of each post electrode 30e. As a result, the self-alignment effect is promoted, and the misalignment of the semiconductor element 20 after soldering with respect to the metal foils 10c and 10d is surely prevented. Further, the positional deviation of the lead frame 60 with respect to the metal foil 10e can be reliably prevented.

Next, the second manufacturing method will be described.
<Second production method>
FIG. 11 is a schematic cross-sectional view of the relevant part for explaining one step of the method for manufacturing the semiconductor device.

First, as shown in this figure, the semiconductor element 20 is placed at a predetermined position in the lower jig 52. By this placement, the position of the semiconductor element 20 is fixed in the lower jig 52.
Subsequently, a paste-like solder material 12a is selectively printed on a main electrode (for example, an emitter electrode) disposed on the upper surface side of the semiconductor element 20. Also, a paste-like solder material 12a is selectively printed on a control electrode (for example, a gate electrode) (not shown).

Subsequently, the above-described printed circuit board 30 is disposed so as to face the semiconductor element 20.
Specifically, the main surface of the printed circuit board 30 on which the post electrode 30e protrudes is opposed to the semiconductor element 20, and the lower end of the post electrode 30e is connected to the main electrode or control electrode (non-conductive) of the semiconductor element 20 via the solder material 12a. Arranged so as to be in contact with the figure.

  Thereby, the outer peripheral ends of the semiconductor element 20 and the printed circuit board 30 are fixed by the lower jig 52. Therefore, the positions of the lower ends of the plurality of post electrodes 30 e are fixed by placing the semiconductor element 20 and the printed board 30 on the lower jig 52.

  Then, the semiconductor element 20 and the printed circuit board 30 fixed by the lower jig 52 are placed in a heating furnace (not shown) together with the lower jig 52 (not shown), the solder material 12a is heated and melted and solder-bonded, and reflow processing is performed. Do.

FIG. 12 is a schematic cross-sectional view of an essential part for explaining one process of a method for manufacturing a semiconductor device.
In this figure, the state of the semiconductor element 20 and the printed circuit board 30 taken out from the lower jig 52 after reflow is shown.

By reflow, the solder layer 12 is formed between the post electrode 30e, the main electrode of the semiconductor element 20 and the control electrode (not shown), and is electrically joined.
FIG. 13 is a schematic cross-sectional view of the relevant part for explaining one step in the method for manufacturing a semiconductor device.

  Next, an insulating substrate 10 that serves as a base of the semiconductor device 1 is prepared. Specifically, the metal foil 10b is bonded to the lower surface side of the insulating plate 10a by the DCB method, and the patterned at least one metal foil 10c, 10d, 10e is applied to the upper surface side of the insulating plate 10a by the DCB method. It is made to join by. In addition, when there are a plurality of metal foils 10c, their patterns are the same as viewed from above the insulating substrate 10. The same applies to the metal foils 10d and 10e. And either metal foil 10c or metal foil 10d and metal foil 10e are electrically connected.

  Subsequently, a paste-like solder material 11a is selectively printed on the metal foils 10c, 10d, and 10e. Note that the solder material 11a is made of, for example, tin-silver-based lead-free. In addition, the solder material 11a may be placed on the metal foils 10c and 10d instead of a paste.

Then, the insulating substrate 10 is placed in the lower jig 53.
FIG. 14 is a schematic cross-sectional view of the relevant part for explaining one step in the method for manufacturing a semiconductor device.
Next, the printed circuit board 30 in which the semiconductor element 20 is bonded to the post electrode 30e is disposed so as to face the insulating substrate 10 placed in the lower jig 53. At this time, the semiconductor element 20 and the solder material 11a come into contact with each other. Further, the lower jig 53 fixes the outer peripheral edge of the printed circuit board 30 in which the insulating substrate 10 and the semiconductor element 20 are bonded to the post electrode 30e.

Then, a solder material 13 a is applied to the upper edge of the through hole 36 of the printed circuit board 30.
FIG. 15 is a schematic cross-sectional view of the relevant part for explaining one step in the method for manufacturing a semiconductor device.
Next, the upper jig 54 made of carbon is fitted into the lower jig 53. Then, the lead frame 60 for external connection terminals is inserted into the through hole 38 provided in the upper jig 54, and the lead frame 60 is further passed through the through hole 36 of the printed circuit board 30, and one end of the lead frame 60 is made of metal. It is made to contact on the solder material 11a arrange | positioned on the foil 10e.

  Subsequently, the insulating substrate 10, the printed circuit board 30 and the like sandwiched between the upper jig 54 and the lower jig 53 are installed in a heating furnace (not shown) together with the upper jig 54 and the lower jig 53, and the solder materials 11a and 13a. Reflow

  Thereafter, the insulating substrate 10, the printed board 30 and the like are taken out from the upper jig 54 and the lower jig 53, and a paste-like underfill material is put into the gap between the insulating board 10 and the printed board 30 from the through hole 32. The underfill material is cured, and the gap between the insulating substrate 10 and the printed circuit board 30 is sealed with the underfill material 40.

Further, after that, the integrated insulating substrate 10 and the printed circuit board 30 are packaged by the resin case with the underfill material 40.
The integrated insulating substrate 10 and the printed circuit board 30 are accommodated in the resin case 70 made of PPS by the underfill material 40, and, for example, a gel mainly composed of silicone is formed on the inner surface of the resin case 70. Alternatively, the sealing material 41 made of epoxy resin is filled and solidified.

Thereby, a semiconductor module having the same configuration as that of the semiconductor module 2 shown in FIG. 10 is completed.
According to such a manufacturing method, the reflow processing of the solder materials 11a, 12a, and 13a is performed twice, and the semiconductor element 20 and the metal foils 10c and 10d, the post electrode 30e, the main electrode and the control electrode of the semiconductor element 20 (illustrated) Not)), one end of the lead frame 60 and the metal foil 10e are joined via the solder layers 11, 12, and 13.

  In particular, in the manufacturing method of the present embodiment, as shown in FIG. 11, the outer peripheral ends of the semiconductor element 20 and the printed circuit board 30 are fixed by the lower jig 52, and the post is positioned on the main electrode and the control electrode of the semiconductor element 20. The solder material 12a is reflowed while the electrode 30e is securely fixed. Therefore, even if the solder material 12a located under each post electrode 30e is melted by reflow, the semiconductor element 20 is not displaced relative to the metal foils 10c and 10d during reflow.

  Further, as shown in FIG. 15, the outer peripheral ends of the insulating substrate 10 and the printed circuit board 30 are fixed by the lower jig 53 and the upper jig 54, and the positions of the main electrode (collector electrode) of the semiconductor element 20 and the metal foils 10c and 10d are fixed. Alternatively, the solder materials 11a and 13a are reflowed while the positions of the lead frame 60 and the metal foil 10e are securely fixed. Therefore, the positional deviation of the semiconductor element 20 with respect to the metal foils 10c and 10d and the positional deviation of the lead frame 60 with respect to the metal foil 10e, which are generated at the time of reflow, are reliably prevented.

  In addition, as a method of electrically connecting the post electrodes 30e and 30g and the main electrode or control electrode of the semiconductor element 20, or the post electrode 30e and the anode side of the semiconductor element 21, a direct connection between metals is used instead of solder bonding. Bonding may be used. Such a bonding method is a method such as ultrasonic bonding or pressure welding.

  In the case of ultrasonic bonding, for example, the post electrodes 30e and 30g can be bonded onto the semiconductor elements 20 and 21 at a frequency of 20 KHz, a load of 40 kgf, and a time of 0.3 sec. At this time, the thickness of the aluminum electrode film formed on the surface electrodes of the semiconductor elements 20 and 21 is 5 to 20 μm. Alternatively, in the case of ultrasonic bonding, copper plating may be performed on the aluminum electrode films of the semiconductor elements 20 and 21 in advance.

  In the case of pressure welding, the roughness of the bonding surface between the surface electrodes of the semiconductor elements 20 and 21 and the post electrode 30e is processed to about 100 nm with a CMP (Chemical Mechanical Polishing) apparatus, and then the processed surface is inactive. It is activated and cleaned in an atmosphere to obtain a rough surface of 10 nm or less. Then, the semiconductor elements 20 and 21 and the joint surface of the post electrode 30e are overlapped and a metal bond or the like is formed between them by applying pressure. Note that heat treatment may be performed depending on the surface state.

These methods can also be used for joining the other main electrode of the semiconductor element 20 to the metal foils 10c and 10d.
Next, a modified example of the structure of the semiconductor device 1 will be illustrated.

<First Modification>
FIG. 16 is a schematic cross-sectional view of the relevant part for explaining a modification of the structure of the semiconductor device.
As shown in the figure, in this embodiment, the surface roughness of the emitter electrode 20a, which is the main electrode of the semiconductor element 20, is adjusted, and such a predetermined roughness is formed on the surface of the emitter electrode 20a. The distance between the electrode 30e and the emitter electrode 20a is further shortened.

Thereby, the thickness of the solder layer 12 can be further reduced, and the heat conduction between the semiconductor element 20 and the printed board 30 is improved. As a result, the heat dissipation of the semiconductor element 20 is improved.
Moreover, since the thickness of the solder layer 12 becomes thinner, the electrical resistance is reduced. Furthermore, the anchor effect is promoted by the surface structure of the emitter electrode 20a, and the solder layer 12 and the emitter electrode 20a are firmly bonded.

  Such roughness may also be formed at the lower end of the post electrode 30e. Thereby, the thickness of the solder layer 12 can be further reduced, and the heat conduction between the semiconductor element 20 and the printed board 30 is further improved. As a result, the heat dissipation of the semiconductor element 20 is further improved.

<Second Modification>
FIG. 17 is a schematic cross-sectional view of the relevant part for explaining a modification of the structure of the semiconductor device.
As shown in the figure, in this embodiment, a flat metal foil 30ba that is electrically connected to an emitter electrode of a semiconductor element (for example, an IGBT element, a power MOSFET element, etc.) 20 via a post electrode 30e, and a collector of the semiconductor element 20 The electrode is disposed so that the post electrode 10 ca and the flat metal foil 30 ca conducted through the metal foil 10 c are opposed to each other in the printed circuit board 30. That is, it arrange | positions so that metal foil 30ca may overlap in the position under metal foil 30ba. Then, the lead frame 61 that conducts to the metal foil 30ba and the lead frame 62 that conducts to the metal foil 30ca are inserted into and installed in the printed circuit board 30.

  According to such a structure, for example, when the lead frame 61 is a positive electrode and the lead frame 62 is a negative electrode, the magnetic field radiated from the metal foil 30ba and the magnetic field radiated from the metal foil 30ca cancel each other, and the parasitic inductor is Can be reduced. Thereby, the surge voltage applied to the semiconductor element 20 is reduced, and the semiconductor element 20 can be stably operated.

In the modification of the present embodiment, a semiconductor element (FWD element) 21 may be used instead of the semiconductor element 20.
Further, the arrangement of the metal foil 30ba and the metal foil 30ca may be a three-dimensional twisted structure. This structure is shown in FIG. 18 as a third modification.

<Third Modification>
FIG. 18 is a main part schematic diagram for explaining a modification of the structure of the semiconductor device.
As illustrated, in this embodiment, the arrangement of the metal foil 30ba and the metal foil 30ca is a three-dimensional twisted structure. Here, FIG. (A) shows the arrangement of only the metal foil 30ba and the metal foil 30ca, and FIG. (B) shows the structure of the printed circuit board 30 at the position between A and B in FIG. (A). Has been. However, in the figure (B), only the cross-sectional part in the figure (A) of the metal foil 30ca is shown.

  For example, the metal foil 30ba is three-dimensionally arranged so that the resin layer 30a is sandwiched therebetween and intersects with the metal foil 30ca, and all the metal foils 30ba are electrically integrated via the post electrodes 30n. Communicating with Although not shown in detail, the metal foil 30ca has a similar structure.

  According to such a structure, the metal foil 30ba and the metal foil 30ca form a twisted structure, the magnetic field radiated from the metal foil 30ba and the magnetic field radiated from the metal foil 30ca cancel each other, and the parasitic inductor is reduced. be able to. In particular, the twisted structure promotes a magnetic field confinement effect and efficiently cancels the magnetic field. Thereby, the surge voltage applied to the semiconductor element 20 is further reduced, and the semiconductor element 20 can be stably operated.

  Further, anchors may be formed on the metal foils 30b, 30c, 30j, 30ja, 30jb, 30jc, 30m, 30ba, and 30ca disposed on the printed circuit board 30 in order to prevent the protective layer 31 from being peeled off. The structure is shown in FIG. 19 as a fourth modification, taking the metal foils 30b and 30c as an example.

<Fourth Modification>
FIG. 19 is a main part schematic diagram for explaining a modification of the structure of the semiconductor device. Here, in FIG. 1A, a schematic top view of the main part of the printed circuit board 30 is shown, and in FIG. 1B, a schematic cross-sectional view of the main part of the printed circuit board 30 is shown. In FIG. (A), the protective layer 31 is not shown in order to clearly represent the pattern shape of the metal foil 30b.

As illustrated, in this embodiment, a plurality of hole portions 30bb are provided in the metal foil 30b. A protective layer 31 is formed on the metal foil 30b.
According to such a structure, the protective layer 31 goes around in the hole 30bb, and peeling of the protective layer 31 from the metal foil 30b can be suppressed by the anchor effect by the hole 30bb.

Note that the shape of the hole 30bb viewed from above is not limited to a rectangular shape, and may be a polygonal shape other than the rectangular shape, a circular shape, or the like.
Further, in the drawing, as an example, a through-hole penetrating from the surface of the metal foil 30b to the resin layer 30a is shown, but a structure that does not particularly penetrate may be used. For example, the hole 30bb having a concave cross section may be used.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor module 10 Insulating substrate 10a Insulating plate 10b, 10c, 10d, 10e, 30b, 30c, 30ba, 30ca, 30j, 30ja, 30jb, 30jc, 30k, 30l, 30m, 37 Metal foil 10ca, 30e, 30g , 30n Post electrode 11, 12, 13, 30i Solder layer 11a, 12a, 13a Solder material 20a Emitter electrode 20, 21 Semiconductor element 30 Printed circuit board 30a Resin layer 30d, 30f Through hole 30h Cylindrical plated layer 30bb Hole 31 Protective layer 32, 36, 38 Through hole 33 IC circuit part 34 Capacitor part 35 Resistor part 40 Underfill material 41 Sealing material 50, 52, 53 Lower jig 51, 54 Upper jig 60, 61, 62 Lead frame 70 Resin case

Claims (5)

An insulating plate;
A metal foil formed on the first main surface of the insulating plate;
At least one other metal foil formed on the second main surface of the insulating plate;
At least one semiconductor element bonded on said another metal foil;
A printed circuit board disposed to face the second main surface of the insulating plate on which the semiconductor element is disposed;
A metal foil formed on the first main surface of the printed circuit board; at least one other metal foil formed on the second main surface of the printed circuit board; and at least one main electrode of the semiconductor element. A plurality of post electrodes formed on the printed circuit board so as to be electrically connected, the cylindrical plating layer being injected and fixed halfway through a through hole provided on the inner wall, and having an elongated shape;
A semiconductor device comprising: A first metal foil selectively disposed on the first main surface of the resin layer; a second metal foil selectively disposed on the second main surface of the resin layer; and a cylindrical plating layer. A printed circuit board comprising a through hole provided in an inner wall, and a plurality of post electrodes that are injected and fixed halfway through the through hole, are electrically connected to the first metal foil and the second metal foil, and have an elongated shape The printed circuit board and the semiconductor element are arranged such that the lower end of the post electrode faces the first main electrode of the semiconductor element, and the lower end of the post electrode and the first main electrode are arranged. Electrically connecting and
An insulating plate, a third metal foil formed on the first main surface of the insulating plate, and at least one fourth metal foil formed on the second main surface of the insulating plate. Preparing an insulating substrate; and
The semiconductor element is placed on the fourth metal foil so that the second main electrode side of the semiconductor element is in contact, and the fourth metal foil and the second main electrode are electrically connected. Process,
A method for manufacturing a semiconductor device, comprising:   The method of manufacturing a semiconductor device according to claim 2, wherein the second metal foil is formed to correspond to the first metal foil. An insulating plate;
A metal foil formed on the first main surface of the insulating plate;
At least one other metal foil formed on the second main surface of the insulating plate;
At least one semiconductor element bonded on said another metal foil;
A printed circuit board disposed to face the second main surface of the insulating plate on which the semiconductor element is disposed;
A metal foil formed on the first main surface of the printed circuit board; at least one other metal foil formed on the second main surface of the printed circuit board; and at least one main electrode of the semiconductor element. A plurality of posts having a diameter of 0.3 to 0.6 mm, in which a cylindrical plating layer formed on the printed circuit board is electrically injected and fixed halfway into a through hole provided on the inner wall so as to be electrically connected Electrodes,
A semiconductor device comprising: 5. The semiconductor device according to claim 1, wherein the post electrode is composed of copper, a copper alloy, aluminum, or an aluminum alloy as a main component.

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