JP2006303223A - Processing method of wafer - Google Patents

Processing method of wafer Download PDF

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JP2006303223A
JP2006303223A JP2005123548A JP2005123548A JP2006303223A JP 2006303223 A JP2006303223 A JP 2006303223A JP 2005123548 A JP2005123548 A JP 2005123548A JP 2005123548 A JP2005123548 A JP 2005123548A JP 2006303223 A JP2006303223 A JP 2006303223A
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wafer
back surface
semiconductor wafer
strain layer
processing
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Kazuma Sekiya
一馬 関家
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Disco Corp
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Disco Abrasive Systems Ltd
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  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a processing method of a wafer in which a gettering sink effect is sustained while ensuring flexural strength. <P>SOLUTION: The processing method of the wafer for imparting the gettering sink effect to the wafer having a plurality of devices formed on the surface comprises a step for forming a predetermined amount of a strained layer on the rear surface of the wafer by immersing the rear surface of the wafer into liquid mixed with abrasive grains and contained in a processing tub, and imparting an ultrasonic wave to the liquid mixed with abrasive grains so that the mixed abrasive grains act on the rear surface of the wafer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、表面に複数のデバイスが形成された半導体ウエーハ等のウエーハにゲッタリングシンク効果を付与するウエーハの加工方法に関する。   The present invention relates to a wafer processing method for providing a gettering sink effect to a wafer such as a semiconductor wafer having a plurality of devices formed on the surface thereof.

半導体デバイス製造工程においては、略円板形状である半導体ウエーハの表面に格子状に配列されたストリートと呼ばれる切断予定ラインによって多数の矩形領域を区画し、該矩形領域の各々にIC、LSI等のデバイスを形成する。このように多数のデバイスが形成された半導体ウエーハをストリートに沿って切断することにより、個々の半導体チップを形成する。半導体チップの小型化および軽量化を図るために、通常、半導体ウエーハをストリートに沿って切断して個々の矩形領域を切断するのに先立って、半導体ウエーハの裏面を研削して所定の厚さに形成している。   In the semiconductor device manufacturing process, a large number of rectangular areas are defined by planned cutting lines called streets arranged in a lattice pattern on the surface of a semiconductor wafer having a substantially disk shape, and each of the rectangular areas includes IC, LSI, etc. Form the device. Individual semiconductor chips are formed by cutting the semiconductor wafer formed with a large number of devices along the streets. In order to reduce the size and weight of the semiconductor chip, the semiconductor wafer is usually cut along the streets to cut the individual rectangular regions, and the back surface of the semiconductor wafer is ground to a predetermined thickness. Forming.

半導体ウエーハの裏面の研削は、通常、ダイヤモンド砥粒をレジンボンドの如き適宜のボンドで固着して形成した研削砥石を、高速回転せしめながら半導体ウエーハの裏面に押圧せしめることによって遂行されている。このような研削方式によって半導体ウエーハの裏面を研削すると、半導体ウエーハの裏面に1μm程度のマイクロクラックからなる加工歪層が生成され、特に半導体ウエーハの厚さを100μm以下に研削した場合には加工歪層によって個々に分割された半導体チップの抗折強度が相当低減される。   The grinding of the back surface of the semiconductor wafer is usually performed by pressing a grinding wheel formed by fixing diamond abrasive grains with an appropriate bond such as a resin bond against the back surface of the semiconductor wafer while rotating at high speed. When the back surface of the semiconductor wafer is ground by such a grinding method, a processing strain layer composed of microcracks of about 1 μm is generated on the back surface of the semiconductor wafer, and particularly when the thickness of the semiconductor wafer is ground to 100 μm or less, the processing strain is generated. The bending strength of the semiconductor chips individually divided by the layers is considerably reduced.

この研削された半導体ウエーハの裏面に生成される加工歪層を除去する対策として、研削された半導体ウエーハの裏面にポリッシングなどの研磨或いはウエットエッチング、ドライエッチングを施している。(例えば、特許文献1、特許文献2参照)。
特開2002−283211号公報 特開2001−85385号公報
As a countermeasure for removing the processing strain layer generated on the back surface of the ground semiconductor wafer, polishing such as polishing, wet etching, or dry etching is performed on the back surface of the ground semiconductor wafer. (For example, refer to Patent Document 1 and Patent Document 2).
JP 2002-28311 A JP 2001-85385 A

而して、本発明者らの研究によれば、DRAM(Dynamic
Random Access memory)やフラッシュメモリーのようにメモリー素子を含むデバイスが形成されたウエーハの場合、ウエーハの裏面を研削した後に研磨或いはエッチング等によって研削によって生成された加工歪層を除去すると、メモリー機能が低下することが判明した。ウエーハの製造工程において半導体の内部に含有した銅(Cu)等の金属原子は、ウエーハの裏面側に偏って存在している。しかるに、ウエーハの裏面に生成された加工歪層を除去すると、加工歪層によるゲッタリングシンク(gettering sink)効果が消失され含有していた銅(Cu)等の金属原子がデバイスの近傍に遊動してメモリー機能に悪影響を及ぼすためと考えられる。
Thus, according to the study by the present inventors, DRAM (Dynamic
In the case of a wafer in which a device including a memory element such as a Random Access memory or a flash memory is formed, the memory function can be achieved by removing the processing strain layer generated by grinding by polishing or etching after grinding the back surface of the wafer. It turned out to be reduced. In the wafer manufacturing process, metal atoms such as copper (Cu) contained in the semiconductor are present on the back side of the wafer. However, when the processing strain layer generated on the back surface of the wafer is removed, the gettering sink effect due to the processing strain layer disappears and the contained metal atoms such as copper (Cu) move to the vicinity of the device. This may be due to adversely affecting the memory function.

本発明は上記事実に鑑みてなされたものであり、その主たる技術課題は、ゲッタリングシンク効果を維持し、抗折強度を確保することができるウエーハの加工方法を提供することにある。   The present invention has been made in view of the above facts, and a main technical problem thereof is to provide a wafer processing method capable of maintaining the gettering sink effect and ensuring the bending strength.

上記主たる技術課題を解決するため、本発明によれば、表面に複数のデバイスが形成されたウエーハにゲッタリングシンク効果を付与するウエーハの加工方法であって、
処理槽に収容され砥粒が混入された液体にウエーハの裏面を浸漬し、砥粒が混入された液体に超音波を付与することにより液体に混入された砥粒をウエーハの裏面に作用せしめ、ウエーハの裏面に所定量の歪層を形成する歪層形成工程を実施する、
ことを特徴とするウエーハの加工方法が提供される。
In order to solve the main technical problem, according to the present invention, a wafer processing method for providing a gettering sink effect to a wafer having a plurality of devices formed on a surface thereof,
Immerse the back surface of the wafer in the liquid contained in the treatment tank and mixed with abrasive grains, and apply the ultrasonic waves to the liquid mixed with abrasive grains to make the abrasive particles mixed in the liquid act on the back surface of the wafer, A strain layer forming step of forming a predetermined amount of strain layer on the back surface of the wafer;
A method for processing a wafer is provided.

また、本発明によれば、上記歪層形成工程を実施する前に、ウエーハの裏面を研削しウエーハを所定の厚さに形成する研削工程と、該研削工程が実施されることによりウエーハの裏面に生成された加工歪層を除去する加工歪層除去工程とを実施する、ウエーハの加工方法が提供される。   Further, according to the present invention, before performing the strain layer forming step, the back surface of the wafer is formed by grinding the back surface of the wafer to form the wafer to a predetermined thickness. And a processing strain layer removing step of removing the processing strain layer generated on the wafer.

本発明によれば、処理槽に収容され砥粒が混入された液体にウエーハの裏面を浸漬し、砥粒が混入された液体に超音波を付与することにより液体に混入された砥粒をウエーハの裏面に作用せしめ、ウエーハの裏面に所定量の歪層を形成するので、ゲッタリングシンク効果を維持し、抗折強度を確保することができる。
また、本発明によるウエーハの加工方法においては、ウエーハの裏面を研削して所定の厚さに形成し、加工歪層除去工程を実施して研削加工歪を除去した後に、歪層形成工程を実施するので、所定量の歪層をバラツキなく形成することができる。従って、ゲッタリングシンク効果および抗折強度が安定したチップを得ることができる。
According to the present invention, the backside of a wafer is immersed in a liquid contained in a processing tank and mixed with abrasive grains, and ultrasonic waves are applied to the liquid mixed with abrasive grains to remove the abrasive grains mixed into the liquid from the wafer. Since a predetermined amount of a strained layer is formed on the back surface of the wafer, the gettering sink effect can be maintained and the bending strength can be ensured.
In the wafer processing method according to the present invention, the back surface of the wafer is ground to form a predetermined thickness, and after the processing strain layer removal step is performed to remove the grinding processing strain, the strain layer formation step is performed. Therefore, a predetermined amount of the strained layer can be formed without variation. Therefore, a chip having a stable gettering sink effect and bending strength can be obtained.

以下、本発明によるウエーハの加工方法の好適な実施形態について、添付図面を参照して更に詳細に説明する。   Preferred embodiments of a wafer processing method according to the present invention will be described below in more detail with reference to the accompanying drawings.

図1には、本発明に従って加工されるウエーハとしての半導体ウエーハの斜視図が示されている。図1に示す半導体ウエーハ2は、シリコンウエーハからなっており、表面2aに複数のストリート21が格子状に形成されているとともに、該複数のストリート21によって区画された複数の領域にデバイス22が形成されている。このように構成された半導体ウエーハ2の表面2aには、図2に示すように保護部材3を貼着する(保護部材貼着工程)。   FIG. 1 shows a perspective view of a semiconductor wafer as a wafer to be processed according to the present invention. A semiconductor wafer 2 shown in FIG. 1 is made of a silicon wafer, and a plurality of streets 21 are formed in a lattice shape on the surface 2a, and devices 22 are formed in a plurality of regions partitioned by the plurality of streets 21. Has been. As shown in FIG. 2, the protective member 3 is stuck to the surface 2a of the semiconductor wafer 2 configured as described above (protective member sticking step).

保護部材貼着工程を実施することにより半導体ウエーハ2の表面2aに保護部材3を貼着したならば、半導体ウエーハ2の裏面2bを研削して半導体ウエーハ2を所定の厚さに形成する研削工程を実施する。この研削工程は、図3に示す研削装置4によって実施する。即ち、研削装置4のチャックテーブル41上に半導体ウエーハ2の保護部材3側を載置し(従って、半導体ウエーハ2は裏面2bが上側となる)、図示しない吸引手段によってチャックテーブル41上に半導体ウエーハ2を吸着保持する。そして、チャックテーブル41を例えば300rpmで回転しつつ、研削砥石42を備えた研削ホイール43を6000rpmで回転せしめて半導体ウエーハ2の裏面2bに接触することにより、所定の厚さ、例えば100μmになるまで研削する。このようにして研削工程を実施すると、半導体ウエーハ2の裏面2bには研削によって厚さが1μm程度の加工歪層が生成される。   If the protective member 3 is attached to the front surface 2a of the semiconductor wafer 2 by performing the protective member attaching step, the grinding step of grinding the back surface 2b of the semiconductor wafer 2 to form the semiconductor wafer 2 to a predetermined thickness. To implement. This grinding process is performed by the grinding apparatus 4 shown in FIG. That is, the protective member 3 side of the semiconductor wafer 2 is placed on the chuck table 41 of the grinding apparatus 4 (therefore, the back surface 2b of the semiconductor wafer 2 is on the upper side), and the semiconductor wafer is placed on the chuck table 41 by suction means (not shown). 2 is adsorbed and held. Then, while rotating the chuck table 41 at, for example, 300 rpm, the grinding wheel 43 provided with the grinding wheel 42 is rotated at 6000 rpm to contact the back surface 2b of the semiconductor wafer 2 until a predetermined thickness, for example, 100 μm is reached. Grind. When the grinding process is performed in this manner, a work strain layer having a thickness of about 1 μm is generated on the back surface 2b of the semiconductor wafer 2 by grinding.

上述した研削工程を実施したならば、半導体ウエーハ2の裏面2bに生成された加工歪層を除去する加工歪層除去工程を実施する。この加工歪層除去工程は例えば図4に示す研磨装置5によって実施する。即ち、研磨装置5のチャックテーブル51上に上述した研削工程が実施された半導体ウエーハ2の保護部材3側を載置し(従って、半導体ウエーハ2は裏面2bが上側となる)、図示しない吸引手段によってチャックテーブル51上に半導体ウエーハ2を吸着保持する。そして、チャックテーブル51を例えば300rpmで回転しつつ、フエルト等の柔軟部材に酸化ジルコニア等の砥粒を分散させ適宜のボンド剤で固定した研磨砥石52を備えた研磨工具53を例えば6000rpmで回転せしめて半導体ウエーハ2の裏面2bに接触することにより、半導体ウエーハ2の裏面2bを研磨加工する。この結果、上述した研削工程を実施することによって半導体ウエーハ2の裏面2bに生成された加工歪層が除去される。なお、加工歪層除去工程は、ポリッシング或いはウエットエッチング、ドライエッチング等によって実施してもよい。   If the grinding process mentioned above is implemented, the process distortion layer removal process of removing the process distortion layer produced | generated on the back surface 2b of the semiconductor wafer 2 will be implemented. This processing strain layer removing step is performed by, for example, the polishing apparatus 5 shown in FIG. That is, the protection member 3 side of the semiconductor wafer 2 subjected to the above-described grinding process is placed on the chuck table 51 of the polishing apparatus 5 (therefore, the back surface 2b of the semiconductor wafer 2 is on the upper side), and suction means (not shown) Thus, the semiconductor wafer 2 is sucked and held on the chuck table 51. Then, while rotating the chuck table 51 at, for example, 300 rpm, a polishing tool 53 including a polishing wheel 52 in which abrasive grains such as zirconia oxide are dispersed in a flexible member such as felt and fixed with an appropriate bonding agent is rotated at, for example, 6000 rpm. By contacting the back surface 2b of the semiconductor wafer 2, the back surface 2b of the semiconductor wafer 2 is polished. As a result, the processing strain layer generated on the back surface 2b of the semiconductor wafer 2 is removed by performing the above-described grinding process. The processing strain layer removing step may be performed by polishing, wet etching, dry etching, or the like.

上述したように加工歪層除去工程を実施したならば、加工歪層が除去された半導体ウエーハ2の裏面2bに所定量の歪層を形成する歪層形成工程を実施する。この歪層形成工程は、例えば図5に示す歪層形成装置6によって実施する。図5に示す歪層形成装置6は、基台61と、該基台61の後側面に取付けられた支持側板62と、基台61上に配設された超音波発信器63と、該超音波発信器63上に配設された処理槽64と、被加工物であるウエーハを仮置きする仮置きテーブル65と、被加工物であるウエーハを保持し仮置きテーブル65と処理槽64との間を移動せしめる被加工物保持手段66とからなっている。超音波発信器63は、20kHz〜10MHzの超音波を発振する。上記処理槽64には、砥粒が混入された液体67が収容されている。液体に混入する砥粒は例えば粒径が2μm程度のダイヤモンド砥粒でよく、液体としては水を用いることができる。上記仮置きテーブル65上には、上述した加工歪層除去工程が実施され図示しない搬送手段によって搬送された半導体ウエーハ2が保護部材3を上側にして載置される。   When the processing strain layer removing step is performed as described above, a strain layer forming step for forming a predetermined amount of strain layer on the back surface 2b of the semiconductor wafer 2 from which the processing strain layer has been removed is performed. This strained layer forming step is performed by, for example, the strained layer forming apparatus 6 shown in FIG. A strain layer forming apparatus 6 shown in FIG. 5 includes a base 61, a support side plate 62 attached to the rear side surface of the base 61, an ultrasonic transmitter 63 disposed on the base 61, A processing tank 64 disposed on the sonic wave transmitter 63, a temporary placement table 65 for temporarily placing a wafer as a workpiece, and a temporary placement table 65 for holding a wafer as a workpiece and the treatment bath 64 It consists of a workpiece holding means 66 that moves between them. The ultrasonic transmitter 63 oscillates an ultrasonic wave of 20 kHz to 10 MHz. The processing tank 64 contains a liquid 67 mixed with abrasive grains. The abrasive grains mixed in the liquid may be diamond abrasive grains having a particle diameter of about 2 μm, for example, and water can be used as the liquid. On the temporary placing table 65, the semiconductor wafer 2 carried by the carrying means (not shown) after the above-described processing strain layer removing step is placed with the protective member 3 facing upward.

上記被加工物保持手段66は、吸着パッド661と、該吸着パッド661を支持する支持手段662と、該支持手段662が支持アーム663を介して取付けられた移動ブロック664と、該移動ブロック664を支持側板62の前面に水平方向に配設された一対に案内レール621、621に沿って移動せしめる移動手段665とからなっている。吸着パッド661は、図示しない吸引手段に接続されており、その下面に被加工物であるウエーハを吸引保持する。支持手段662は、図示の実施形態においてはエアシリンダからなっており、そのピストンロッド662aの先端に吸着パッド661が取付けられる。移動ブロック664は、上記一対の案内レール621、621と嵌合する一対の被案内溝664a、664aを備えており、この被案内溝664a、664aを案内レール621、621に嵌合することにより案内レール621、621に移動可能に支持される。移動手段665は、一対の案内レール621と621の間に平行に配設された雄ネジロッド655aと、該雄ネジロッド655aを回転駆動するためのパルスモータ655b等の駆動源を含んでいる。雄ネジロッド655aは、その一端が上記支持側板62に固定された軸受ブロック655cに回転自在に支持されており、その他端が上記パルスモータ655bの出力軸に連結されている。なお、雄ネジロッド655aは、移動ブロック664に形成された貫通雌ネジ穴664bに螺合されている。従って、パルスモータ655bによって雄ネジロッド655aを正転および逆転駆動することにより、移動ブロック664は案内レール621、621に沿って移動せしめられる。   The workpiece holding means 66 includes a suction pad 661, a support means 662 for supporting the suction pad 661, a moving block 664 to which the support means 662 is attached via a support arm 663, and the moving block 664. It comprises moving means 665 for moving along a pair of guide rails 621 and 621 disposed in the horizontal direction on the front surface of the support side plate 62. The suction pad 661 is connected to suction means (not shown), and sucks and holds a wafer as a workpiece on the lower surface thereof. The support means 662 is an air cylinder in the illustrated embodiment, and a suction pad 661 is attached to the tip of the piston rod 662a. The moving block 664 includes a pair of guided grooves 664 a and 664 a that are fitted to the pair of guide rails 621 and 621, and the guided grooves 664 a and 664 a are guided by fitting to the guide rails 621 and 621. The rails 621 and 621 are supported so as to be movable. The moving means 665 includes a male screw rod 655a disposed in parallel between the pair of guide rails 621 and 621, and a drive source such as a pulse motor 655b for rotationally driving the male screw rod 655a. One end of the male screw rod 655a is rotatably supported by a bearing block 655c fixed to the support side plate 62, and the other end is connected to the output shaft of the pulse motor 655b. The male screw rod 655a is screwed into a through female screw hole 664b formed in the moving block 664. Accordingly, the moving block 664 is moved along the guide rails 621 and 621 by driving the male screw rod 655a forward and backward by the pulse motor 655b.

以上のように構成された歪層形成装置6を用いて実施する歪層形成工程について、図5および図6を参照して説明する。
上述した加工歪層除去工程が実施された半導体ウエーハ2は、図示しない搬送手段によって保護部材3を上側にして仮置きテーブル65上に載置される。半導体ウエーハ2が仮置きテーブル65上に載置されたならば、被加工物保持手段66の移動手段665を作動して吸着パッド661を仮置きテーブル65の上方に位置付け、更に支持手段662を作動して吸着パッド661を所定量下降せしめる。そして、図示しない吸引手段を作動し、吸着パッド661によって仮置きテーブル65に載置されている半導体ウエーハ2を吸引保持する。吸着パッド661に半導体ウエーハ2を吸引保持したならば、支持手段662を作動して吸着パッド661を所定量上昇し、更に移動手段665を作動して吸着パッド661を処理槽64の上方に位置付ける。そして、支持手段662を作動し吸着パッド661を所定量下降して、吸着パッド661に吸引保持されている半導体ウエーハ2の裏面2bを処理槽64に収容されている砥粒が混入された液体67に浸漬する。
A strain layer forming step performed using the strain layer forming apparatus 6 configured as described above will be described with reference to FIGS. 5 and 6.
The semiconductor wafer 2 on which the above-described processing strain layer removing step has been performed is placed on the temporary placement table 65 with the protective member 3 facing upward by a conveying means (not shown). When the semiconductor wafer 2 is placed on the temporary placement table 65, the moving means 665 of the workpiece holding means 66 is activated to position the suction pad 661 above the temporary placement table 65, and the support means 662 is further activated. Then, the suction pad 661 is lowered by a predetermined amount. Then, a suction means (not shown) is operated, and the semiconductor wafer 2 placed on the temporary placement table 65 is sucked and held by the suction pad 661. If the semiconductor wafer 2 is sucked and held by the suction pad 661, the support means 662 is operated to raise the suction pad 661 by a predetermined amount, and the moving means 665 is further operated to position the suction pad 661 above the processing bath 64. Then, the support means 662 is operated to lower the suction pad 661 by a predetermined amount, and the back surface 2b of the semiconductor wafer 2 sucked and held by the suction pad 661 is mixed with abrasive 67 contained in the processing tank 64. Immerse in.

次に、超音波発信器63を作動して、処理槽64に収容されている砥粒が混入された液体67に20kHz〜10MHzの超音波を付与する。この結果、液体に混入されている砥粒が遊動し半導体ウエーハ2の裏面2bに作用するので、半導体ウエーハ2の裏面2bには所定量の歪層が形成される(歪層形成工程)。なお、砥粒が混入された液体67に超音波を付与する時間は、数分でよい。   Next, the ultrasonic transmitter 63 is operated to apply an ultrasonic wave of 20 kHz to 10 MHz to the liquid 67 mixed with abrasive grains accommodated in the treatment tank 64. As a result, abrasive grains mixed in the liquid move and act on the back surface 2b of the semiconductor wafer 2, so that a predetermined amount of strain layer is formed on the back surface 2b of the semiconductor wafer 2 (strain layer forming step). The time for applying the ultrasonic wave to the liquid 67 mixed with abrasive grains may be several minutes.

上述したように半導体ウエーハ2の裏面2bに所定量の歪層を形成したならば、支持手段662を作動して半導体ウエーハ2を吸引保持した吸着パッド661を所定量上昇せしめる。そして、移動手段665を作動して吸着パッド661を仮置きテーブル65の上方に位置付け、更に支持手段662を作動して吸着パッド661を所定量下降せしめる。次に、吸着パッド661による吸引保持を解除することにより、吸着パッド661に吸引保持されていた半導体ウエーハ2は仮置きテーブル65上に載置される。   As described above, when a predetermined amount of the strained layer is formed on the back surface 2b of the semiconductor wafer 2, the support means 662 is operated to raise the suction pad 661 that sucks and holds the semiconductor wafer 2 by a predetermined amount. Then, the moving means 665 is operated to position the suction pad 661 above the temporary placement table 65, and the support means 662 is further operated to lower the suction pad 661 by a predetermined amount. Next, the semiconductor wafer 2 suctioned and held by the suction pad 661 is placed on the temporary placement table 65 by releasing the suction holding by the suction pad 661.

以上のようにして、歪層形成工程が実施され仮置きテーブル65上に戻された半導体ウエーハ2は、図示しない搬送手段によってダイシング装置としての例えば切削装置に搬送される。そして、切削装置によって半導体ウエーハ2をストリート21に沿って切断し、個々の半導体チップに分割する。   As described above, the semiconductor wafer 2 that has been subjected to the strain layer forming process and returned to the temporary placement table 65 is transported to a cutting device as a dicing device, for example, by a transport unit (not shown). Then, the semiconductor wafer 2 is cut along the streets 21 by a cutting device and divided into individual semiconductor chips.

実験例1Experimental example 1

厚さ600μmの半導体ウエーハの裏面を研削して厚さを100μmに形成し、透過型電子顕微鏡による観察で1μm程度のマイクロクラックを形成した。このように形成された半導体ウエーハを切削装置によりストリートに沿って切断し、縦10mm、横10mmの半導体チップを製作した。このようにして製作された半導体チップは、上述したゲッタリングシンク(gettering
sink)効果が得られたが、抗折強度が600MPaであった。
The back surface of a 600 μm-thick semiconductor wafer was ground to a thickness of 100 μm, and microcracks of about 1 μm were formed by observation with a transmission electron microscope. The semiconductor wafer thus formed was cut along the streets with a cutting device to produce semiconductor chips of 10 mm length and 10 mm width. The semiconductor chip manufactured in this way is the gettering sink described above.
sink) effect was obtained, but the bending strength was 600 MPa.

実験例2Experimental example 2

厚さ600mの半導体ウエーハの裏面を研削して厚さを100μmに形成し、上述した加工歪層除去工程を実施して研削加工歪を除去した後、上述した歪層形成工程を実施して半導体ウエーハの裏面に透過型電子顕微鏡による観察で0.2μm程度のマイクロクラックを形成した。このように形成された半導体ウエーハを切削装置によりストリートに沿って切断し、縦10mm、横10mmの半導体チップを製作した。このように製作した半導体チップは、上記実験例1によって製作された半導体チップと同等のゲッタリングシンク(gettering sink)効果が得られた。また、実験例2よって製作された半導体チップは、抗折強度が900MPaであった。   The back surface of a semiconductor wafer having a thickness of 600 m is ground to form a thickness of 100 μm, and after the processing strain layer removal step described above is performed to remove the grinding strain, the strain layer formation step described above is performed and the semiconductor is formed. Microcracks of about 0.2 μm were formed on the back surface of the wafer by observation with a transmission electron microscope. The semiconductor wafer thus formed was cut along the streets with a cutting device to produce semiconductor chips of 10 mm length and 10 mm width. The semiconductor chip manufactured in this way has a gettering sink effect equivalent to that of the semiconductor chip manufactured according to Experimental Example 1. In addition, the semiconductor chip manufactured according to Experimental Example 2 had a bending strength of 900 MPa.

以上のように、本発明によって製作された半導体チップ(実験例2)は、従来の方法によって製作された半導体チップ(実験例1)と同等のゲッタリングシンク(gettering sink)効果が得られるとともに、抗折強度が1.5倍となった。
また、本発明によるウエーハの加工方法においては、ウエーハの裏面を研削して所定の厚さに形成し、上述した加工歪層除去工程を実施して研削加工歪を除去した後に、上述した歪層形成工程を実施するので、所定量の歪層をバラツキなく形成することができる。従って、ゲッタリングシンク(gettering sink)効果および抗折強度が安定したチップを得ることができる。
As described above, the semiconductor chip manufactured according to the present invention (Experimental Example 2) has the same gettering sink effect as the semiconductor chip manufactured according to the conventional method (Experimental Example 1). The bending strength was 1.5 times.
In the wafer processing method according to the present invention, the back surface of the wafer is ground to a predetermined thickness, and after the processing strain layer removing step is performed to remove the grinding processing strain, the strain layer described above is used. Since the forming step is performed, a predetermined amount of the strained layer can be formed without variation. Therefore, a chip having a stable gettering sink effect and bending strength can be obtained.

本発明によるウエーハの加工方法によって加工される半導体ウエーハの斜視図。The perspective view of the semiconductor wafer processed by the processing method of the wafer by this invention. 図1に示す半導体ウエーハの表面に保護部材を貼着した状態を示す斜視図。The perspective view which shows the state which affixed the protection member on the surface of the semiconductor wafer shown in FIG. 本発明によるウエーハの加工方法における研削工程の説明図。Explanatory drawing of the grinding process in the processing method of the wafer by this invention. 本発明によるウエーハの加工方法における加工歪層除去工程の説明図。Explanatory drawing of the process distortion layer removal process in the processing method of the wafer by this invention. 本発明によるウエーハの加工方法における歪層形成工程を実施するための歪層形成装置の斜視図。The perspective view of the distortion layer forming apparatus for implementing the distortion layer formation process in the processing method of the wafer by this invention. 本発明によるウエーハの加工方法における歪層形成工程の説明図。Explanatory drawing of the distortion layer formation process in the processing method of the wafer by this invention.

符号の説明Explanation of symbols

2:半導体ウエーハ
21:ストリート
22:デバイス
3:保護部材
4:研削装置
41:研削装置のチャックテーブル
42:研削砥石
43:研削ホイール
5:研磨装置
51:研磨装置のチャックテーブル
52:研磨砥石
53:研磨工具
6:歪層形成装置
63:超音波発信器
64:処理槽
65:仮置きテーブル
66:被加工物保持手段
661:吸着パッド
662:支持手段662
665:移動手段
67:砥粒が混入された液体
2: Semiconductor wafer 21: Street 22: Device 3: Protection member 4: Grinding device 41: Grinding device chuck table 42: Grinding wheel 43: Grinding wheel 5: Polishing device 51: Polishing device chuck table 52: Polishing wheel 53: Polishing tool 6: Strain layer forming device 63: Ultrasonic transmitter 64: Treatment tank 65: Temporary table 66: Workpiece holding means 661: Suction pad 662: Support means 662
665: moving means 67: liquid mixed with abrasive grains

Claims (2)

表面に複数のデバイスが形成されたウエーハにゲッタリングシンク効果を付与するウエーハの加工方法であって、
処理槽に収容され砥粒が混入された液体にウエーハの裏面を浸漬し、砥粒が混入された液体に超音波を付与することにより液体に混入された砥粒をウエーハの裏面に作用せしめ、ウエーハの裏面に所定量の歪層を形成する歪層形成工程を実施する、
ことを特徴とするウエーハの加工方法。
A wafer processing method for providing a gettering sink effect to a wafer having a plurality of devices formed on a surface,
Immerse the back surface of the wafer in the liquid contained in the treatment tank and mixed with abrasive grains, and apply the ultrasonic waves to the liquid mixed with abrasive grains to make the abrasive particles mixed in the liquid act on the back surface of the wafer, A strain layer forming step of forming a predetermined amount of strain layer on the back surface of the wafer;
A method for processing a wafer.
該歪層形成工程を実施する前に、ウエーハの裏面を研削しウエーハを所定の厚さに形成する研削工程と、該研削工程が実施されることによりウエーハの裏面に生成された加工歪層を除去する加工歪層除去工程とを実施する、請求項1記載のウエーハの加工方法。   Before performing the strain layer forming step, a grinding step for grinding the back surface of the wafer to form the wafer to a predetermined thickness, and a processing strain layer generated on the back surface of the wafer by performing the grinding step are performed. The wafer processing method according to claim 1, wherein a processing strain layer removing step of removing is performed.
JP2005123548A 2005-04-21 2005-04-21 Processing method of wafer Pending JP2006303223A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011082470A (en) * 2009-09-11 2011-04-21 Tokyo Seimitsu Co Ltd Method for processing wafer and wafer processing apparatus
JP2015015412A (en) * 2013-07-08 2015-01-22 富士電機株式会社 Semiconductor device
KR101588981B1 (en) * 2014-12-10 2016-01-26 주식회사 엘지실트론 Apparatus for reprocessing a polishing plate
JP2017208466A (en) * 2016-05-19 2017-11-24 株式会社ディスコ Wafer evaluation method
KR20230144467A (en) 2022-04-07 2023-10-16 가부시기가이샤 디스코 Gettering layer forming apparatus and processing apparatus

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JPS5660022A (en) * 1979-10-22 1981-05-23 Nec Corp Processing method and device for semiconductor wafer
JPS5681934A (en) * 1979-12-10 1981-07-04 Hitachi Ltd Formation of semiconductor element
JPH07263453A (en) * 1994-03-25 1995-10-13 Toshiba Corp Semiconductor device and its manufacture
JP2001085385A (en) * 1999-07-14 2001-03-30 Nisso Engineering Co Ltd Method and device for etching silicon
JP2002283211A (en) * 2001-03-28 2002-10-03 Disco Abrasive Syst Ltd Polishing device and grinding/polishing machine including this

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011082470A (en) * 2009-09-11 2011-04-21 Tokyo Seimitsu Co Ltd Method for processing wafer and wafer processing apparatus
JP2015015412A (en) * 2013-07-08 2015-01-22 富士電機株式会社 Semiconductor device
KR101588981B1 (en) * 2014-12-10 2016-01-26 주식회사 엘지실트론 Apparatus for reprocessing a polishing plate
JP2017208466A (en) * 2016-05-19 2017-11-24 株式会社ディスコ Wafer evaluation method
KR20230144467A (en) 2022-04-07 2023-10-16 가부시기가이샤 디스코 Gettering layer forming apparatus and processing apparatus

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