JP2014528115A - 電力効率の優れたプロセッサアーキテクチャ - Google Patents
電力効率の優れたプロセッサアーキテクチャ Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
- H04W88/02—Terminal devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1028—Power efficiency
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/62—Details of cache specific to multiprocessor cache arrangements
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/30—Systems integrating technologies related to power network operation and communication or information technologies for improving the carbon footprint of the management of residential or tertiary loads, i.e. smart grids as climate change mitigation technology in the buildings sector, including also the last stages of power distribution and the control, monitoring or operating management systems at local level
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
Description
Claims (20)
- 命令を実行する第1コアと、
前記第1コアとはヘテロジニアスであり、前記第1コアよりも小さい、命令を実行する第2コアと、
前記第1コア及び前記第2コアが低電力状態にある際に、前記第1コアではなく、前記第2コアを割込みに応答してウェイクアップさせるロジックと
を備える装置。 - 前記ロジックは常に、前記第1コアではなく、前記第2コアを前記割込みに応答してウェイクアップさせる、請求項1に記載の装置。
- 前記ロジックは、前記割込みに応答して、前記第1コアの実行状態のサブセットを前記第2コアに提供する、請求項1または2に記載の装置。
- 前記第2コアは、前記第2コアが前記割込みを処理することができるかどうかを判断し、前記判断の結果が否定的な場合、ウェイクアップ信号を前記第1コアへ送信させる、請求項3に記載の装置。
- 前記第2コアが前記割込みを処理することができないという前記判断に応答して、前記ロジックは、前記第2コアから前記第1コアの前記実行状態の前記サブセットを取得し、前記実行状態の前記サブセットを、一時的記憶領域内に保存されている前記第1コアの前記実行状態の残りの部分とマージする、請求項4に記載の装置。
- 前記装置は、マルチコアプロセッサを備え、
前記マルチコアプロセッサは、
前記第1コア及び前記第2コアと、
電力制御ユニット(PCU)と
を有し、
前記PCUは、前記ロジックを含み、
前記ロジックは、
ウェイクアップロジックと、
状態転送ロジックと、
未定義処理ロジックと、
割込み履歴記憶領域と
を含む、請求項1から5のいずれか1項に記載の装置。 - 前記ロジックに結合されたアクセラレータを更に備え、前記アクセラレータは、タスクを実行し、前記タスクの完了に応じて前記割込みを前記ロジックへ送信する、請求項1から6のいずれか1項に記載の装置。
- 前記第2コアは、前記割込みがデータ移動動作に対する要求を有する際に、前記割込みを処理する、請求項7に記載の装置。
- 前記第2コアは、前記割込みがベクトル演算に対する要求を有する際に、前記第1コアが前記割込みを処理できるようにするために、ウェイクアップ信号を第1コアへ送信させる、請求項7または8に記載の装置。
- 前記ロジックは、前記第2コアから未定義命令障害を受け取り、前記第2コアが前記ベクトル演算を処理することができないと判断し、前記第2コアから実行状態を取得し、前記実行状態を、一時的な記憶領域内に保存されている前記第1コアの実行状態のうち少なくとも一部分とマージし、マージされた前記実行状態を前記第1コアへ送信させる、請求項9に記載の装置。
- 前記ロジックは、複数の割込みを分析し、前記複数の割込みのうち過半数が前記第1コアによって処理されることを要する場合、前記ロジックは、前記割込みに応答して前記第2コアをウェイクアップさせず、その代わりに、前記第1コアをウェイクアップさせる、請求項1から10のいずれか1項に記載の装置。
- 第1の小さなコアと、第1の大きなコアと、アクセラレータとを含むプロセッサのロジック内の前記アクセラレータから、前記第1の小さなコア及び前記第1の大きなコアが低電力状態にある際に、割込みを受け取る段階と、
前記割込みに応答して、レジューム信号を前記第1の小さなコアに対して直接的に送信し、前記第1の大きなコアの実行状態のサブセットを前記第1の小さなコアに対して提供する段階と、
前記第1の小さなコアが前記割込みと関連する要求を処理することができるかどうかを判断し、前記判断の結果が肯定的である場合、前記要求に対応する動作を前記第1の小さなコアで実行する段階と
を備える方法。 - 前記第1の小さなコアが前記要求を処理することができない場合、前記第1の小さなコアから前記実行状態の前記サブセットを取得し、前記実行状態の前記サブセットを前記第1の大きなコアの保存されている実行状態とマージし、ウェイクアップ信号及びマージされた前記実行状態を前記第1の大きなコアに対して送信する段階を更に備える、請求項12に記載の方法。
- その後に、前記要求に対応する前記動作を前記第1の大きなコアで実行する段階を更に備える、請求項13に記載の方法。
- 前記割込みを前記第1の小さなコアと前記第1の大きなコアとのうちどちらに割り当てるべきかを示すヒントと共に前記割込みを受け取る段階を更に備える、請求項12から14のいずれか1項に記載の方法。
- 前記割込みのタイプに基づいて表のエントリにアクセスし、前記エントリに基づいて、前記レジューム信号を前記第1の小さなコアと前記第1の大きなコアとのうちどちらに直接的に送信するのかを判断する段階を更に備える、請求項12から15のいずれか1項に記載の方法。
- マルチコアプロセッサと、
前記マルチコアプロセッサに結合されたダイナミックランダムアクセスメモリ(DRAM)と
を備え、
前記マルチコアプロセッサは、
第1の複数のコアと、
前記第1の複数のコアよりも低い熱設計電力を有する第2の複数のコアと、
アクセラレータと、
電力制御ユニット(PCU)と
を有し、
前記PCUは、前記第1の複数のコア及び前記第2の複数のコアが低電力状態にある際に、前記アクセラレータから割込みを受け取り、前記割込みに応答して、レジューム信号を前記第2の複数のコアのうち第1のコアに対して直接的に送信し、前記第1の複数のコアのうち第1のコアの実行状態のサブセットを前記第2の複数のコアのうち前記第1のコアに提供する、システム。 - 前記第1の複数のコアは、前記第2の複数のコアとはヘテロジニアスの設計を有する、請求項17に記載のシステム。
- 前記第2の複数のコアは、オペレーティングシステム(OS)に対してトランスペアレントである、請求項17または18に記載のシステム。
- 前記PCUは、前記割込みを使用して表のエントリにアクセスし、前記第1の複数のコア又は前記第2の複数のコアの第1のコアに前記レジューム信号を送るか否かを決定し、前記PCUは、前記エントリが、前記第2の複数のコアのうち1つが前記割込みと同一のタイプの以前の割込みに応答して未定義障害に遭遇したことを示す場合、前記レジューム信号を前記第1の複数のコアの前記第1のコアに対して送信する請求項17から19のいずれか1項に記載のシステム。
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JP2016153400A Division JP2017021811A (ja) | 2016-08-04 | 2016-08-04 | 電力効率の優れたプロセッサアーキテクチャ |
JP2016153399A Division JP2016212907A (ja) | 2016-08-04 | 2016-08-04 | 電力効率の優れたプロセッサアーキテクチャ |
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KR (6) | KR101889756B1 (ja) |
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