JP6197196B2 - 電力効率の優れたプロセッサアーキテクチャ - Google Patents
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- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
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- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
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- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/30—Systems integrating technologies related to power network operation and communication or information technologies for improving the carbon footprint of the management of residential or tertiary loads, i.e. smart grids as climate change mitigation technology in the buildings sector, including also the last stages of power distribution and the control, monitoring or operating management systems at local level
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- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D30/00—Reducing energy consumption in communication networks
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Description
Claims (13)
- マルチコアプロセッサを備え、前記マルチコアプロセッサは、
命令を実行する第1コアと、
前記第1コアとはヘテロジニアスであり、前記第1コアよりも小さく、オペレーティングシステムに対してトランスペアレントである、命令を実行する第2コアと、
割込みを受け取り、前記第1コア又は前記第2コアを前記割込みに応答してウェイクアップさせるロジックを含むとともに、システム動作の際に発生した割込みと前記割込みが前記第2コアによって正常に処理されたかどうかとを示すエントリを有する電力制御ユニット(PCU)と、を有し、
前記PCUは、前記第1コア及び前記第2コアが低電力状態にある際に、前記割込みの受け取りに応じて前記エントリに基づいて同一タイプの以前の割込みが前記第2コアによって正常に処理されたかどうかを判断し、前記第2コアによって正常に処理されたと判断した場合、前記割込みを前記第2コアに割り当て、
前記PCUが前記割込みを割り当てた前記第2コアは、前記第2コアが前記割込みを処理することができるかどうかを判断し、前記割込みを処理することができないと判断した場合、信号を前記PCUに送信し、
前記信号を受信した前記PCUは、ウェイクアップ信号を前記第1コアへ送信する、プロセッサ。 - 前記ロジックは、前記割込みに応答して、前記第1コアの実行状態のサブセットを前記第2コアに提供する、請求項1に記載のプロセッサ。
- 前記第2コアが前記割込みを処理することができないという前記判断に応答して、前記ロジックは、前記第2コアから前記第1コアの前記実行状態の前記サブセットを取得し、前記実行状態の前記サブセットを、一時的記憶領域内に保存されている前記第1コアの前記実行状態の残りの部分とマージする、請求項2に記載のプロセッサ。
- 前記ロジックは、
ウェイクアップロジックと、
状態転送ロジックと、
前記第2コアにより発行される未定義障害を受信および処理する未定義処理ロジックと、
前記第2コアにより先の割込みが正常に処理されたかどうかを示す前記エントリを格納する割込み履歴記憶領域と
を含む、請求項1から3のいずれか1項に記載のプロセッサ。 - 前記ロジックに結合されたアクセラレータを更に備え、前記アクセラレータは、タスクを実行し、前記タスクの完了に応じて前記割込みを前記ロジックへ送信する、請求項1から4のいずれか1項に記載のプロセッサ。
- 前記第2コアは、前記割込みがデータ移動動作に対する要求を有する際に、前記割込みを処理する、請求項5に記載のプロセッサ。
- 前記第2コアは、前記割込みがベクトル演算に対する要求を有する際に、前記第1コアが前記割込みを処理できるようにするために、ウェイクアップ信号を第1コアへ送信させる、請求項5または6に記載のプロセッサ。
- 前記ロジックは、前記第2コアから未定義命令障害を受け取り、前記第2コアが前記ベクトル演算を処理することができないと判断し、前記第2コアから実行状態を取得し、前記実行状態を、一時的な記憶領域内に保存されている前記第1コアの実行状態のうち少なくとも一部分とマージし、マージされた前記実行状態を前記第1コアへ送信させる、請求項7に記載のプロセッサ。
- オペレーティングシステムに対してトランスペアレントである第1の小さなコアと、第1の大きなコアと、アクセラレータと、電力制御ユニット(PCU)と、を含むプロセッサのロジック内の前記アクセラレータから、前記PCUにより、前記第1の小さなコア及び前記第1の大きなコアが低電力状態にある際に、割込みを受け取る段階と、
前記PCUにより、前記割込みに応答して、前記割込みのタイプに基づいて表のエントリにアクセスし、前記エントリに基づいて、レジューム信号を前記第1の小さなコアと前記第1の大きなコアとのうちどちらに直接的に送信するのかを判断する段階と、
前記PCUにより、前記レジューム信号を前記第1の小さなコアに対して直接的に送信し、前記第1の大きなコアの実行状態のサブセットを前記第1の小さなコアに対して提供する段階と、
前記第1の小さなコアが前記割込みと関連する要求を処理することができるかどうかを前記レジューム信号を受信した前記第1の小さなコアで判断し、前記要求を処理することができると判断した場合、前記要求に対応する動作を前記第1の小さなコアで実行し、前記要求を処理することができないと判断した場合、前記第1の小さなコアにより信号を前記PCUに送信し、前記信号を受信した前記PCUによりウェイクアップ信号を前記第1の大きなコアに対して送信して、前記要求に対応する動作を前記第1の大きなコアで実行する段階と、
を備え、
前記PCUは、前記エントリに基づいて、前記レジューム信号を前記第1の小さなコアと前記第1の大きなコアとのうちどちらに直接的に送信するのかを判断する場合に、システム動作の際に発生した割込みと、前記割込みが前記第1の小さなコアによって正常に処理されたかどうかと、を示す前記エントリに基づいて、同一タイプの以前の割込みが前記第1の小さなコアによって正常に処理されたかどうかを判断し、前記第1の小さなコアによって正常に処理されたと判断した場合、前記レジューム信号を前記第1の小さなコアに送信することを決定する、方法。 - 前記第1の大きなコアで実行する段階は、前記第1の小さなコアから前記実行状態の前記サブセットを取得し、前記実行状態の前記サブセットを前記第1の大きなコアの保存されている実行状態とマージし、マージされた前記実行状態を前記第1の大きなコアに対して送信する段階を含む、請求項9に記載の方法。
- 前記割込みを受け取る段階は、前記割込みを前記第1の小さなコアと前記第1の大きなコアとのうちどちらに割り当てるべきかを示すヒントを前記割込みと共に受け取る段階を含む、請求項9または10に記載の方法。
- マルチコアプロセッサと、
前記マルチコアプロセッサに結合されたダイナミックランダムアクセスメモリ(DRAM)と
を備え、
前記マルチコアプロセッサは、
第1の複数のコアと、
前記第1の複数のコアよりも低い熱設計電力を有し、オペレーティングシステム(OS)に対してトランスペアレントである第2の複数のコアと、
アクセラレータと、
電力制御ユニット(PCU)と
を有し、
前記PCUは、前記第1の複数のコア及び前記第2の複数のコアが低電力状態にある際に、前記アクセラレータから割込みを受け取り、前記割込みに応答して前記第1の複数のコアの第1のコア又は前記第2の複数のコアの第1のコアにレジューム信号を送るか否かを決定し、該決定に応じて前記レジューム信号を前記第1の複数のコアのうち第1のコアに対して送信する、又は、前記レジューム信号を前記第2の複数のコアのうち第1のコアに対して直接的に送信し、前記第1の複数のコアのうち第1のコアの実行状態のサブセットを前記第2の複数のコアのうち前記第1のコアに提供し、
前記PCUは、前記レジューム信号を送るか否かの決定において、前記割込みを使用して表のエントリにアクセスし、前記エントリが、前記第2の複数のコアのうち1つが前記割込みと同一のタイプの以前の割込みに応答して未定義障害に遭遇したことを示す場合、前記レジューム信号を前記第1の複数のコアの前記第1のコアに対して送信することを決定し、前記エントリが、前記割込みと同一タイプの以前の割込みが前記第2の複数のコアのうちの1つによって正常に処理されたことを示す場合、前記レジューム信号を前記第2の複数のコアの前記第1のコアに対して送信することを決定する、システム。 - 前記第1の複数のコアは、前記第2の複数のコアとはヘテロジニアスの設計を有する、請求項12に記載のシステム。
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