JP2014510403A5 - - Google Patents

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Publication number
JP2014510403A5
JP2014510403A5 JP2013556653A JP2013556653A JP2014510403A5 JP 2014510403 A5 JP2014510403 A5 JP 2014510403A5 JP 2013556653 A JP2013556653 A JP 2013556653A JP 2013556653 A JP2013556653 A JP 2013556653A JP 2014510403 A5 JP2014510403 A5 JP 2014510403A5
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JP
Japan
Prior art keywords
pattern
track
interconnect
tracks
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2013556653A
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English (en)
Japanese (ja)
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JP6134652B2 (ja
JP2014510403A (ja
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Publication date
Priority claimed from US13/410,145 external-priority patent/US8372743B2/en
Application filed filed Critical
Priority claimed from PCT/US2012/027554 external-priority patent/WO2012119105A2/en
Publication of JP2014510403A publication Critical patent/JP2014510403A/ja
Publication of JP2014510403A5 publication Critical patent/JP2014510403A5/ja
Application granted granted Critical
Publication of JP6134652B2 publication Critical patent/JP6134652B2/ja
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JP2013556653A 2011-03-02 2012-03-02 ハイブリッドピッチ分割パターン分割リソグラフィプロセス Active JP6134652B2 (ja)

Applications Claiming Priority (11)

Application Number Priority Date Filing Date Title
US201161448437P 2011-03-02 2011-03-02
US201161448451P 2011-03-02 2011-03-02
US201161448423P 2011-03-02 2011-03-02
US201161448447P 2011-03-02 2011-03-02
US61/448,423 2011-03-02
US61/448,451 2011-03-02
US61/448,447 2011-03-02
US61/448,437 2011-03-02
US13/410,145 US8372743B2 (en) 2011-03-02 2012-03-01 Hybrid pitch-split pattern-split lithography process
US13/410,145 2012-03-01
PCT/US2012/027554 WO2012119105A2 (en) 2011-03-02 2012-03-02 Hybrid pitch-split pattern-split litrography process

Publications (3)

Publication Number Publication Date
JP2014510403A JP2014510403A (ja) 2014-04-24
JP2014510403A5 true JP2014510403A5 (https=) 2015-04-23
JP6134652B2 JP6134652B2 (ja) 2017-05-24

Family

ID=46758517

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2013556909A Active JP6140616B2 (ja) 2011-03-02 2012-03-02 ダブルパターニングされるリソグラフィプロセスのためのパターン分割分解ストラテジー
JP2013556653A Active JP6134652B2 (ja) 2011-03-02 2012-03-02 ハイブリッドピッチ分割パターン分割リソグラフィプロセス

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP2013556909A Active JP6140616B2 (ja) 2011-03-02 2012-03-02 ダブルパターニングされるリソグラフィプロセスのためのパターン分割分解ストラテジー

Country Status (2)

Country Link
JP (2) JP6140616B2 (https=)
WO (2) WO2012119098A2 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9583609B2 (en) * 2013-03-25 2017-02-28 Texas Instruments Incorporated MOS transistor structure and method of forming the structure with vertically and horizontally-elongated metal contacts
CN109983564B (zh) * 2016-11-16 2023-05-02 东京毅力科创株式会社 亚分辨率衬底图案化的方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5561317A (en) * 1990-08-24 1996-10-01 Canon Kabushiki Kaisha Method of manufacturing semiconductor devices
JP3050210B2 (ja) * 1998-09-24 2000-06-12 株式会社ニコン 露光方泡および該方法を用いる素子製造方法
JP4109944B2 (ja) * 2002-09-20 2008-07-02 キヤノン株式会社 固体撮像装置の製造方法
SG126877A1 (en) * 2005-04-12 2006-11-29 Asml Masktools Bv A method, program product and apparatus for performing double exposure lithography
US7824842B2 (en) * 2005-10-05 2010-11-02 Asml Netherlands B.V. Method of patterning a positive tone resist layer overlaying a lithographic substrate
EP1843202B1 (en) * 2006-04-06 2015-02-18 ASML Netherlands B.V. Method for performing dark field double dipole lithography
JP2007294500A (ja) * 2006-04-21 2007-11-08 Nec Electronics Corp 半導体装置およびその製造方法
KR100861363B1 (ko) * 2006-07-21 2008-10-01 주식회사 하이닉스반도체 이중 노광을 위한 패턴분할 방법
JP2006303541A (ja) * 2006-07-28 2006-11-02 Renesas Technology Corp 半導体集積回路装置の製造方法
JP4945367B2 (ja) * 2006-08-14 2012-06-06 エーエスエムエル マスクツールズ ビー．ブイ． 回路パターンを複数の回路パターンに分離する装置および方法
JP2008071838A (ja) * 2006-09-12 2008-03-27 Nec Electronics Corp 半導体装置の製造方法
JP5032948B2 (ja) * 2006-11-14 2012-09-26 エーエスエムエル マスクツールズ ビー．ブイ． Ｄｐｔプロセスで用いられるパターン分解を行うための方法、プログラムおよび装置
JP2008311502A (ja) * 2007-06-15 2008-12-25 Toshiba Corp パターン形成方法
JP5218227B2 (ja) * 2008-12-12 2013-06-26 信越化学工業株式会社 パターン形成方法
KR101532012B1 (ko) * 2008-12-24 2015-06-30 삼성전자주식회사 반도체 소자 및 반도체 소자의 패턴 형성 방법
JP5235719B2 (ja) * 2009-02-27 2013-07-10 株式会社日立ハイテクノロジーズ パターン測定装置

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