JP2014507802A - 本体領域に直接接続されたソースラインを有するメモリ装置および方法 - Google Patents
本体領域に直接接続されたソースラインを有するメモリ装置および方法 Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Abstract
【選択図】図1
Description
Claims (23)
- 第1の端部に接続されたソース領域、および第2の端部に接続されたドレイン領域を有する細長形本体領域と、
複数のゲートのそれぞれが、少なくとも電荷記憶構造により前記細長形本体領域から分離される、前記細長形本体領域の長さに沿った複数のゲートと、
前記本体領域に直接接続されたソースラインと、を備える、
メモリ装置。 - 前記細長形本体領域が垂直方向に方向付けられる、請求項1に記載のメモリ装置。
- 前記細長形本体領域が水平方向に方向付けられる、請求項1に記載のメモリ装置。
- 前記細長形本体領域が“U”字型を形成する、請求項1に記載のメモリ装置。
- 前記細長形本体領域の第1の端部に近接した第1の選択ゲートと、前記細長形本体領域の第2の端部に近接した第2の選択ゲートをさらに備える、請求項1に記載のメモリ装置。
- 第1の端部に接続されたn型ソース領域、および第2の端部に接続されたn型ドレイン領域を有するp型細長形本体領域と、
複数のゲートのそれぞれが、少なくともそれぞれの電荷記憶構造により前記p型本体領域から分離される、前記p型細長形本体領域の長さに沿った複数のゲートと
前記本体領域の第1の端部に近接した第1の選択ゲートと、
前記本体領域の第2の端部に近接した第2の選択ゲートと、
前記本体領域の端部において前記p型細長形本体領域に直接接続されたソースラインと、を備え、
前記n型ソース領域が、前記p型細長形本体領域の端部の断面を実質的に取り囲み、また前記ソースラインに接続される、
メモリ装置。 - 前記p型細長形本体領域の少なくとも前記端部が、p+型のドープされたポリシリコンから形成される、請求項6に記載のメモリ装置。
- 前記n型ソース領域が、n+型のポリシリコンから形成される、請求項6に記載のメモリ装置。
- 前記n型ドレイン領域が、n+型のポリシリコンから形成される、請求項6に記載のメモリ装置。
- 前記p型細長形本体領域が、“U”字型を形成する、請求項6に記載のメモリ装置。
- 前記ソースラインが、前記n型ソース領域の頂部上に積み重ねられる、請求項10に記載のメモリ装置。
- 第1および第2の上方に向いた端部を有する細長形本体領域と、
第1の上方に向いた端部に接続されたドレイン領域と、
第2の上方に向いた端部に接続されたソース領域と、
前記細長形本体領域の長さに沿った複数のゲートと、を備える
U字型のメモリセルストリングと、
前記ドレイン領域に接続されたデータラインと、
前記細長形本体領域の前記第2の上方に向いた端部に直接接続され、かつ前記ソース領域に接続されたソースラインと、を備える、
メモリ装置。 - 前記ソースラインおよび前記ソース領域が、近接したメモリセルストリングと共用される、請求項12に記載のメモリ装置。
- 前記ソース領域が、前記細長形本体領域の前記第2の上方に向いた端部の断面を実質的に取り囲む、請求項12に記載のメモリ装置。
- 前記ゲートが、近接したメモリセルストリングと共用される、請求項12に記載のメモリ装置。
- 前記ゲートの第1の部分が、第1の近接したメモリセルストリングと共用され、前記ゲートの第2の部分が、第2の近接したメモリセルストリングと共用される、請求項14に記載のメモリ装置。
- 複数のゲートを第1の電圧にバイアスするステップと、
ソースラインを第2の電圧にバイアスするステップと、を含み、
前記ソースラインはストリングの細長形本体領域に直接接続され、前記第2の電圧は前記第1の電圧と異なる、
メモリセルストリングを消去する方法。 - 前記複数のゲートを前記第1の電圧にバイアスするステップが、前記複数のゲートをおよそゼロボルトにバイアスするステップを含む、
請求項17に記載の方法。 - 前記ソースライン電圧を前記第2の電圧にバイアスするステップが、前記ソースライン電圧をおよそ20ボルトにバイアスするステップを含む、請求項17に記載の方法。
- データラインを浮遊させるステップをさらに含み、前記ソースラインをバイアスするステップが、前記データラインをおよそ前記第1の電圧に接続する、請求項17に記載の方法。
- 前記ストリングの選択ゲートを浮遊させるステップをさらに含む、請求項17に記載の方法。
- 複数のゲートを第1の電圧にバイアスするステップと、
プログラミングのため選択されたゲートを第2の電圧にバイアスするステップと、
ソースラインを第3の電圧にバイアスするステップと、を含み、
前記ソースラインはストリングの細長形本体領域に直接接続され、前記第2の電圧は前記第1の電圧と異なる、
メモリセルストリングのプログラミング方法。 - 前記ソースラインを第3の電圧にバイアスするステップが、ソースラインをおよそゼロボルトにバイアスするステップを含む、請求項22に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US13/011,223 US8750040B2 (en) | 2011-01-21 | 2011-01-21 | Memory devices having source lines directly coupled to body regions and methods |
US13/011,223 | 2011-01-21 | ||
PCT/US2012/021873 WO2012100056A2 (en) | 2011-01-21 | 2012-01-19 | Memory devices having source lines directly coupled to body regions and methods |
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JP2014507802A true JP2014507802A (ja) | 2014-03-27 |
JP5923114B2 JP5923114B2 (ja) | 2016-05-24 |
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US (7) | US8750040B2 (ja) |
JP (1) | JP5923114B2 (ja) |
CN (2) | CN108694978B (ja) |
TW (1) | TWI525623B (ja) |
WO (1) | WO2012100056A2 (ja) |
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JP2010225946A (ja) * | 2009-03-24 | 2010-10-07 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
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US20170047120A1 (en) | 2017-02-16 |
US8750040B2 (en) | 2014-06-10 |
TW201237874A (en) | 2012-09-16 |
CN103329270B (zh) | 2018-04-24 |
US20140286106A1 (en) | 2014-09-25 |
JP5923114B2 (ja) | 2016-05-24 |
US20230317172A1 (en) | 2023-10-05 |
US9997247B2 (en) | 2018-06-12 |
US20210043259A1 (en) | 2021-02-11 |
US20120188825A1 (en) | 2012-07-26 |
CN108694978A (zh) | 2018-10-23 |
US9484100B2 (en) | 2016-11-01 |
CN108694978B (zh) | 2022-05-10 |
US10825528B2 (en) | 2020-11-03 |
US20180268909A1 (en) | 2018-09-20 |
US11361827B2 (en) | 2022-06-14 |
US11705205B2 (en) | 2023-07-18 |
WO2012100056A3 (en) | 2012-11-15 |
WO2012100056A2 (en) | 2012-07-26 |
TWI525623B (zh) | 2016-03-11 |
US20220246215A1 (en) | 2022-08-04 |
CN103329270A (zh) | 2013-09-25 |
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