JP2014500993A5 - - Google Patents
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- JP2014500993A5 JP2014500993A5 JP2013532870A JP2013532870A JP2014500993A5 JP 2014500993 A5 JP2014500993 A5 JP 2014500993A5 JP 2013532870 A JP2013532870 A JP 2013532870A JP 2013532870 A JP2013532870 A JP 2013532870A JP 2014500993 A5 JP2014500993 A5 JP 2014500993A5
- Authority
- JP
- Japan
- Prior art keywords
- registers
- physical
- instruction
- register
- architected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000013507 mapping Methods 0.000 claims 10
- 230000004044 response Effects 0.000 claims 9
- 238000000034 method Methods 0.000 claims 6
- 238000004519 manufacturing process Methods 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 claims 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/900,124 US9626190B2 (en) | 2010-10-07 | 2010-10-07 | Method and apparatus for floating point register caching |
| US12/900,124 | 2010-10-07 | ||
| PCT/US2011/054688 WO2012047833A1 (en) | 2010-10-07 | 2011-10-04 | Method and apparatus for floating point register caching |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2014500993A JP2014500993A (ja) | 2014-01-16 |
| JP2014500993A5 true JP2014500993A5 (enExample) | 2014-11-20 |
| JP5703382B2 JP5703382B2 (ja) | 2015-04-15 |
Family
ID=44863229
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013532870A Active JP5703382B2 (ja) | 2010-10-07 | 2011-10-04 | 浮動小数点レジスタキャッシングのための方法及び装置 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US9626190B2 (enExample) |
| EP (1) | EP2625599B1 (enExample) |
| JP (1) | JP5703382B2 (enExample) |
| KR (1) | KR101797187B1 (enExample) |
| CN (1) | CN103262028B (enExample) |
| WO (1) | WO2012047833A1 (enExample) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8914615B2 (en) * | 2011-12-02 | 2014-12-16 | Arm Limited | Mapping same logical register specifier for different instruction sets with divergent association to architectural register file using common address format |
| US9632947B2 (en) * | 2013-08-19 | 2017-04-25 | Intel Corporation | Systems and methods for acquiring data for loads at different access times from hierarchical sources using a load queue as a temporary storage buffer and completing the load early |
| CN105993000B (zh) * | 2013-10-27 | 2021-05-07 | 超威半导体公司 | 用于浮点寄存器混叠的处理器和方法 |
| JP6493088B2 (ja) * | 2015-08-24 | 2019-04-03 | 富士通株式会社 | 演算処理装置及び演算処理装置の制御方法 |
| US10838733B2 (en) | 2017-04-18 | 2020-11-17 | International Business Machines Corporation | Register context restoration based on rename register recovery |
| US10545766B2 (en) | 2017-04-18 | 2020-01-28 | International Business Machines Corporation | Register restoration using transactional memory register snapshots |
| US10649785B2 (en) | 2017-04-18 | 2020-05-12 | International Business Machines Corporation | Tracking changes to memory via check and recovery |
| US10963261B2 (en) | 2017-04-18 | 2021-03-30 | International Business Machines Corporation | Sharing snapshots across save requests |
| US10782979B2 (en) | 2017-04-18 | 2020-09-22 | International Business Machines Corporation | Restoring saved architected registers and suppressing verification of registers to be restored |
| US11010192B2 (en) | 2017-04-18 | 2021-05-18 | International Business Machines Corporation | Register restoration using recovery buffers |
| US10572265B2 (en) | 2017-04-18 | 2020-02-25 | International Business Machines Corporation | Selecting register restoration or register reloading |
| US10740108B2 (en) | 2017-04-18 | 2020-08-11 | International Business Machines Corporation | Management of store queue based on restoration operation |
| US10761983B2 (en) * | 2017-11-14 | 2020-09-01 | International Business Machines Corporation | Memory based configuration state registers |
| US10592164B2 (en) | 2017-11-14 | 2020-03-17 | International Business Machines Corporation | Portions of configuration state registers in-memory |
| US10853078B2 (en) * | 2018-12-21 | 2020-12-01 | Intel Corporation | Method and apparatus for supporting speculative memory optimizations |
| KR20210134915A (ko) * | 2019-02-20 | 2021-11-11 | 옵티멈 세미컨덕터 테크놀로지스 인코포레이티드 | 좌표 회전 디지털 컴퓨터(cordic)를 사용하여 부동 소수점 삼각 함수의 하드웨어 효율적인 적응적 계산을 위한 장치 및 방법 |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000056969A (ja) * | 1998-08-07 | 2000-02-25 | Matsushita Electric Ind Co Ltd | レジスタファイル |
| US6237076B1 (en) | 1998-08-19 | 2001-05-22 | International Business Machines Corporation | Method for register renaming by copying a 32 bits instruction directly or indirectly to a 64 bits instruction |
| US6425072B1 (en) | 1999-08-31 | 2002-07-23 | Advanced Micro Devices, Inc. | System for implementing a register free-list by using swap bit to select first or second register tag in retire queue |
| US6772317B2 (en) * | 2001-05-17 | 2004-08-03 | Intel Corporation | Method and apparatus for optimizing load memory accesses |
| US7065631B2 (en) * | 2002-04-09 | 2006-06-20 | Sun Microsystems, Inc. | Software controllable register map |
| US7127592B2 (en) * | 2003-01-08 | 2006-10-24 | Sun Microsystems, Inc. | Method and apparatus for dynamically allocating registers in a windowed architecture |
| US7725682B2 (en) * | 2006-01-10 | 2010-05-25 | International Business Machines Corporation | Method and apparatus for sharing storage and execution resources between architectural units in a microprocessor using a polymorphic function unit |
| US7506139B2 (en) * | 2006-07-12 | 2009-03-17 | International Business Machines Corporation | Method and apparatus for register renaming using multiple physical register files and avoiding associative search |
| US7475224B2 (en) * | 2007-01-03 | 2009-01-06 | International Business Machines Corporation | Register map unit supporting mapping of multiple register specifier classes |
| US8140780B2 (en) * | 2008-12-31 | 2012-03-20 | Micron Technology, Inc. | Systems, methods, and devices for configuring a device |
| US8266411B2 (en) | 2009-02-05 | 2012-09-11 | International Business Machines Corporation | Instruction set architecture with instruction characteristic bit indicating a result is not of architectural importance |
| US8707015B2 (en) | 2010-07-01 | 2014-04-22 | Advanced Micro Devices, Inc. | Reclaiming physical registers renamed as microcode architectural registers to be available for renaming as instruction set architectural registers based on an active status indicator |
| US8972701B2 (en) | 2011-12-06 | 2015-03-03 | Arm Limited | Setting zero bits in architectural register for storing destination operand of smaller size based on corresponding zero flag attached to renamed physical register |
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2010
- 2010-10-07 US US12/900,124 patent/US9626190B2/en active Active
-
2011
- 2011-10-04 JP JP2013532870A patent/JP5703382B2/ja active Active
- 2011-10-04 KR KR1020137008998A patent/KR101797187B1/ko active Active
- 2011-10-04 WO PCT/US2011/054688 patent/WO2012047833A1/en not_active Ceased
- 2011-10-04 CN CN201180059045.0A patent/CN103262028B/zh active Active
- 2011-10-04 EP EP11771344.6A patent/EP2625599B1/en active Active