CN106575260A8 - 采用数据压缩的高速缓存技术 - Google Patents

采用数据压缩的高速缓存技术 Download PDF

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Publication number
CN106575260A8
CN106575260A8 CN201580045588.5A CN201580045588A CN106575260A8 CN 106575260 A8 CN106575260 A8 CN 106575260A8 CN 201580045588 A CN201580045588 A CN 201580045588A CN 106575260 A8 CN106575260 A8 CN 106575260A8
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China
Prior art keywords
cache
data
compressed
technology
data compression
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Pending
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CN201580045588.5A
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English (en)
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CN106575260A (zh
Inventor
K.S.格林斯鲁德
S.N.特里卡
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Intel Corp
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Intel Corp
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Application filed by Intel Corp filed Critical Intel Corp
Publication of CN106575260A publication Critical patent/CN106575260A/zh
Publication of CN106575260A8 publication Critical patent/CN106575260A8/zh
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0886—Variable-length word access
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20—Employing a main memory using a specific memory technology
    • G06F2212/202—Non-volatile memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/40—Specific encoding of data in memory or cache
    • G06F2212/401—Compressed data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements
    • G06F2212/621—Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

描述了采用数据压缩的高速缓存技术。本公开的技术包括高速缓存系统、方法和计算机可读介质，其中高速缓存行中的数据在被写入到高速缓存存储器之前被压缩。在一些实施例中，该技术使得高速缓存控制器能够在将压缩数据写入到高速缓存存储器之前了解高速缓存行中的数据被压缩的程度。因此，高速缓存控制器可至少部分地基于压缩数据的大小、可归因于压缩数据（或其对应的输入数据）的压缩比或其组合来确定压缩数据将被存储在高速缓存存储器中的何处。
CN201580045588.5A 2014-09-26 2015-08-31 采用数据压缩的高速缓存技术 Pending CN106575260A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/497,392 2014-09-26
US14/497,392 US20160092361A1 (en) 2014-09-26 2014-09-26 Caching technologies employing data compression
PCT/US2015/047758 WO2016048599A1 (en) 2014-09-26 2015-08-31 Caching technologies employing data compression

Publications (2)

Publication Number Publication Date
CN106575260A CN106575260A (zh) 2017-04-19
CN106575260A8 true CN106575260A8 (zh) 2017-07-11

Family

ID=55581788

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580045588.5A Pending CN106575260A (zh) 2014-09-26 2015-08-31 采用数据压缩的高速缓存技术

Country Status (6)

Country Link
US (1) US20160092361A1 (zh)
KR (1) KR20170036075A (zh)
CN (1) CN106575260A (zh)
DE (1) DE112015003540T5 (zh)
TW (1) TWI594121B (zh)
WO (1) WO2016048599A1 (zh)

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US10490238B2 (en) * 2017-06-29 2019-11-26 SK Hynix Inc. Serializer and memory device including the same
EP3665580B1 (en) * 2017-08-08 2023-03-08 Continental Automotive Technologies GmbH Method of operating a cache
US10558364B2 (en) * 2017-10-16 2020-02-11 Alteryx, Inc. Memory allocation in a data analytics system
US10534555B2 (en) 2017-11-29 2020-01-14 International Business Machines Corporation Host synchronized autonomous data chip address sequencer for a distributed buffer memory system
US10395698B2 (en) 2017-11-29 2019-08-27 International Business Machines Corporation Address/command chip controlled data chip address sequencing for a distributed memory buffer system
US10747442B2 (en) 2017-11-29 2020-08-18 International Business Machines Corporation Host controlled data chip address sequencing for a distributed memory buffer system
US10489069B2 (en) 2017-11-29 2019-11-26 International Business Machines Corporation Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system
CN109558088B (zh) * 2018-12-03 2021-12-17 郑州云海信息技术有限公司 一种压缩方法、系统、设备及计算机可读存储介质
US10884940B2 (en) * 2018-12-21 2021-01-05 Advanced Micro Devices, Inc. Method and apparatus for using compression to improve performance of low voltage caches
JP2020154525A (ja) * 2019-03-19 2020-09-24 キオクシア株式会社 メモリシステムおよび情報処理システム
US11054993B2 (en) 2019-05-28 2021-07-06 Intel Corporation Mass storage system having peer-to-peer data movements between a cache and a backend store
CN113656364B (zh) * 2021-08-05 2024-02-20 福瑞泰克智能系统有限公司 传感器数据处理方法、装置和计算机可读存储介质
CN114579050B (zh) * 2022-02-14 2024-04-02 阿里巴巴（中国）有限公司 处理压缩数据的方法以及装置

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US6879266B1 (en) * 1997-08-08 2005-04-12 Quickshift, Inc. Memory module including scalable embedded parallel data compression and decompression engines
US6735673B2 (en) * 2002-01-10 2004-05-11 Hewlett-Packard Development Company, L.P. Apparatus and methods for cache line compression
US7849241B2 (en) * 2006-03-23 2010-12-07 International Business Machines Corporation Memory compression method and apparatus for heterogeneous processor architectures in an information handling system
JP4653830B2 (ja) * 2008-09-19 2011-03-16 株式会社東芝 命令キャッシュシステム
US8479080B1 (en) * 2009-07-12 2013-07-02 Apple Inc. Adaptive over-provisioning in memory systems
US20110161560A1 (en) * 2009-12-31 2011-06-30 Hutchison Neil D Erase command caching to improve erase performance on flash memory
WO2012056493A1 (en) * 2010-10-26 2012-05-03 Hitachi, Ltd. File management method and computer system
CN102129873B (zh) * 2011-03-29 2012-07-04 西安交通大学 提高计算机末级高速缓存可靠性的数据压缩装置及其方法
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Also Published As

Publication number Publication date
DE112015003540T5 (de) 2017-05-04
WO2016048599A1 (en) 2016-03-31
KR20170036075A (ko) 2017-03-31
TWI594121B (zh) 2017-08-01
CN106575260A (zh) 2017-04-19
US20160092361A1 (en) 2016-03-31
TW201629774A (zh) 2016-08-16

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CI01 Publication of corrected invention patent application

Correction item: Priority

Correct: 14/497,392 2014.09.26 US

Number: 16

Volume: 33

CI01 Publication of corrected invention patent application
CI02 Correction of invention patent application

Correction item: Priority

Correct: 14/497,392 2014.09.26 US

Number: 16

Page: The title page

Volume: 33

CI02 Correction of invention patent application
RJ01 Rejection of invention patent application after publication

Application publication date: 20170419

RJ01 Rejection of invention patent application after publication