JP2014220537A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2014220537A JP2014220537A JP2014172343A JP2014172343A JP2014220537A JP 2014220537 A JP2014220537 A JP 2014220537A JP 2014172343 A JP2014172343 A JP 2014172343A JP 2014172343 A JP2014172343 A JP 2014172343A JP 2014220537 A JP2014220537 A JP 2014220537A
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
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Abstract
【解決手段】半導体装置において、基板と、基板上に配置される半導体素子と、半導体素子上に配置される放熱部材と、基板の上部と、半導体素子と、放熱部材とを被覆する封止部材とを備え、放熱部材の半導体素子に配置される面の表面積は、半導体素子の放熱部材が配置される面の表面積よりも大きいことを特徴とする。本発明に係る半導体装置によれば、封止部材内部に放熱部材を埋め込むことによって、従来の放熱部材より小さな面積の放熱部材によって半導体素子動作時の熱を効果的に封止部材内部に拡散させ、半導体装置の放熱性を向上させ、熱抵抗の低減を図ることが可能となる。
【選択図】図4
Description
部材7、31と半導体素子3と間に数十〜数百[μ]の厚さの封止部材5が介在し、この封止部材5の熱伝導率は0.5〜3[W/mK]程度であって金属等に比べると熱伝導率が低いため、熱抵抗が大きく、半導体素子3から発生した熱は封止部材5内部で十分に拡散されない。また、従来の放熱板部材7、31が大気に露出するように半導体装置の上部に搭載された半導体装置20、30においては、半導体素子3上から発生する熱が放熱部材7、31へ到達するまでの放熱面積が限られているために、半導体装置表面から十分な放熱効果が得られない。
本発明の実施形態1に係る半導体装置について図面を参照して説明する。
図4(A)及び図4(B)は実施形態1に係る半導体装置100の概略構成を示す図である。図4(A)は半導体装置100の概略構成を示す平面図、図4(B)は図4(A)に示すA−A´線から見た半導体装置100の断面図である。図4(A)及び図4(B)において、半導体装置100は、基板101と、基板101上に接着剤102Bを介して配置される半導体チップ103と、半導体チップ103の上に接着剤102Aを介して配置される放熱部材107と、基板101の上部と半導体素子103と放熱部材107とを被覆する封止部材105とを備える。
導体素子103上の封止部材105に伝導すると共に、特に封止部材105内部の横方向にも効果的に熱を拡散させることによって、半導体素子103から封止部材105表面に至るまでの放熱面積、すなわち放熱経路を広げることができる。したがって、本発明に係る半導体装置100は、図2又は図3に示す従来の半導体装置にみられるような、封止部材5上に放熱部材7、31が露出している半導体装置20、30よりも、半導体装置の熱抵抗θjaを低減することが可能である。
図14から図16に示す熱解析結果に基づき、本発明の実施例における半導体装置の放熱特性を従来の放熱部材を有する半導体装置と比較して説明する。
本発明の実施形態2に係る半導体装置200について図面を参照して説明する。本発明の実施形態2は、前述の実施形態1に係る半導体装置100において、放熱部材107と半導体素子103との間にスペーサ201が配置される例を説明するものである。
本発明の実施形態3に係る半導体装置について図面を参照して説明する。本発明の実施形態3は、前述の実施形態1に係る半導体装置100において、放熱部材107と半導体素子103との間に、更に半導体素子203が配置される構成例を説明するものである。
本発明の実施形態4に係る半導体装置400について図面を参照して説明する。本発明の実施形態4は、前述の実施形態1に係る半導体装置100において、放熱部材の構造を変えた例を説明するものである。
(実施形態5)
本発明の実施形態5に係る半導体装置について図面を参照して説明する。本発明の実施形態5は、前述の実施形態1に係る半導体装置100において、放熱部材107の外部形状を変えた例を説明するものである。
本発明の実施形態6に係る半導体装置について図面を参照して説明する。本発明の実施形態6は、前述の実施形態1に係る半導体装置100において、複数の半導体素子103が並べて配置される例を説明するものである。なお、実施形態6に係る半導体装置600は、複数の半導体素子103が同一基板101上に並べて配置されることに特徴があり、その他の構成は実施形態1において説明した構成と同様であるため、その他の構成や半導体装置600の製造方法や実施形態6における半導体装置600の放熱特性等に関する図示及び説明は省略する。
Claims (1)
- 基板と、
前記基板上に配置される半導体素子と、
前記半導体素子上に配置される放熱部材と、
前記基板の上部と、前記半導体素子と、前記放熱部材とを被覆する封止部材とを有し、
前記放熱部材の前記半導体素子に配置される面の表面積は、前記半導体素子の前記放熱部材が配置される面の表面積よりも大きいことを特徴とする半導体装置。
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JP2010169574A Division JP2012033559A (ja) | 2010-07-28 | 2010-07-28 | 半導体装置 |
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Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0766327A (ja) * | 1993-08-25 | 1995-03-10 | Toshiba Corp | 放熱板を有する半導体装置及び放熱板の製造方法 |
JP2003258166A (ja) * | 2001-12-27 | 2003-09-12 | Denso Corp | 半導体装置 |
JP2004327558A (ja) * | 2003-04-22 | 2004-11-18 | Matsushita Electric Works Ltd | 半導体装置 |
US20070210438A1 (en) * | 2006-03-07 | 2007-09-13 | Briere Michael A | Semiconductor package |
JP2009117702A (ja) * | 2007-11-08 | 2009-05-28 | Nec Electronics Corp | 半導体装置 |
JP2009295794A (ja) * | 2008-06-05 | 2009-12-17 | Mitsubishi Electric Corp | 樹脂封止型半導体装置とその製造方法 |
JP2010199516A (ja) * | 2009-02-27 | 2010-09-09 | Denso Corp | 電子装置 |
JP2011530190A (ja) * | 2008-08-04 | 2011-12-15 | クラスタード システムズ カンパニー | 接点を冷却した電子機器匡体 |
-
2014
- 2014-08-27 JP JP2014172343A patent/JP5955911B2/ja active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0766327A (ja) * | 1993-08-25 | 1995-03-10 | Toshiba Corp | 放熱板を有する半導体装置及び放熱板の製造方法 |
JP2003258166A (ja) * | 2001-12-27 | 2003-09-12 | Denso Corp | 半導体装置 |
JP2004327558A (ja) * | 2003-04-22 | 2004-11-18 | Matsushita Electric Works Ltd | 半導体装置 |
US20070210438A1 (en) * | 2006-03-07 | 2007-09-13 | Briere Michael A | Semiconductor package |
JP2009117702A (ja) * | 2007-11-08 | 2009-05-28 | Nec Electronics Corp | 半導体装置 |
JP2009295794A (ja) * | 2008-06-05 | 2009-12-17 | Mitsubishi Electric Corp | 樹脂封止型半導体装置とその製造方法 |
JP2011530190A (ja) * | 2008-08-04 | 2011-12-15 | クラスタード システムズ カンパニー | 接点を冷却した電子機器匡体 |
JP2010199516A (ja) * | 2009-02-27 | 2010-09-09 | Denso Corp | 電子装置 |
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R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |