JP2014143419A - 3次元的な表面電界緩和が増強された半導体デバイス - Google Patents
3次元的な表面電界緩和が増強された半導体デバイス Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 99
- 230000002829 reductive effect Effects 0.000 title claims description 19
- 239000002019 doping agent Substances 0.000 claims abstract description 91
- 239000000758 substrate Substances 0.000 claims abstract description 66
- 239000002800 charge carrier Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims description 30
- 238000002955 isolation Methods 0.000 claims description 26
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 9
- 230000000737 periodic effect Effects 0.000 claims description 6
- 230000000694 effects Effects 0.000 abstract description 21
- 230000005684 electric field Effects 0.000 description 29
- 238000009792 diffusion process Methods 0.000 description 28
- 210000000746 body region Anatomy 0.000 description 25
- 230000001965 increasing effect Effects 0.000 description 12
- 230000015556 catabolic process Effects 0.000 description 11
- 238000013461 design Methods 0.000 description 7
- 238000009825 accumulation Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 230000009467 reduction Effects 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 6
- 238000003860 storage Methods 0.000 description 6
- 230000007704 transition Effects 0.000 description 6
- 239000006185 dispersion Substances 0.000 description 5
- 239000007943 implant Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- ALKWEXBKAHPJAQ-NAKRPEOUSA-N Asn-Leu-Asp-Asp Chemical group NC(=O)C[C@H](N)C(=O)N[C@@H](CC(C)C)C(=O)N[C@@H](CC(O)=O)C(=O)N[C@@H](CC(O)=O)C(O)=O ALKWEXBKAHPJAQ-NAKRPEOUSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 230000036961 partial effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 210000003056 antler Anatomy 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000779 depleting effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 239000000446 fuel Substances 0.000 description 1
- 238000001802 infusion Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004513 sizing Methods 0.000 description 1
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Abstract
【解決手段】デバイスは半導体基板を備え、半導体基板におけるソース領域およびドレイン領域は第1の横方向に沿って互いから離間されている。動作時にソース領域とドレイン領域との間にバイアス電圧が印加されると、半導体基板におけるドリフト領域を通じて電荷担体がドリフトする。ドリフト領域は、ドリフト領域とドレイン領域との間の接合部に沿った第2の横方向においてノッチ部分を含むドーパントプロファイルを有する。
【選択図】図5
Description
Claims (20)
- デバイスであって、
半導体基板と、
前記半導体基板におけるソース領域およびドレイン領域であって、第1の横方向に沿って互いから離間されているソース領域およびドレイン領域と、
前記半導体基板におけるドリフト領域であって、動作時に前記ソース領域と前記ドレイン領域との間にバイアス電圧が印加されるとドリフト領域を通じて電荷担体がドリフトするドリフト領域と、を備え、
前記ドリフト領域は、該ドリフト領域と前記ドレイン領域との間の接合部に沿った第2の横方向において切り欠きドーパントプロファイルを有する、デバイス。 - 前記ドリフト領域は前記ドレイン領域の下の開口を備え、
前記開口は櫛形状境界を有する、請求項1に記載のデバイス。 - 前記ドリフト領域は、前記ドリフト領域と前記ドレイン領域との間の接合部において、前記ドレイン領域の垂直厚さ方向に狭まっている、請求項1に記載のデバイス。
- 前記ドリフト領域は前記ドレイン領域を通じて横方向に延在していない、請求項1に記載のデバイス。
- 前記ドリフト領域は外側部分および内側部分を備え、該内側部分は該外側部分によって包囲され、前記ドレイン領域の下に配置されており、
前記内側部分は、動作時に前記ドリフト領域の完全な空乏化が達成されるように、前記外側部分に対して縮小されている、請求項1に記載のデバイス。 - 前記切り欠きドーパントプロファイルは方形波状の切り欠きパターンを有する、請求項1に記載のデバイス。
- 前記切り欠きドーパントプロファイルは周期的な切り欠きパターンを有する、請求項1に記載のデバイス。
- 前記半導体基板はエピタキシャル層を備え、前記ソース、ドレイン、およびドリフト領域は該エピタキシャル層に形成されており、
前記ドリフト領域は前記エピタキシャル層に対する切り欠きの境界に沿って前記ドレイン領域の下で切り詰められている、請求項1に記載のデバイス。 - 前記半導体基板において前記ソース領域と前記ドレイン領域との間にトレンチ分離領域をさらに備え、
前記ドリフト領域は、前記トレンチ分離領域の下の第1の領域と、前記ドレイン領域の下の第2の領域とを備え、
前記ドリフト領域の前記第2の領域におけるドーパント濃度は、前記第1の領域に対して低減されている、請求項1に記載のデバイス。 - 電子装置であって、
半導体基板と、
前記半導体基板におけるリサーフトランジスタと、を備え、該リサーフトランジスタは、
第1の導電型を有し、動作時にチャネルが形成される第1の半導体領域と、
第2の導電型を有し、第1の横方向に沿って互いから離間されている第2の半導体領域および第3の半導体領域と、
前記第2の導電型を有する第4の半導体領域であって、前記第2の半導体領域と第3の半導体領域との間にバイアス電圧が印加されると、電荷担体が動作時に前記第1の半導体領域に形成される前記チャネルからを第4の半導体領域通じてドリフトする第4の半導体領域と、を備え、
前記第4の半導体領域は、前記第3の半導体領域と第4の半導体領域との間の接合部に沿って第2の横方向に切り欠きドーパントプロファイルを有する、電子装置。 - 前記第4の半導体領域は前記第3の半導体領域の下の開口を備え、
前記開口は櫛形状境界を有する、請求項10に記載の電子装置。 - 前記第4の半導体領域は前記第3の半導体領域を通じて横方向に延在していない、請求項10に記載の電子装置。
- 前記第4の半導体領域は外側領域および内側領域を備え、該内側領域は該外側領域によって包囲され、前記第3の半導体領域の下に配置されており、
前記内側領域は、動作時に前記第4の半導体領域の完全な空乏化が達成されるように、前記外側領域に対して縮小されている、請求項10に記載の電子装置。 - 前記半導体基板はエピタキシャル層を備え、前記第1の半導体領域、第2の半導体領域、第3の半導体領域、および第4の半導体領域は該エピタキシャル層に形成されており、
前記第4の半導体領域は前記エピタキシャル層に対する切り欠きの境界に沿って前記第3の半導体領域の下で切り詰められている、請求項10に記載の電子装置。 - 前記リサーフトランジスタは、前記第2の半導体領域と前記第3の半導体領域との間にトレンチ分離領域をさらに備え、
前記第4の半導体領域は、前記トレンチ分離領域の下の第1の領域と前記第3の半導体領域の下の第2の領域とを備え、
前記第4の半導体領域の前記第2の領域におけるドーパント濃度は、前記第1の領域に対して低減されている、請求項10に記載の電子装置。 - トランジスタを作製する方法であって、
ドリフト領域を形成するための基板の第1の領域にドーパントを注入するステップと、
前記基板の第2の領域および第3の領域にソース領域およびドレイン領域をそれぞれ形成するステップであって、該第2の領域および該第3の領域は第1の横方向において互いから離間されている、前記ステップと、を備え、
前記第1の領域は前記第3の領域を通じて横方向に延在しておらず、第2の横方向に切り欠きのドレイン側境界を有する、方法。 - 前記第1の領域は前記第3の領域の下の開口を備え、該開口は切り欠きのドレイン側境界を有する、請求項16に記載の方法。
- 前記ドリフト領域が前記ドレイン領域に電気的に結合されるように、前記基板をアニーリングするステップをさらに備える、請求項16に記載の方法。
- 前記第1の領域および前記第3の領域は横方向において重ならない、請求項16に記載の方法。
- 前記基板のエピタキシャル層を形成するステップをさらに備え、前記第1の領域、第2の領域、および第3の領域は前記エピタキシャル層に配置される、請求項16に記載の方法。
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