JP2013538012A - 熱管理を伴う積層半導体チップデバイス - Google Patents
熱管理を伴う積層半導体チップデバイス Download PDFInfo
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- JP2013538012A JP2013538012A JP2013530242A JP2013530242A JP2013538012A JP 2013538012 A JP2013538012 A JP 2013538012A JP 2013530242 A JP2013530242 A JP 2013530242A JP 2013530242 A JP2013530242 A JP 2013530242A JP 2013538012 A JP2013538012 A JP 2013538012A
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09072—Hole or recess under component or special relationship between hole and component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10378—Interposers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10416—Metallic blocks or heatsinks completely inserted in a PCB
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
- H05K2201/10515—Stacked components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/1056—Metal over component, i.e. metal plate over component mounted on or embedded in PCB
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
【選択図】図1
Description
Claims (25)
- 第1の半導体チップ(35)を、第1の開口部(70)を含む第1の基板(60)に連結するステップと、
熱管理デバイス(75,75′,75′′)を、前記第1の開口部を経由して前記第1の半導体チップと熱接触するように配置するステップと、を含む、
製造方法。 - 前記熱管理デバイスは、ヒートスプレッダ、ベーパチャンバ、または熱電冷却器のうち1つを備える、請求項1の方法。
- 前記第1の半導体チップおよび前記熱管理デバイスのうち少なくとも1つは、前記第1の開口部に少なくとも部分的に配置される、請求項1の方法。
- 複数の半導体チップ(25,30,35)を前記第1の基板に連結するステップを含む、請求項1の方法。
- 前記複数の半導体チップのうち1つは、インターポーザ(20)を備える、請求項4の方法。
- 前記第1の基板は回路基板を備え、前記方法は、前記第1の回路基板を第2の回路基板(85)に連結するステップを含む、請求項1の方法。
- 前記第2の回路基板は第2の開口部(95)を備え、前記熱管理デバイスは、前記第2の開口部に少なくとも部分的に配置される、請求項6の方法。
- 前記熱管理デバイスは、前記第2の回路基板に連結される、請求項7の方法。
- 熱管理デバイスを、半導体チップデバイス(10)の第1の半導体チップと熱接触するように配置するステップを含む製造方法であって、
前記半導体チップデバイスは、前記第1の半導体チップ(60)に連結される第1の基板を含み、前記第1の基板は、第1の開口部(70)を含み、前記熱接触は、前記第1の開口部を経由する、方法。 - 前記熱管理デバイスは、ヒートスプレッダ、ベーパチャンバ、または熱電冷却器のうち1つを備える、請求項9の方法。
- 前記第1の半導体チップおよび前記熱管理デバイスのうち少なくとも1つは、前記第1の開口部に少なくとも部分的に配置される、請求項9の方法。
- 前記半導体チップデバイスは、前記第1の基板に連結される複数の半導体チップ(25,30,35)を備える、請求項9の方法。
- 前記複数の半導体チップのうち1つは、インターポーザ(20)を備える、請求項12の方法。
- 前記第1の基板は回路基板を備え、前記方法は、前記第1の回路基板を第2の回路基板(85)に連結するステップを含む、請求項9の方法。
- 前記第2の回路基板は第2の開口部(95)を備え、前記熱管理デバイスは、前記第2の開口部に少なくとも部分的に配置される、請求項14の方法。
- 前記熱管理デバイス(75′′)は、前記第2の回路基板に連結される、請求項15の方法。
- 第1の基板に連結される第1の半導体チップ(35)を含む半導体チップデバイス(10)であって、前記第1の基板は第1の開口部(70)を含む半導体チップデバイスと、
前記第1の開口部を経由して前記第1の半導体チップと熱接触する熱管理デバイス(70)と、を備える、
装置。 - 前記熱管理デバイスは、ヒートスプレッダ、ベーパチャンバ、または熱電冷却器のうち1つを備える、請求項17の装置。
- 前記第1の半導体チップおよび前記熱管理デバイスのうち少なくとも1つは、前記第1の開口部に少なくとも部分的に配置される、請求項17の装置。
- 前記第1の半導体チップおよび前記熱管理デバイスの両方は、前記第1の開口部に少なくとも部分的に配置される、請求項17の装置。
- 前記第1の基板に連結される複数の半導体チップを備える、請求項17の装置。
- 前記複数の半導体チップのうち1つは、インターポーザ(20)を備える、請求項21の装置。
- 前記第1の基板は、第2の回路基板に連結される回路基板(85)を備える、請求項17の装置。
- 前記第2の回路基板は第2の開口部(95)を備え、前記熱管理デバイスは、前記第2の開口部に少なくとも部分的に配置される、請求項23の装置。
- 前記熱管理デバイスは前記第2の回路基板に連結される、請求項24の装置。
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US12/889,590 | 2010-09-24 | ||
US12/889,590 US8472190B2 (en) | 2010-09-24 | 2010-09-24 | Stacked semiconductor chip device with thermal management |
PCT/US2011/052466 WO2012040271A1 (en) | 2010-09-24 | 2011-09-21 | Stacked semiconductor chip device with thermal management |
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JP2013538012A true JP2013538012A (ja) | 2013-10-07 |
JP2013538012A5 JP2013538012A5 (ja) | 2014-11-06 |
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JP2013530242A Pending JP2013538012A (ja) | 2010-09-24 | 2011-09-21 | 熱管理を伴う積層半導体チップデバイス |
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US (1) | US8472190B2 (ja) |
EP (1) | EP2619795A1 (ja) |
JP (1) | JP2013538012A (ja) |
KR (1) | KR20130102052A (ja) |
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WO (1) | WO2012040271A1 (ja) |
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Also Published As
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US8472190B2 (en) | 2013-06-25 |
WO2012040271A1 (en) | 2012-03-29 |
KR20130102052A (ko) | 2013-09-16 |
EP2619795A1 (en) | 2013-07-31 |
US20120075807A1 (en) | 2012-03-29 |
CN103098207A (zh) | 2013-05-08 |
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