JP2013528300A5 - - Google Patents

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Publication number
JP2013528300A5
JP2013528300A5 JP2013512625A JP2013512625A JP2013528300A5 JP 2013528300 A5 JP2013528300 A5 JP 2013528300A5 JP 2013512625 A JP2013512625 A JP 2013512625A JP 2013512625 A JP2013512625 A JP 2013512625A JP 2013528300 A5 JP2013528300 A5 JP 2013528300A5
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JP
Japan
Prior art keywords
terminal
power supply
virtual
voltage
supply terminal
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Application number
JP2013512625A
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English (en)
Japanese (ja)
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JP5791207B2 (ja
JP2013528300A (ja
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Publication date
Priority claimed from US12/786,916 external-priority patent/US8489906B2/en
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Publication of JP2013528300A publication Critical patent/JP2013528300A/ja
Publication of JP2013528300A5 publication Critical patent/JP2013528300A5/ja
Application granted granted Critical
Publication of JP5791207B2 publication Critical patent/JP5791207B2/ja
Active legal-status Critical Current
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JP2013512625A 2010-05-25 2011-04-20 複数の低電力モードを有するデータプロセッサ Active JP5791207B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/786,916 2010-05-25
US12/786,916 US8489906B2 (en) 2010-05-25 2010-05-25 Data processor having multiple low power modes
PCT/US2011/033211 WO2011149606A2 (en) 2010-05-25 2011-04-20 Data processor having multiple low power modes

Publications (3)

Publication Number Publication Date
JP2013528300A JP2013528300A (ja) 2013-07-08
JP2013528300A5 true JP2013528300A5 (https=) 2014-05-22
JP5791207B2 JP5791207B2 (ja) 2015-10-07

Family

ID=45004629

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013512625A Active JP5791207B2 (ja) 2010-05-25 2011-04-20 複数の低電力モードを有するデータプロセッサ

Country Status (5)

Country Link
US (1) US8489906B2 (https=)
EP (1) EP2577422B1 (https=)
JP (1) JP5791207B2 (https=)
CN (1) CN102906665B (https=)
WO (1) WO2011149606A2 (https=)

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* Cited by examiner, † Cited by third party
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US8977878B2 (en) * 2011-05-19 2015-03-10 Texas Instruments Incorporated Reducing current leakage in L1 program memory
US8230247B2 (en) * 2011-12-30 2012-07-24 Intel Corporation Transferring architectural functions of a processor to a platform control hub responsive to the processor entering a deep sleep state
US9104395B2 (en) * 2012-05-02 2015-08-11 Semiconductor Energy Laboratory Co., Ltd. Processor and driving method thereof
US9405357B2 (en) * 2013-04-01 2016-08-02 Advanced Micro Devices, Inc. Distribution of power gating controls for hierarchical power domains
US9335814B2 (en) * 2013-08-28 2016-05-10 Intel Corporation Adaptively controlling low power mode operation for a cache memory
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US9582068B2 (en) * 2015-02-24 2017-02-28 Qualcomm Incorporated Circuits and methods providing state information preservation during power saving operations
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US10228746B1 (en) * 2017-12-05 2019-03-12 Western Digital Technologies, Inc. Dynamic distributed power control circuits
JP2025177976A (ja) * 2024-05-24 2025-12-05 ウィル セミコンダクター （シャンハイ） カンパニー リミテッド 半導体集積回路

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JP3184265B2 (ja) * 1991-10-17 2001-07-09 株式会社日立製作所 半導体集積回路装置およびその制御方法
JP4387122B2 (ja) * 1996-11-21 2009-12-16 株式会社日立製作所 低電力プロセッサ
US6021500A (en) 1997-05-07 2000-02-01 Intel Corporation Processor with sleep and deep sleep modes
JP2001053599A (ja) * 1999-08-12 2001-02-23 Nec Corp 半導体集積回路
US6785829B1 (en) 2000-06-30 2004-08-31 Intel Corporation Multiple operating frequencies in a processor
US6941480B1 (en) 2000-09-30 2005-09-06 Intel Corporation Method and apparatus for transitioning a processor state from a first performance mode to a second performance mode
US7260731B1 (en) 2000-10-23 2007-08-21 Transmeta Corporation Saving power when in or transitioning to a static mode of a processor
US7539878B2 (en) 2001-09-19 2009-05-26 Freescale Semiconductor, Inc. CPU powerdown method and apparatus therefor
US7080269B2 (en) 2003-05-15 2006-07-18 International Business Machines Corporation Method and apparatus for implementing power-saving sleep mode in design with multiple clock domains
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JP5374120B2 (ja) 2008-11-14 2013-12-25 ルネサスエレクトロニクス株式会社 半導体集積回路装置

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