Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/32—Means for saving power
  • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/32—Means for saving power
  • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
  • G06F1/3234—Power saving characterised by the action undertaken
  • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/0008—Arrangements for reducing power consumption
  • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
  • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

• Static leakage power has become a significant portion of the power consumption of very large scale system-on-a-chip (SoC) integrated circuits. Reducing leakage current is becoming an increasingly important factor in extending battery life of, for example, handheld devices.
• SoC system-on-a-chip
• a processor comprising: a first virtual terminal; a second virtual terminal; a first power supply terminal; a second power supply terminal; circuitry coupled between the second power supply terminal and the first virtual terminal; a first voltage regulator coupled between the first virtual terminal and the second virtual terminal; a second voltage regulator coupled between the second virtual terminal and the first power supply terminal, wherein: when the first voltage regulator is enabled, a voltage between the second power supply terminal and the first virtual terminal is less than a voltage between the second power supply terminal and the second virtual terminal, and when the second voltage regulator is enabled, a voltage between the second power supply terminal and the second virtual terminal is less than a voltage between the second power supply terminal and the first power supply terminal.
• Processor 10 includes global voltage regulator 22 and local voltage regulators 20 and 24.
• Global voltage regulator 22 includes transistors 32 and 34, and bias circuit 36.
• Local voltage regulator 20 includes transistors 26 and 28 and bias circuit 30.
• Local voltage regulator 24 includes transistors 38 and 40 and bias circuit 42.
• An embodiment of a bias circuit is described later in the discussion of FIG. 2.
• transistor 32 has a first current electrode coupled to a virtual ground conductor labeled "VVSS", a control electrode coupled to receive control signal "DISABLE 2", and a second current electrode coupled to a ground conductor labeled "VSS”.
• Transistor 34 has a first current electrode coupled to VVSS, a control electrode, and a second current electrode coupled to VSS.
• control signals DISABLE 1 , DISABLE 2, and DISABLE 3 are used to elevate the voltage at the ground terminals of the circuit blocks for the purpose of reducing power consumption by reducing static leakage current.
• the voltage regulators are tiered, or in a hierarchical order. All of the blocks of processor 10 can receive the same ground (VSS) potential, or some voltage level above ground, such as for example, the voltages at power supply terminals VVSS, or VVVSS 1 and VVVSS 2 depending on which voltage regulators are turned on.
• Volatile memory circuits, such as a SRAM (static random access memory) have certain voltage requirements for reliable data retention.
• cache 18 is implemented as a SRAM and therefore has a minimum data retention voltage. Therefore, with respect to cache 18, care must be taken to ensure that the voltage at VVVSS 2 is not raised above the minimum data retention voltage.
• the normal operating mode is entered when power management unit 19 asserts control signal DISABLE 1 , DISABLE 2, and DISABLE 3 as logic high voltages.
• Each of transistors 26, 32, and 38 are conductive, effectively disabling voltage regulators 20, 22, and 24 so that power supply terminals VSS, VVSS, VVVSS 1 , and VVVSS 2 are all at ground potential.
• circuit 12 Because the power supply voltage is already very low (e.g. 0.9 volts), and due to variations in the process and the electrical characteristics of the transistors and the power supply voltage, the data state of circuit 12 may become easily corruptible, or unstable, when transitioning from a normal mode to a low power mode. In the case where circuit 12 is an SRAM array, increasing the voltage at node N3 too much can reduce margins to the point where memory cells inadvertently change logic states. Therefore, it is important that the voltage at node N3 transition smoothly and without any overshoot of the predetermined voltage above ground. In voltage regulator 20, transistors 222 and 224 form a very low gain inverting stage so that the voltage transitions at node N3 are over-dampened.
• voltage regulator 20 transistors 222 and 224 form a very low gain inverting stage so that the voltage transitions at node N3 are over-dampened.
• FIG. 3 illustrates a flow chart of a method 50 for entering a low power mode of data processor 10 of FIG. 1 .
• Method 50 starts at step 52.
• a low power mode is entered by enabling voltage regulators 22 and 20 and disabling voltage regulator 24. In other methods, a different low power mode may be entered depending on which voltage regulators are enabled.
• decision step 56 it is determined if processor 10 is to be activated to, for example, execute instructions. If the answer is NO, the NO path is taken and step 56 is repeated. If it is determined that processor 10 should be activated, the YES path is taken to step 60.
• regulators 22 and 20 are disabled by asserting control signals DISABLE 1 and DISABLE 2.
• FIG. 1 Some of the above embodiments, as applicable, may be implemented using a variety of different information processing systems.
• Figure 1 and the discussion thereof describe an exemplary data processor
• this exemplary processor is presented merely to provide a useful reference in discussing various aspects of the invention.
• the description of the processor has been simplified for purposes of discussion, and it is just one of many different types of appropriate processors that may be used in accordance with the invention.
• Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements.

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• Engineering & Computer Science (AREA)
• General Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Computing Systems (AREA)
• General Physics & Mathematics (AREA)
• Mathematical Physics (AREA)
• Power Sources (AREA)
• Microcomputers (AREA)

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• 2010
  • 2010-05-25 US US12/786,916 patent/US8489906B2/en active Active
• 2011
  • 2011-04-20 EP EP11787069.1A patent/EP2577422B1/en active Active
  • 2011-04-20 WO PCT/US2011/033211 patent/WO2011149606A2/en not_active Ceased
  • 2011-04-20 CN CN201180025514.7A patent/CN102906665B/zh active Active
  • 2011-04-20 JP JP2013512625A patent/JP5791207B2/ja active Active

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