JP2013526066A - 低減されたダイ歪みアッセンブリのためのパッケージ基板のためのcte補償 - Google Patents

低減されたダイ歪みアッセンブリのためのパッケージ基板のためのcte補償 Download PDF

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JP2013526066A
JP2013526066A JP2013508271A JP2013508271A JP2013526066A JP 2013526066 A JP2013526066 A JP 2013526066A JP 2013508271 A JP2013508271 A JP 2013508271A JP 2013508271 A JP2013508271 A JP 2013508271A JP 2013526066 A JP2013526066 A JP 2013526066A
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substrate
dies
die
package substrate
singulated
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JP2013526066A5 (enExample
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ローズ シモンズ マシューズ マーガレット
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日本テキサス・インスツルメンツ株式会社
テキサス インスツルメンツ インコーポレイテッド
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Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8227295B2 (en) * 2008-10-16 2012-07-24 Texas Instruments Incorporated IC die having TSV and wafer level underfill and stacked IC devices comprising a workpiece solder connected to the TSV
US9048233B2 (en) * 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8786066B2 (en) * 2010-09-24 2014-07-22 Intel Corporation Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same
US8796075B2 (en) * 2011-01-11 2014-08-05 Nordson Corporation Methods for vacuum assisted underfilling
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US10153179B2 (en) 2012-08-24 2018-12-11 Taiwan Semiconductor Manufacturing Company Carrier warpage control for three dimensional integrated circuit (3DIC) stacking
KR20140110334A (ko) * 2013-03-07 2014-09-17 삼성전자주식회사 반도체 패키지 및 그 제조 방법
JP2014179419A (ja) * 2013-03-14 2014-09-25 Alpha- Design Kk 電子部品の接合方法
US8901748B2 (en) * 2013-03-14 2014-12-02 Intel Corporation Direct external interconnect for embedded interconnect bridge package
US20150014852A1 (en) * 2013-07-12 2015-01-15 Yueli Liu Package assembly configurations for multiple dies and associated techniques
US9892970B2 (en) 2016-06-02 2018-02-13 Globalfoundries Inc. Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same
US9929085B2 (en) 2016-06-02 2018-03-27 Globalfoundries Inc. Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same
WO2018013086A1 (en) 2016-07-12 2018-01-18 Hewlett-Packard Development Company, L.P. Composite wafers
KR102649471B1 (ko) 2016-09-05 2024-03-21 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
US9966363B1 (en) * 2017-02-03 2018-05-08 Nanya Technology Corporation Semiconductor apparatus and method for preparing the same
US10396003B2 (en) * 2017-10-18 2019-08-27 Micron Technology, Inc. Stress tuned stiffeners for micro electronics package warpage control
US10548230B2 (en) * 2018-01-04 2020-01-28 Micron Technology, Inc. Method for stress reduction in semiconductor package via carrier
CN111989771A (zh) * 2018-02-19 2020-11-24 迪德鲁科技(Bvi)有限公司 制造玻璃框架扇出型封装的系统和方法
US10692793B2 (en) * 2018-03-02 2020-06-23 Micron Technology, Inc. Electronic device with a package-level thermal regulator mechanism and associated systems, devices, and methods
CN110634806A (zh) * 2018-06-21 2019-12-31 美光科技公司 半导体装置组合件和其制造方法
US11694906B2 (en) * 2019-09-03 2023-07-04 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing semiconductor devices
US12412862B2 (en) * 2021-04-28 2025-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and manufacturing method thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003092375A (ja) * 2001-09-19 2003-03-28 Matsushita Electric Ind Co Ltd 半導体装置、その製造方法およびその検査方法
JP2005216989A (ja) * 2004-01-28 2005-08-11 Hitachi Maxell Ltd マルチチップモジュールの製造方法
JP2006294692A (ja) * 2005-04-06 2006-10-26 Nec Electronics Corp 半導体装置およびその製造方法
JP2007115774A (ja) * 2005-10-18 2007-05-10 Nec Electronics Corp 半導体装置の製造方法
JP2007214220A (ja) * 2006-02-08 2007-08-23 Oki Electric Ind Co Ltd 半導体パッケージの製造方法
JP2009117767A (ja) * 2007-11-09 2009-05-28 Shinko Electric Ind Co Ltd 半導体装置の製造方法及びそれにより製造した半導体装置

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6294407B1 (en) * 1998-05-06 2001-09-25 Virtual Integration, Inc. Microelectronic packages including thin film decal and dielectric adhesive layer having conductive vias therein, and methods of fabricating the same
US6008070A (en) * 1998-05-21 1999-12-28 Micron Technology, Inc. Wafer level fabrication and assembly of chip scale packages
US6627998B1 (en) * 2000-07-27 2003-09-30 International Business Machines Corporation Wafer scale thin film package
US6506681B2 (en) * 2000-12-06 2003-01-14 Micron Technology, Inc. Thin flip—chip method
US6879492B2 (en) * 2001-03-28 2005-04-12 International Business Machines Corporation Hyperbga buildup laminate
JP3831287B2 (ja) * 2002-04-08 2006-10-11 株式会社日立製作所 半導体装置の製造方法
KR100555505B1 (ko) * 2003-07-09 2006-03-03 삼성전자주식회사 실리사이드층의 증착 및 제거에 의해서 콘택홀 바닥에서확장된 오픈 선폭을 구현하는 연결 콘택 형성 방법
TWI245381B (en) * 2003-08-14 2005-12-11 Via Tech Inc Electrical package and process thereof
TWI254425B (en) 2004-10-26 2006-05-01 Advanced Semiconductor Eng Chip package structure, chip packaging process, chip carrier and manufacturing process thereof
US7256483B2 (en) * 2004-10-28 2007-08-14 Philips Lumileds Lighting Company, Llc Package-integrated thin film LED
KR100688560B1 (ko) * 2005-07-22 2007-03-02 삼성전자주식회사 웨이퍼 레벨 칩 스케일 패키지 및 그 제조 방법
DE102005053842B4 (de) * 2005-11-09 2008-02-07 Infineon Technologies Ag Halbleiterbauelement mit Verbindungselementen und Verfahren zur Herstellung desselben
SG133445A1 (en) * 2005-12-29 2007-07-30 Micron Technology Inc Methods for packaging microelectronic devices and microelectronic devices formed using such methods
US7473577B2 (en) 2006-08-11 2009-01-06 International Business Machines Corporation Integrated chip carrier with compliant interconnect
US7846776B2 (en) * 2006-08-17 2010-12-07 Micron Technology, Inc. Methods for releasably attaching sacrificial support members to microfeature workpieces and microfeature devices formed using such methods
TWI316749B (en) * 2006-11-17 2009-11-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabrication method thereof
US7605477B2 (en) 2007-01-25 2009-10-20 Raytheon Company Stacked integrated circuit assembly
US20080188037A1 (en) 2007-02-05 2008-08-07 Bridge Semiconductor Corporation Method of manufacturing semiconductor chip assembly with sacrificial metal-based core carrier
US8012857B2 (en) * 2007-08-07 2011-09-06 Semiconductor Components Industries, Llc Semiconductor die singulation method
TWI375321B (en) * 2007-08-24 2012-10-21 Xintec Inc Electronic device wafer level scale packages and fabrication methods thereof
US20100090339A1 (en) * 2008-09-12 2010-04-15 Kumar Ananda H Structures and Methods for Wafer Packages, and Probes
US8106504B2 (en) * 2008-09-25 2012-01-31 King Dragon International Inc. Stacking package structure with chip embedded inside and die having through silicon via and method of the same
US8237257B2 (en) * 2008-09-25 2012-08-07 King Dragon International Inc. Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same
US7863092B1 (en) * 2008-09-30 2011-01-04 Xilinx, Inc. Low cost bumping and bonding method for stacked die
US8952519B2 (en) * 2010-01-13 2015-02-10 Chia-Sheng Lin Chip package and fabrication method thereof
KR101698805B1 (ko) * 2010-03-23 2017-02-02 삼성전자주식회사 웨이퍼 레벨의 패키지 방법 및 그에 의해 제조되는 반도체 소자

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003092375A (ja) * 2001-09-19 2003-03-28 Matsushita Electric Ind Co Ltd 半導体装置、その製造方法およびその検査方法
JP2005216989A (ja) * 2004-01-28 2005-08-11 Hitachi Maxell Ltd マルチチップモジュールの製造方法
JP2006294692A (ja) * 2005-04-06 2006-10-26 Nec Electronics Corp 半導体装置およびその製造方法
JP2007115774A (ja) * 2005-10-18 2007-05-10 Nec Electronics Corp 半導体装置の製造方法
JP2007214220A (ja) * 2006-02-08 2007-08-23 Oki Electric Ind Co Ltd 半導体パッケージの製造方法
JP2009117767A (ja) * 2007-11-09 2009-05-28 Shinko Electric Ind Co Ltd 半導体装置の製造方法及びそれにより製造した半導体装置

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US20130029457A1 (en) 2013-01-31
CN102844861A (zh) 2012-12-26
US20140183719A1 (en) 2014-07-03
CN102844861B (zh) 2016-01-13
US8759154B2 (en) 2014-06-24
US20110266693A1 (en) 2011-11-03
WO2011139875A2 (en) 2011-11-10
WO2011139875A3 (en) 2012-02-23

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