JP2013504130A - 汎用使用のための処理ユニット内部メモリ - Google Patents

汎用使用のための処理ユニット内部メモリ Download PDF

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Publication number
JP2013504130A
JP2013504130A JP2012528080A JP2012528080A JP2013504130A JP 2013504130 A JP2013504130 A JP 2013504130A JP 2012528080 A JP2012528080 A JP 2012528080A JP 2012528080 A JP2012528080 A JP 2012528080A JP 2013504130 A JP2013504130 A JP 2013504130A
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internal memory
gpu
memory
processing unit
interface
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JP2012528080A
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Japanese (ja)
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JP2013504130A5 (enExample
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サドウスキー グレッグ
アイオールチャ コンスタンチン
ブラザーズ ジョン
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication of JP2013504130A publication Critical patent/JP2013504130A/ja
Publication of JP2013504130A5 publication Critical patent/JP2013504130A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
  • Dram (AREA)
  • Image Input (AREA)
  • Image Processing (AREA)
  • Multi Processors (AREA)
JP2012528080A 2009-09-03 2010-09-03 汎用使用のための処理ユニット内部メモリ Pending JP2013504130A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US23973009P 2009-09-03 2009-09-03
US61/239,730 2009-09-03
US12/616,636 US8803897B2 (en) 2009-09-03 2009-11-11 Internal, processing-unit memory for general-purpose use
US12/616,636 2009-11-11
PCT/US2010/047784 WO2011028984A1 (en) 2009-09-03 2010-09-03 An internal, processing-unit memory for general-purpose use

Publications (2)

Publication Number Publication Date
JP2013504130A true JP2013504130A (ja) 2013-02-04
JP2013504130A5 JP2013504130A5 (enExample) 2013-10-24

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JP2012528080A Pending JP2013504130A (ja) 2009-09-03 2010-09-03 汎用使用のための処理ユニット内部メモリ

Country Status (7)

Country Link
US (1) US8803897B2 (enExample)
EP (1) EP2473915B1 (enExample)
JP (1) JP2013504130A (enExample)
KR (1) KR20120059590A (enExample)
CN (1) CN102597951B (enExample)
IN (1) IN2012DN02568A (enExample)
WO (1) WO2011028984A1 (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015035201A (ja) * 2013-07-08 2015-02-19 株式会社リコー 画像処理装置、画像処理方法、及びプログラム
JP2020038626A (ja) * 2018-08-10 2020-03-12 ベイジン バイドゥ ネットコム サイエンス アンド テクノロジー カンパニー リミテッド 人工知能チップに用いられる命令実行方法及び装置
JP2020087413A (ja) * 2018-11-30 2020-06-04 エスケーハイニックス株式会社ＳＫ ｈｙｎｉｘ Ｉｎｃ． メモリシステム
JP2021530813A (ja) * 2018-07-26 2021-11-11 ザイリンクス インコーポレイテッドXilinx Incorporated 専用低レイテンシリンクを使用した複数のハードウェアアクセラレータのための統合されたアドレス空間

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US9058675B2 (en) * 2010-05-29 2015-06-16 Intel Corporation Non-volatile storage for graphics hardware
US8819378B2 (en) * 2011-11-14 2014-08-26 Arm Limited Data processing apparatus and method for performing memory transactions within such a data processing apparatus
US9239793B2 (en) 2011-12-13 2016-01-19 Ati Technologies Ulc Mechanism for using a GPU controller for preloading caches
US20130163195A1 (en) * 2011-12-22 2013-06-27 Nvidia Corporation System, method, and computer program product for performing operations on data utilizing a computation module
US8650525B2 (en) * 2012-06-22 2014-02-11 Altera Corporation Integrated circuit compilation
CN103795947B (zh) * 2012-10-31 2017-02-08 晨星软件研发(深圳)有限公司 使用在视频信号处理装置中的存储器空间配置方法
US8884906B2 (en) * 2012-12-21 2014-11-11 Intel Corporation Offloading touch processing to a graphics processor
WO2015101827A1 (en) * 2013-12-31 2015-07-09 Mosys, Inc. Integrated main memory and coprocessor with low latency
US11138135B2 (en) * 2018-09-20 2021-10-05 Samsung Electronics Co., Ltd. Scale-out high bandwidth memory system
EP4405774A4 (en) * 2021-09-22 2025-05-21 INTEL Corporation Controlling a power consumption of circuitry
CN113867963A (zh) * 2021-09-30 2021-12-31 联想(北京)有限公司 一种电子设备及处理方法

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US20070294454A1 (en) * 2006-06-15 2007-12-20 Radoslav Danilak Motherboard for cost-effective high performance graphics system with two or more graphics processing units
US20070294458A1 (en) * 2006-06-15 2007-12-20 Radoslav Danilak Bus interface controller for cost-effective high performance graphics system with two or more graphics processing units
US20070291039A1 (en) * 2006-06-15 2007-12-20 Radoslav Danilak Graphics processing unit for cost effective high performance graphics system with two or more graphics processing units
US20080109795A1 (en) * 2006-11-02 2008-05-08 Nvidia Corporation C/c++ language extensions for general-purpose graphics processing unit
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US20090077320A1 (en) * 2004-10-08 2009-03-19 Hoover Russell D Direct access of cache lock set data without backing memory
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US7619629B1 (en) * 2006-06-15 2009-11-17 Nvidia Corporation Method and system for utilizing memory interface bandwidth to connect multiple graphics processing units
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US7965898B2 (en) * 2005-10-28 2011-06-21 Nvidia Corporation Accelerating video decoding using multiple processors
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US7925836B2 (en) * 2008-01-25 2011-04-12 Arm Limited Selective coherency control
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JPH03227177A (ja) * 1990-01-18 1991-10-08 Natl Semiconductor Corp <Ns> 共用内部メモリを有する集積化デジタル信号プロセサ／汎用ｃｐｕ
JPH05173941A (ja) * 1991-12-26 1993-07-13 Fujitsu Ltd 並列計算機の分散フレームメモリによる画像処理装置
JP2002304382A (ja) * 2001-01-31 2002-10-18 Pacific Design Kk データ処理システム、データ処理装置およびその制御方法
US20040160449A1 (en) * 2003-02-18 2004-08-19 Microsoft Corporation Video memory management
US6956579B1 (en) * 2003-08-18 2005-10-18 Nvidia Corporation Private addressing in a multi-processor graphics processing system
JP2005209206A (ja) * 2004-01-21 2005-08-04 Thomson Licensing Sa マルチプロセッサシステムにおけるデータ転送方法、マルチプロセッサシステム、及び、この方法を実施するプロセッサ
US20090077320A1 (en) * 2004-10-08 2009-03-19 Hoover Russell D Direct access of cache lock set data without backing memory
JP2006268809A (ja) * 2005-03-24 2006-10-05 Kaadeikku Corporation:Kk 画像メモリ並列回路
JP2009510612A (ja) * 2005-09-27 2009-03-12 株式会社ソニー・コンピュータエンタテインメント Ｃｅｌｌプロセッサにおけるタスクおよびデータ管理
US20070291039A1 (en) * 2006-06-15 2007-12-20 Radoslav Danilak Graphics processing unit for cost effective high performance graphics system with two or more graphics processing units
US20070294458A1 (en) * 2006-06-15 2007-12-20 Radoslav Danilak Bus interface controller for cost-effective high performance graphics system with two or more graphics processing units
US20070294454A1 (en) * 2006-06-15 2007-12-20 Radoslav Danilak Motherboard for cost-effective high performance graphics system with two or more graphics processing units
US7619629B1 (en) * 2006-06-15 2009-11-17 Nvidia Corporation Method and system for utilizing memory interface bandwidth to connect multiple graphics processing units
US20070294696A1 (en) * 2006-06-20 2007-12-20 Papakipos Matthew N Multi-thread runtime system
US20080109795A1 (en) * 2006-11-02 2008-05-08 Nvidia Corporation C/c++ language extensions for general-purpose graphics processing unit
US20080111225A1 (en) * 2006-11-15 2008-05-15 Samsung Electronics Co., Ltd. Semiconductor device package
US20090125290A1 (en) * 2007-11-08 2009-05-14 Prosenjit Chatterjee Automatic verification of device models
US20090138658A1 (en) * 2007-11-21 2009-05-28 The Regents Of The University Of Michigan Cache memory system for a data processing apparatus
US20090150654A1 (en) * 2007-12-07 2009-06-11 Nvidia Corporation Fused multiply-add functional unit
US20100149199A1 (en) * 2008-12-11 2010-06-17 Nvidia Corporation System and method for video memory usage for general system application
JP2011048579A (ja) * 2009-08-26 2011-03-10 Univ Of Tokyo 画像処理装置及び画像処理方法

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015035201A (ja) * 2013-07-08 2015-02-19 株式会社リコー 画像処理装置、画像処理方法、及びプログラム
JP2021530813A (ja) * 2018-07-26 2021-11-11 ザイリンクス インコーポレイテッドXilinx Incorporated 専用低レイテンシリンクを使用した複数のハードウェアアクセラレータのための統合されたアドレス空間
JP7565911B2 (ja) 2018-07-26 2024-10-11 ザイリンクス インコーポレイテッド 専用低レイテンシリンクを使用した複数のハードウェアアクセラレータのための統合されたアドレス空間
JP2020038626A (ja) * 2018-08-10 2020-03-12 ベイジン バイドゥ ネットコム サイエンス アンド テクノロジー カンパニー リミテッド 人工知能チップに用いられる命令実行方法及び装置
JP7001643B2 (ja) 2018-08-10 2022-01-19 ベイジン バイドゥ ネットコム サイエンス テクノロジー カンパニー リミテッド 人工知能チップに用いられる命令実行方法及び装置
JP2020087413A (ja) * 2018-11-30 2020-06-04 エスケーハイニックス株式会社ＳＫ ｈｙｎｉｘ Ｉｎｃ． メモリシステム
JP7349812B2 (ja) 2018-11-30 2023-09-25 エスケーハイニックス株式会社 メモリシステム

Also Published As

Publication number Publication date
KR20120059590A (ko) 2012-06-08
CN102597951A (zh) 2012-07-18
EP2473915A1 (en) 2012-07-11
WO2011028984A1 (en) 2011-03-10
IN2012DN02568A (enExample) 2015-08-28
US20110050710A1 (en) 2011-03-03
CN102597951B (zh) 2016-05-04
US8803897B2 (en) 2014-08-12
EP2473915B1 (en) 2017-03-15

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