CN102597951B - 一般目的使用的内部处理单元的存储器 - Google Patents

一般目的使用的内部处理单元的存储器 Download PDF

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Publication number
CN102597951B
CN102597951B CN201080049244.9A CN201080049244A CN102597951B CN 102597951 B CN102597951 B CN 102597951B CN 201080049244 A CN201080049244 A CN 201080049244A CN 102597951 B CN102597951 B CN 102597951B
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China
Prior art keywords
gpu
memory
internal storage
interface
cpu
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CN201080049244.9A
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Chinese (zh)
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CN102597951A (zh
Inventor
G·萨多斯基
K·伊乌尔查
J·布拉泽尔
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
  • Dram (AREA)
  • Image Input (AREA)
  • Image Processing (AREA)
  • Multi Processors (AREA)
CN201080049244.9A 2009-09-03 2010-09-03 一般目的使用的内部处理单元的存储器 Active CN102597951B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US23973009P 2009-09-03 2009-09-03
US61/239,730 2009-09-03
US12/616,636 US8803897B2 (en) 2009-09-03 2009-11-11 Internal, processing-unit memory for general-purpose use
US12/616,636 2009-11-11
PCT/US2010/047784 WO2011028984A1 (en) 2009-09-03 2010-09-03 An internal, processing-unit memory for general-purpose use

Publications (2)

Publication Number Publication Date
CN102597951A CN102597951A (zh) 2012-07-18
CN102597951B true CN102597951B (zh) 2016-05-04

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ID=43624191

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201080049244.9A Active CN102597951B (zh) 2009-09-03 2010-09-03 一般目的使用的内部处理单元的存储器

Country Status (7)

Country Link
US (1) US8803897B2 (enExample)
EP (1) EP2473915B1 (enExample)
JP (1) JP2013504130A (enExample)
KR (1) KR20120059590A (enExample)
CN (1) CN102597951B (enExample)
IN (1) IN2012DN02568A (enExample)
WO (1) WO2011028984A1 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9058675B2 (en) * 2010-05-29 2015-06-16 Intel Corporation Non-volatile storage for graphics hardware
US8819378B2 (en) * 2011-11-14 2014-08-26 Arm Limited Data processing apparatus and method for performing memory transactions within such a data processing apparatus
US9239793B2 (en) 2011-12-13 2016-01-19 Ati Technologies Ulc Mechanism for using a GPU controller for preloading caches
US20130163195A1 (en) * 2011-12-22 2013-06-27 Nvidia Corporation System, method, and computer program product for performing operations on data utilizing a computation module
US8650525B2 (en) * 2012-06-22 2014-02-11 Altera Corporation Integrated circuit compilation
CN103795947B (zh) * 2012-10-31 2017-02-08 晨星软件研发(深圳)有限公司 使用在视频信号处理装置中的存储器空间配置方法
US8884906B2 (en) * 2012-12-21 2014-11-11 Intel Corporation Offloading touch processing to a graphics processor
JP6337494B2 (ja) * 2013-07-08 2018-06-06 株式会社リコー 画像処理装置、画像処理方法、及びプログラム
WO2015101827A1 (en) * 2013-12-31 2015-07-09 Mosys, Inc. Integrated main memory and coprocessor with low latency
US10802995B2 (en) * 2018-07-26 2020-10-13 Xilinx, Inc. Unified address space for multiple hardware accelerators using dedicated low latency links
CN110825530B (zh) * 2018-08-10 2022-12-23 昆仑芯(北京)科技有限公司 用于人工智能芯片的指令执行方法和装置
US11138135B2 (en) * 2018-09-20 2021-10-05 Samsung Electronics Co., Ltd. Scale-out high bandwidth memory system
KR102693213B1 (ko) * 2018-11-30 2024-08-09 에스케이하이닉스 주식회사 메모리 시스템
EP4405774A4 (en) * 2021-09-22 2025-05-21 INTEL Corporation Controlling a power consumption of circuitry
CN113867963A (zh) * 2021-09-30 2021-12-31 联想(北京)有限公司 一种电子设备及处理方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040160449A1 (en) * 2003-02-18 2004-08-19 Microsoft Corporation Video memory management
EP1557755A1 (en) * 2004-01-21 2005-07-27 Thomson Licensing S.A. Method for transferring data in a multiprocessor system, multiprocessor system and processor carrying out this method.
US20070294696A1 (en) * 2006-06-20 2007-12-20 Papakipos Matthew N Multi-thread runtime system
CN100489820C (zh) * 2005-10-18 2009-05-20 威盛电子股份有限公司 在计算机系统中延迟命令发出的方法和系统

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0843254A3 (en) * 1990-01-18 1999-08-18 National Semiconductor Corporation Integrated digital signal processor/general purpose CPU with shared internal memory
JPH05173941A (ja) * 1991-12-26 1993-07-13 Fujitsu Ltd 並列計算機の分散フレームメモリによる画像処理装置
JP4783527B2 (ja) * 2001-01-31 2011-09-28 株式会社ガイア・システム・ソリューション データ処理システム、データ処理装置およびその制御方法
US6956579B1 (en) * 2003-08-18 2005-10-18 Nvidia Corporation Private addressing in a multi-processor graphics processing system
JP2005296065A (ja) * 2004-04-06 2005-10-27 Konica Minolta Medical & Graphic Inc 医用画像生成システム及び医用画像生成方法並びに表示制御プログラム
US7475190B2 (en) * 2004-10-08 2009-01-06 International Business Machines Corporation Direct access of cache lock set data without backing memory
US7921365B2 (en) * 2005-02-15 2011-04-05 Microsoft Corporation System and method for browsing tabbed-heterogeneous windows
JP2006268809A (ja) * 2005-03-24 2006-10-05 Kaadeikku Corporation:Kk 画像メモリ並列回路
US7522168B2 (en) * 2005-09-27 2009-04-21 Sony Computer Entertainment Inc. Cell processor task and data management
US7376795B2 (en) * 2005-10-27 2008-05-20 International Business Machines Corporation Memory coherence protocol enhancement using cache line access frequencies
US7965898B2 (en) * 2005-10-28 2011-06-21 Nvidia Corporation Accelerating video decoding using multiple processors
US7500041B2 (en) * 2006-06-15 2009-03-03 Nvidia Corporation Graphics processing unit for cost effective high performance graphics system with two or more graphics processing units
US7562174B2 (en) * 2006-06-15 2009-07-14 Nvidia Corporation Motherboard having hard-wired private bus between graphics cards
US7619629B1 (en) * 2006-06-15 2009-11-17 Nvidia Corporation Method and system for utilizing memory interface bandwidth to connect multiple graphics processing units
US7412554B2 (en) * 2006-06-15 2008-08-12 Nvidia Corporation Bus interface controller for cost-effective high performance graphics system with two or more graphics processing units
US20080109795A1 (en) * 2006-11-02 2008-05-08 Nvidia Corporation C/c++ language extensions for general-purpose graphics processing unit
KR100813625B1 (ko) * 2006-11-15 2008-03-14 삼성전자주식회사 반도체 소자 패키지
US8271252B2 (en) * 2007-11-08 2012-09-18 Nvidia Corporation Automatic verification of device models
US8335122B2 (en) * 2007-11-21 2012-12-18 The Regents Of The University Of Michigan Cache memory system for a data processing apparatus
US8106914B2 (en) * 2007-12-07 2012-01-31 Nvidia Corporation Fused multiply-add functional unit
US7836257B2 (en) * 2007-12-19 2010-11-16 International Business Machines Corpation System and method for cache line replacement selection in a multiprocessor environment
US7925836B2 (en) * 2008-01-25 2011-04-12 Arm Limited Selective coherency control
KR101619847B1 (ko) * 2008-07-16 2016-05-11 삼성전자주식회사 화상형성장치, 호스트 장치 및 그의 웹페이지 인쇄 방법
US8610732B2 (en) * 2008-12-11 2013-12-17 Nvidia Corporation System and method for video memory usage for general system application
JP2011048579A (ja) * 2009-08-26 2011-03-10 Univ Of Tokyo 画像処理装置及び画像処理方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040160449A1 (en) * 2003-02-18 2004-08-19 Microsoft Corporation Video memory management
EP1557755A1 (en) * 2004-01-21 2005-07-27 Thomson Licensing S.A. Method for transferring data in a multiprocessor system, multiprocessor system and processor carrying out this method.
CN100489820C (zh) * 2005-10-18 2009-05-20 威盛电子股份有限公司 在计算机系统中延迟命令发出的方法和系统
US20070294696A1 (en) * 2006-06-20 2007-12-20 Papakipos Matthew N Multi-thread runtime system

Also Published As

Publication number Publication date
KR20120059590A (ko) 2012-06-08
CN102597951A (zh) 2012-07-18
EP2473915A1 (en) 2012-07-11
WO2011028984A1 (en) 2011-03-10
IN2012DN02568A (enExample) 2015-08-28
JP2013504130A (ja) 2013-02-04
US20110050710A1 (en) 2011-03-03
US8803897B2 (en) 2014-08-12
EP2473915B1 (en) 2017-03-15

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