KR20120059590A - 범용 사용을 위한 내부의, 처리-유닛 메모리 - Google Patents

범용 사용을 위한 내부의, 처리-유닛 메모리 Download PDF

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Publication number
KR20120059590A
KR20120059590A KR1020127008022A KR20127008022A KR20120059590A KR 20120059590 A KR20120059590 A KR 20120059590A KR 1020127008022 A KR1020127008022 A KR 1020127008022A KR 20127008022 A KR20127008022 A KR 20127008022A KR 20120059590 A KR20120059590 A KR 20120059590A
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KR
South Korea
Prior art keywords
internal memory
gpu
memory
processing unit
internal
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Ceased
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KR1020127008022A
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English (en)
Korean (ko)
Inventor
그레그 사도우스키
콘스탄틴 이오우르챠
존 브라더스
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
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Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20120059590A publication Critical patent/KR20120059590A/ko
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
  • Dram (AREA)
  • Image Input (AREA)
  • Image Processing (AREA)
  • Multi Processors (AREA)
KR1020127008022A 2009-09-03 2010-09-03 범용 사용을 위한 내부의, 처리-유닛 메모리 Ceased KR20120059590A (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US23973009P 2009-09-03 2009-09-03
US61/239,730 2009-09-03
US12/616,636 US8803897B2 (en) 2009-09-03 2009-11-11 Internal, processing-unit memory for general-purpose use
US12/616,636 2009-11-11
PCT/US2010/047784 WO2011028984A1 (en) 2009-09-03 2010-09-03 An internal, processing-unit memory for general-purpose use

Publications (1)

Publication Number Publication Date
KR20120059590A true KR20120059590A (ko) 2012-06-08

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020127008022A Ceased KR20120059590A (ko) 2009-09-03 2010-09-03 범용 사용을 위한 내부의, 처리-유닛 메모리

Country Status (7)

Country Link
US (1) US8803897B2 (enExample)
EP (1) EP2473915B1 (enExample)
JP (1) JP2013504130A (enExample)
KR (1) KR20120059590A (enExample)
CN (1) CN102597951B (enExample)
IN (1) IN2012DN02568A (enExample)
WO (1) WO2011028984A1 (enExample)

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US9239793B2 (en) 2011-12-13 2016-01-19 Ati Technologies Ulc Mechanism for using a GPU controller for preloading caches
US20130163195A1 (en) * 2011-12-22 2013-06-27 Nvidia Corporation System, method, and computer program product for performing operations on data utilizing a computation module
US8650525B2 (en) * 2012-06-22 2014-02-11 Altera Corporation Integrated circuit compilation
CN103795947B (zh) * 2012-10-31 2017-02-08 晨星软件研发(深圳)有限公司 使用在视频信号处理装置中的存储器空间配置方法
US8884906B2 (en) * 2012-12-21 2014-11-11 Intel Corporation Offloading touch processing to a graphics processor
JP6337494B2 (ja) * 2013-07-08 2018-06-06 株式会社リコー 画像処理装置、画像処理方法、及びプログラム
WO2015101827A1 (en) * 2013-12-31 2015-07-09 Mosys, Inc. Integrated main memory and coprocessor with low latency
US10802995B2 (en) * 2018-07-26 2020-10-13 Xilinx, Inc. Unified address space for multiple hardware accelerators using dedicated low latency links
CN110825530B (zh) * 2018-08-10 2022-12-23 昆仑芯(北京)科技有限公司 用于人工智能芯片的指令执行方法和装置
KR102693213B1 (ko) * 2018-11-30 2024-08-09 에스케이하이닉스 주식회사 메모리 시스템
EP4405774A4 (en) * 2021-09-22 2025-05-21 INTEL Corporation Controlling a power consumption of circuitry
CN113867963A (zh) * 2021-09-30 2021-12-31 联想(北京)有限公司 一种电子设备及处理方法

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200033711A (ko) * 2018-09-20 2020-03-30 삼성전자주식회사 스케일-아웃 고대역폭 메모리 시스템

Also Published As

Publication number Publication date
CN102597951A (zh) 2012-07-18
EP2473915A1 (en) 2012-07-11
WO2011028984A1 (en) 2011-03-10
IN2012DN02568A (enExample) 2015-08-28
JP2013504130A (ja) 2013-02-04
US20110050710A1 (en) 2011-03-03
CN102597951B (zh) 2016-05-04
US8803897B2 (en) 2014-08-12
EP2473915B1 (en) 2017-03-15

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