IN2012DN02568A - - Google Patents

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Publication number
IN2012DN02568A
IN2012DN02568A IN2568DEN2012A IN2012DN02568A IN 2012DN02568 A IN2012DN02568 A IN 2012DN02568A IN 2568DEN2012 A IN2568DEN2012 A IN 2568DEN2012A IN 2012DN02568 A IN2012DN02568 A IN 2012DN02568A
Authority
IN
India
Prior art keywords
internal memory
gpu
couple
processing unit
dram
Prior art date
Application number
Other languages
English (en)
Inventor
Greg Sadowski
Konstantine Iourcha
John Brothers
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of IN2012DN02568A publication Critical patent/IN2012DN02568A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
  • Dram (AREA)
  • Image Input (AREA)
  • Image Processing (AREA)
  • Multi Processors (AREA)
IN2568DEN2012 2009-09-03 2010-09-03 IN2012DN02568A (enExample)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US23973009P 2009-09-03 2009-09-03
US12/616,636 US8803897B2 (en) 2009-09-03 2009-11-11 Internal, processing-unit memory for general-purpose use
PCT/US2010/047784 WO2011028984A1 (en) 2009-09-03 2010-09-03 An internal, processing-unit memory for general-purpose use

Publications (1)

Publication Number Publication Date
IN2012DN02568A true IN2012DN02568A (enExample) 2015-08-28

Family

ID=43624191

Family Applications (1)

Application Number Title Priority Date Filing Date
IN2568DEN2012 IN2012DN02568A (enExample) 2009-09-03 2010-09-03

Country Status (7)

Country Link
US (1) US8803897B2 (enExample)
EP (1) EP2473915B1 (enExample)
JP (1) JP2013504130A (enExample)
KR (1) KR20120059590A (enExample)
CN (1) CN102597951B (enExample)
IN (1) IN2012DN02568A (enExample)
WO (1) WO2011028984A1 (enExample)

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US9058675B2 (en) * 2010-05-29 2015-06-16 Intel Corporation Non-volatile storage for graphics hardware
US8819378B2 (en) * 2011-11-14 2014-08-26 Arm Limited Data processing apparatus and method for performing memory transactions within such a data processing apparatus
US9239793B2 (en) 2011-12-13 2016-01-19 Ati Technologies Ulc Mechanism for using a GPU controller for preloading caches
US20130163195A1 (en) * 2011-12-22 2013-06-27 Nvidia Corporation System, method, and computer program product for performing operations on data utilizing a computation module
US8650525B2 (en) * 2012-06-22 2014-02-11 Altera Corporation Integrated circuit compilation
CN103795947B (zh) * 2012-10-31 2017-02-08 晨星软件研发(深圳)有限公司 使用在视频信号处理装置中的存储器空间配置方法
US8884906B2 (en) * 2012-12-21 2014-11-11 Intel Corporation Offloading touch processing to a graphics processor
JP6337494B2 (ja) * 2013-07-08 2018-06-06 株式会社リコー 画像処理装置、画像処理方法、及びプログラム
WO2015101827A1 (en) * 2013-12-31 2015-07-09 Mosys, Inc. Integrated main memory and coprocessor with low latency
US10802995B2 (en) * 2018-07-26 2020-10-13 Xilinx, Inc. Unified address space for multiple hardware accelerators using dedicated low latency links
CN110825530B (zh) * 2018-08-10 2022-12-23 昆仑芯(北京)科技有限公司 用于人工智能芯片的指令执行方法和装置
US11138135B2 (en) * 2018-09-20 2021-10-05 Samsung Electronics Co., Ltd. Scale-out high bandwidth memory system
KR102693213B1 (ko) * 2018-11-30 2024-08-09 에스케이하이닉스 주식회사 메모리 시스템
EP4405774A4 (en) * 2021-09-22 2025-05-21 INTEL Corporation Controlling a power consumption of circuitry
CN113867963A (zh) * 2021-09-30 2021-12-31 联想(北京)有限公司 一种电子设备及处理方法

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JPH05173941A (ja) * 1991-12-26 1993-07-13 Fujitsu Ltd 並列計算機の分散フレームメモリによる画像処理装置
JP4783527B2 (ja) * 2001-01-31 2011-09-28 株式会社ガイア・システム・ソリューション データ処理システム、データ処理装置およびその制御方法
US6947051B2 (en) * 2003-02-18 2005-09-20 Microsoft Corporation Video memory management
US6956579B1 (en) * 2003-08-18 2005-10-18 Nvidia Corporation Private addressing in a multi-processor graphics processing system
FR2865291A1 (fr) * 2004-01-21 2005-07-22 Thomson Licensing Sa Procede de transfert de donnees dans un systeme multiprocesseur, systeme multiprocesseur et processeur mettant en oeuvre ce procede
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US7965898B2 (en) * 2005-10-28 2011-06-21 Nvidia Corporation Accelerating video decoding using multiple processors
US7500041B2 (en) * 2006-06-15 2009-03-03 Nvidia Corporation Graphics processing unit for cost effective high performance graphics system with two or more graphics processing units
US7562174B2 (en) * 2006-06-15 2009-07-14 Nvidia Corporation Motherboard having hard-wired private bus between graphics cards
US7619629B1 (en) * 2006-06-15 2009-11-17 Nvidia Corporation Method and system for utilizing memory interface bandwidth to connect multiple graphics processing units
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US8335122B2 (en) * 2007-11-21 2012-12-18 The Regents Of The University Of Michigan Cache memory system for a data processing apparatus
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JP2011048579A (ja) * 2009-08-26 2011-03-10 Univ Of Tokyo 画像処理装置及び画像処理方法

Also Published As

Publication number Publication date
KR20120059590A (ko) 2012-06-08
CN102597951A (zh) 2012-07-18
EP2473915A1 (en) 2012-07-11
WO2011028984A1 (en) 2011-03-10
JP2013504130A (ja) 2013-02-04
US20110050710A1 (en) 2011-03-03
CN102597951B (zh) 2016-05-04
US8803897B2 (en) 2014-08-12
EP2473915B1 (en) 2017-03-15

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