JP2013258188A5 - - Google Patents

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Publication number
JP2013258188A5
JP2013258188A5 JP2012131857A JP2012131857A JP2013258188A5 JP 2013258188 A5 JP2013258188 A5 JP 2013258188A5 JP 2012131857 A JP2012131857 A JP 2012131857A JP 2012131857 A JP2012131857 A JP 2012131857A JP 2013258188 A5 JP2013258188 A5 JP 2013258188A5
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JP
Japan
Prior art keywords
phosphorus
doped silicon
film
single crystal
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2012131857A
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English (en)
Japanese (ja)
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JP2013258188A (ja
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Publication date
Application filed filed Critical
Priority to JP2012131857A priority Critical patent/JP2013258188A/ja
Priority claimed from JP2012131857A external-priority patent/JP2013258188A/ja
Priority to KR1020130060848A priority patent/KR101455251B1/ko
Priority to TW102120506A priority patent/TWI497610B/zh
Priority to US13/915,054 priority patent/US20130344689A1/en
Publication of JP2013258188A publication Critical patent/JP2013258188A/ja
Publication of JP2013258188A5 publication Critical patent/JP2013258188A5/ja
Pending legal-status Critical Current

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JP2012131857A 2012-06-11 2012-06-11 基板処理方法と半導体装置の製造方法、および基板処理装置 Pending JP2013258188A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2012131857A JP2013258188A (ja) 2012-06-11 2012-06-11 基板処理方法と半導体装置の製造方法、および基板処理装置
KR1020130060848A KR101455251B1 (ko) 2012-06-11 2013-05-29 기판 처리 방법과 반도체 장치의 제조 방법 및 기판 처리 장치
TW102120506A TWI497610B (zh) 2012-06-11 2013-06-10 Semiconductor device manufacturing method and substrate processing device
US13/915,054 US20130344689A1 (en) 2012-06-11 2013-06-11 Method for processing substrate, method for manufacturing semiconductor device, and substrate processing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012131857A JP2013258188A (ja) 2012-06-11 2012-06-11 基板処理方法と半導体装置の製造方法、および基板処理装置

Publications (2)

Publication Number Publication Date
JP2013258188A JP2013258188A (ja) 2013-12-26
JP2013258188A5 true JP2013258188A5 (enExample) 2015-07-30

Family

ID=49774780

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012131857A Pending JP2013258188A (ja) 2012-06-11 2012-06-11 基板処理方法と半導体装置の製造方法、および基板処理装置

Country Status (4)

Country Link
US (1) US20130344689A1 (enExample)
JP (1) JP2013258188A (enExample)
KR (1) KR101455251B1 (enExample)
TW (1) TWI497610B (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6338904B2 (ja) * 2014-03-24 2018-06-06 株式会社Ｓｃｒｅｅｎホールディングス 基板処理装置
JP6560991B2 (ja) * 2016-01-29 2019-08-14 株式会社Ｋｏｋｕｓａｉ Ｅｌｅｃｔｒｉｃ 半導体装置の製造方法、基板処理装置およびプログラム
JP7199286B2 (ja) * 2019-03-29 2023-01-05 東京エレクトロン株式会社 基板処理装置
US11302836B2 (en) * 2020-01-14 2022-04-12 Hoon Kim Plasmonic field-enhanced photodetector and image sensor using light absorbing layer having split conduction band and valence band
KR102824349B1 (ko) * 2022-04-28 2025-06-23 가부시키가이샤 코쿠사이 엘렉트릭 기판 처리 방법, 반도체 장치의 제조 방법, 프로그램 및 기판 처리 장치

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JPS6158879A (ja) * 1984-08-29 1986-03-26 Nec Corp シリコン薄膜結晶の製造方法
JPH05226657A (ja) * 1992-02-10 1993-09-03 Nippondenso Co Ltd 薄膜トランジスタおよびその製造方法
JP3009979B2 (ja) * 1993-07-05 2000-02-14 シャープ株式会社 半導体装置及びその製造方法
JPH0982651A (ja) * 1995-09-14 1997-03-28 Toshiba Corp 半導体装置の製造方法
TW328650B (en) * 1996-08-27 1998-03-21 United Microelectronics Corp The MOS device and its manufacturing method
US5908307A (en) * 1997-01-31 1999-06-01 Ultratech Stepper, Inc. Fabrication method for reduced-dimension FET devices
JPH10326837A (ja) * 1997-03-25 1998-12-08 Toshiba Corp 半導体集積回路装置の製造方法、半導体集積回路装置、半導体装置、及び、半導体装置の製造方法
US6068928A (en) * 1998-02-25 2000-05-30 Siemens Aktiengesellschaft Method for producing a polycrystalline silicon structure and polycrystalline silicon layer to be produced by the method
US6346732B1 (en) * 1999-05-14 2002-02-12 Kabushiki Kaisha Toshiba Semiconductor device with oxide mediated epitaxial layer
JP3886085B2 (ja) * 1999-05-14 2007-02-28 株式会社東芝 半導体エピタキシャル基板の製造方法
JP3492973B2 (ja) * 2000-03-30 2004-02-03 株式会社東芝 半導体装置の製造方法
JP2001291850A (ja) * 2000-04-10 2001-10-19 Hitachi Cable Ltd 結晶シリコン薄膜の製造方法
EP1287555A1 (en) * 2000-05-31 2003-03-05 Infineon Technologies North America Corp. Process for forming doped epitaxial silicon on a silicon substrate
EP1296361A1 (en) * 2001-09-13 2003-03-26 STMicroelectronics S.r.l. A process of forming an interface free layer of silicon on a substrate of monocrystalline silicon
KR100680946B1 (ko) * 2004-04-28 2007-02-08 주식회사 하이닉스반도체 반도체 소자의 콘택 플러그 형성방법
US7361563B2 (en) * 2004-06-17 2008-04-22 Samsung Electronics Co., Ltd. Methods of fabricating a semiconductor device using a selective epitaxial growth technique
JP2007329200A (ja) * 2006-06-06 2007-12-20 Toshiba Corp 半導体装置の製造方法
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JP5023004B2 (ja) * 2008-06-30 2012-09-12 株式会社日立国際電気 基板処理方法及び基板処理装置
JP2010141079A (ja) * 2008-12-11 2010-06-24 Hitachi Kokusai Electric Inc 半導体装置の製造方法
US8313999B2 (en) * 2009-12-23 2012-11-20 Intel Corporation Multi-gate semiconductor device with self-aligned epitaxial source and drain

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