JP2013225535A - Semiconductor device and semiconductor testing device - Google Patents
Semiconductor device and semiconductor testing device Download PDFInfo
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
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Abstract
Description
本発明は、１つの電源用電極リードと個別にワイヤボンディングされる複数の電源用電極パッドを介して動作電源の供給を受ける集積回路部を備えた半導体装置に関する。 The present invention relates to a semiconductor device including an integrated circuit portion that receives operation power through one power electrode lead and a plurality of power electrode pads individually wire-bonded.
半導体装置の製造工程において、半導体チップをパッケージングする際に、半導体チップの周縁部に形成された電極パッドとパッケージ側に備えられた電極リードとを電気的に接続するボンディングと呼ばれる工程が行なわれる。ボンディングでは、微細な金属ワイヤを用いて電極パッドと電極リードとを接続するワイヤボンディングが広く採用されており、この場合、半導体チップに形成された集積回路に供給する電源電圧もボンディングワイヤを介して電源用電極リードから電源用電極パッドに印加される。 In a semiconductor device manufacturing process, when a semiconductor chip is packaged, a process called bonding is performed to electrically connect an electrode pad formed on the peripheral edge of the semiconductor chip and an electrode lead provided on the package side. . In bonding, wire bonding in which an electrode pad and an electrode lead are connected using a fine metal wire is widely used. In this case, the power supply voltage supplied to the integrated circuit formed on the semiconductor chip is also connected via the bonding wire. It is applied to the power electrode pad from the power electrode lead.
近年、半導体チップに形成される集積回路の高集積化、規模の拡大化、高速化等に伴って消費電力が増加し、より大きな電流を電源用電極リードから電源用電極パッドに流す必要性が高まっている。この容量を確保するための技術として、２つの電源用電極パッドを設け、１つの電源用電極リードからそれぞれの電源用電極パッドに個別にワイヤボンディングするダブルボンディングという手法が知られている。 In recent years, power consumption has increased as integrated circuits formed on semiconductor chips have been highly integrated, scaled up, and speeded up, and there has been a need to pass a larger current from the power electrode leads to the power electrode pads. It is growing. As a technique for securing this capacity, there is known a technique called double bonding in which two power supply electrode pads are provided and wire bonding is individually performed from one power supply electrode lead to each power supply electrode pad.
図５は、ダブルボンディングを行なっている従来の半導体装置４０の構成例を示す図である。従来の半導体装置４０において、パッケージ基板４００に半導体チップ４１０が搭載されており、半導体チップ４１０の周縁部に第１電源用電極パッド４１２ａ、第２電源用電極パッド４１２ｂ、入力信号用電極パッド４１３、出力信号用電極パッド４１４等の電極パッドが形成されている。 FIG. 5 is a diagram showing a configuration example of a conventional semiconductor device 40 performing double bonding. In the conventional semiconductor device 40, a semiconductor chip 410 is mounted on a package substrate 400, and a first power electrode pad 412 a, a second power electrode pad 412 b, an input signal electrode pad 413, Electrode pads such as an output signal electrode pad 414 are formed.
第１電源用電極パッド４１２ａ、第２電源用電極パッド４１２ｂは、半導体チップ４１０に形成された集積回路部４１１への電源供給を受けるための電極パッドである。第１電源用電極パッド４１２ａ、第２電源用電極パッド４１２ｂは、集積回路部４１１内部で電気的に接続されている。 The first power supply electrode pad 412 a and the second power supply electrode pad 412 b are electrode pads for receiving power supply to the integrated circuit portion 411 formed in the semiconductor chip 410. The first power supply electrode pad 412a and the second power supply electrode pad 412b are electrically connected inside the integrated circuit portion 411.
入力信号用電極パッド４１３は、外部からの信号を入力するための電極パッドであり、高入力抵抗となっている。出力信号用電極パッド４１４は、外部に信号を出力するための電極パッドである。 The input signal electrode pad 413 is an electrode pad for inputting an external signal, and has a high input resistance. The output signal electrode pad 414 is an electrode pad for outputting a signal to the outside.
パッケージ基板４００には、電源用電極リード４２１、入力信号用電極リード４２２、出力信号用電極リード４２３等の電極リードが備えられており、入力信号用電極リード４２２、出力信号用電極リード４２３は、それぞれ、入力信号用電極パッド４１３、出力信号用電極パッド４１４と１本のワイヤでボンディングされている。 The package substrate 400 includes electrode leads such as a power supply electrode lead 421, an input signal electrode lead 422, and an output signal electrode lead 423. The input signal electrode lead 422 and the output signal electrode lead 423 include: Each of them is bonded to the input signal electrode pad 413 and the output signal electrode pad 414 with one wire.
また、電源用電極リード４２１は、ワイヤ４２５ａにより第１電源用電極パッド４１２ａにボンディングされ、ワイヤ４２５ｂにより第２電源用電極パッド４１２ｂにボンディングされている。すなわち、１つの電源用電極リード４２１から２つの電源用電極パッド４１２に個別にボンディングされるダブルボンディングとなっている。 The power supply electrode lead 421 is bonded to the first power supply electrode pad 412a by a wire 425a, and is bonded to the second power supply electrode pad 412b by a wire 425b. That is, double bonding is performed by individually bonding from one power supply electrode lead 421 to two power supply electrode pads 412.
半導体装置４０では、製造工程において良否の試験が行なわれる。半導体装置４０の試験では、ボンディングワイヤの断線も試験項目に含める必要があるが、ダブルボンディングでは、一方のワイヤが切断状態であっても、他方のワイヤが導通しておれば、集積回路部４１１は動作可能であるため、単純な動作検査では断線を検出できない。このため、例えば、電源用電極リード４２１側から見た抵抗値の微小な差に基づいて一方のワイヤの断線の有無を判別したり、断線検出のための専用装置を用いたり、目視や画像を用いて一方のワイヤの断線の有無を判別等しなければならず、手間やコストがかかる上に、検出精度も十分とはいえない。 The semiconductor device 40 is tested for quality in the manufacturing process. In the test of the semiconductor device 40, it is necessary to include the disconnection of the bonding wire as a test item. However, in the double bonding, the integrated circuit portion 411 can be used as long as the other wire is conductive even if one wire is cut. Is operable, a disconnection cannot be detected by a simple operation test. For this reason, for example, the presence or absence of disconnection of one wire is determined based on a minute difference in resistance value viewed from the power electrode lead 421 side, a dedicated device for disconnection detection is used, or visual or image is displayed. Therefore, it is necessary to determine whether one of the wires is broken, which is troublesome and costly, and the detection accuracy is not sufficient.
ダブルボンディングの一方のワイヤの断線が試験において看過された場合、直ちに半導体装置４０の動作に影響を与えるものではないが、十分な電流容量が確保できず、発熱等によって後に不具合が発生するおそれがある。このため、ダブルボンディングの一方のワイヤが断線した状態で半導体装置４０を使用することは避けることが望ましい。 If the disconnection of one wire of the double bonding is overlooked in the test, it does not immediately affect the operation of the semiconductor device 40, but a sufficient current capacity cannot be secured, and there is a possibility that a malfunction will occur later due to heat generation or the like. is there. For this reason, it is desirable to avoid using the semiconductor device 40 in a state where one wire of double bonding is disconnected.
そこで、本発明は、１つの電源用電極リードと個別にワイヤボンディングされる複数の電源用電極パッドを介して動作電源の供給を受ける集積回路部を備えた半導体装置において、いずれかのボンディングワイヤが断線した状態で使用されることを防止するための技術を提供することを目的とする。 Accordingly, the present invention provides a semiconductor device including an integrated circuit portion that receives supply of operating power via a single power electrode lead and a plurality of power electrode pads that are individually wire-bonded. It aims at providing the technique for preventing using it in the state where it was disconnected.
上記課題を解決するため、本発明の第１の態様である半導体装置は、電源用電極リードと、前記電源用電極リードと個別にワイヤボンディングされる複数の電源用電極パッドと、前記複数の電源用電極パッドを介して動作電源の供給を受ける回路部とを備え、各電源用電極パッドから前記回路部に至るそれぞれの経路上に、他の電源用電極パッドに電源電圧が印加された場合に導通状態となるスイッチを設けたことを特徴とする。
ここで、入力信号用電極パッドをさらに備え、各電源用電極パッドと前記入力信号用電極パッドとの間に、抵抗と、前記入力信号用電極方向を順方向とした整流素子とを直列に接続してもよい。
このとき、それぞれの抵抗の値、あるいは、それぞれの整流素子の順方向降下電圧値が異なることが望ましい。
上記課題を解決するため、本発明の第２の態様である半導体試験装置は、上述の半導体装置の試験を行なう半導体試験装置であって、前記電源用電極リードに電源電圧を供給する端子と、前記入力信号用電極パッドから出力される電流の値に基づいて、前記電源用電極リードにボンディングされたワイヤの断線を判定する判定部と、を備えたことを特徴とする。
上記課題を解決するため、本発明の第３の態様である半導体試験装置は、上述の半導体装置の試験を行なう半導体試験装置であって、前記電源用電極リードに電源電圧を供給する端子と、前記電源用電極リードにボンディングされたワイヤの断線がない場合に各抵抗を流れるべき電流の値と、前記入力信号用電極パッドから出力される電流の測定値とに基づいて、どのワイヤで断線が生じたかを判定する判定部と、を備えたことを特徴とする。
In order to solve the above problems, a semiconductor device according to a first aspect of the present invention includes a power electrode lead, a plurality of power electrode pads individually wire-bonded to the power electrode lead, and the plurality of power supplies. A circuit unit that receives operation power via the electrode pads for power supply, and when a power supply voltage is applied to each of the power supply electrode pads on each path from each power electrode pad to the circuit unit. A switch that is in a conductive state is provided.
Here, an input signal electrode pad is further provided, and between each power supply electrode pad and the input signal electrode pad, a resistor and a rectifying element having the input signal electrode direction as a forward direction are connected in series. May be.
At this time, it is desirable that each resistance value or forward voltage drop value of each rectifying element is different.
In order to solve the above problems, a semiconductor test apparatus according to a second aspect of the present invention is a semiconductor test apparatus for testing the semiconductor device described above, and a terminal for supplying a power supply voltage to the power supply electrode lead; And a determination unit that determines disconnection of the wire bonded to the power supply electrode lead based on the value of the current output from the input signal electrode pad.
In order to solve the above-described problem, a semiconductor test apparatus according to a third aspect of the present invention is a semiconductor test apparatus for testing the above-described semiconductor device, and a terminal for supplying a power supply voltage to the power supply electrode lead; Based on the value of the current that should flow through each resistor when there is no disconnection of the wire bonded to the power supply electrode lead, and the measured value of the current output from the input signal electrode pad, which wire is disconnected And a determination unit for determining whether or not it has occurred.
本発明によれば、１つの電源用電極リードと個別にワイヤボンディングされる複数の電源用電極パッドを介して動作電源の供給を受ける集積回路部を備えた半導体装置において、いずれかのボンディングワイヤが断線した状態で使用されることを防止するための技術が提供される。 According to the present invention, in a semiconductor device including an integrated circuit portion that receives supply of operation power via one power electrode lead and a plurality of power electrode pads individually wire bonded, A technique for preventing use in a disconnected state is provided.
本発明の実施の形態について図面を参照して説明する。図１は、本実施形態に係る半導体装置１０の構成を示す図である。半導体装置１０において、パッケージ基板１００に半導体チップ１１０が搭載されており、半導体チップ１１０の周縁部に第１電源用電極パッド１１２ａ、第２電源用電極パッド１１２ｂ、入力信号用電極パッド１１３、出力信号用電極パッド１１４等の電極パッドが形成されている。 Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram illustrating a configuration of a semiconductor device 10 according to the present embodiment. In the semiconductor device 10, the semiconductor chip 110 is mounted on the package substrate 100, and the first power supply electrode pad 112 a, the second power supply electrode pad 112 b, the input signal electrode pad 113, and the output signal are disposed on the periphery of the semiconductor chip 110. Electrode pads such as electrode pads 114 are formed.
第１電源用電極パッド１１２ａ、第２電源用電極パッド１１２ｂは、半導体チップ１１０に形成された集積回路部１１１への電源供給を受けるための電極パッドである。入力信号用電極パッド１１３は、外部からの信号を入力するための電極パッドであり、高入力抵抗となっている。出力信号用電極パッド１１４は、外部に信号を出力するための電極パッドである。 The first power supply electrode pad 112 a and the second power supply electrode pad 112 b are electrode pads for receiving power supply to the integrated circuit unit 111 formed in the semiconductor chip 110. The input signal electrode pad 113 is an electrode pad for inputting an external signal, and has a high input resistance. The output signal electrode pad 114 is an electrode pad for outputting a signal to the outside.
パッケージ基板１００には、電源用電極リード１２１、入力信号用電極リード１２２、出力信号用電極リード１２３等の電極リードが備えられており、入力信号用電極リード１２２、出力信号用電極リード１２３は、それぞれ、入力信号用電極パッド１１３、出力信号用電極パッド１１４と１本のワイヤでボンディングされている。 The package substrate 100 includes electrode leads such as a power electrode lead 121, an input signal electrode lead 122, and an output signal electrode lead 123. The input signal electrode lead 122 and the output signal electrode lead 123 include: Each of them is bonded to the input signal electrode pad 113 and the output signal electrode pad 114 with one wire.
また、電源用電極リード１２１は、ワイヤ１２５ａにより第１電源用電極パッド１１２ａにボンディングされ、ワイヤ１２５ｂにより第２電源用電極パッド１１２ｂにボンディングされている。すなわち、１つの電源用電極リード１２１から２つの電源用電極パッド１１２に個別にボンディングされるダブルボンディングとなっている。 The power supply electrode lead 121 is bonded to the first power supply electrode pad 112a by a wire 125a, and is bonded to the second power supply electrode pad 112b by a wire 125b. That is, double bonding is performed by individually bonding from one power supply electrode lead 121 to two power supply electrode pads 112.
本実施形態の半導体装置１０の集積回路部１１１には、電源用電極パッド１１２の後段にボンディングワイヤ断線遮断回路１１５が形成され、電源用電極パッド１１２と入力信号用電極パッド１１３との間に、ボンディングワイヤ断線検出回路１１６が形成されている。これらの回路は、集積回路部１１１の他の回路（内部回路）と同じプロセスで形成することができる。 In the integrated circuit portion 111 of the semiconductor device 10 of the present embodiment, a bonding wire disconnection blocking circuit 115 is formed at the subsequent stage of the power electrode pad 112, and between the power electrode pad 112 and the input signal electrode pad 113, A bonding wire disconnection detection circuit 116 is formed. These circuits can be formed by the same process as other circuits (internal circuits) of the integrated circuit portion 111.
ボンディングワイヤ断線遮断回路１１５は、ダブルボンディングに使用されているワイヤ１２５ａ、１２５ｂのいずれかが断線している場合に、集積回路部１１１の内部回路への電源供給を遮断する回路である。 The bonding wire disconnection cut-off circuit 115 is a circuit that cuts off the power supply to the internal circuit of the integrated circuit unit 111 when one of the wires 125a and 125b used for double bonding is cut.
具体的には、第１電源用電極パッドと集積回路部１１１の内部回路への配線との間に、第２電源用電極パッドに電源電圧が印加された場合に導通状態となるスイッチＳＷａを設け、第２電源用電極パッドと集積回路部１１１の内部回路への配線との間に、第１電源用電極パッドに電源電圧が印加された場合に導通状態となるスイッチＳＷｂを設けている。スイッチＳＷａ、スイッチＳＷｂは、例えば、ＭＯＳＦＥＴ等のスイッチング素子を用いて構成することができる。また、スイッチＳＷａ、スイッチＳＷｂの後段は電気的に接続され、集積回路部１１１の内部回路に導かれる。 Specifically, a switch SWa that is conductive when a power supply voltage is applied to the second power supply electrode pad is provided between the first power supply electrode pad and the wiring to the internal circuit of the integrated circuit unit 111. A switch SWb that is conductive when a power supply voltage is applied to the first power supply electrode pad is provided between the second power supply electrode pad and the wiring to the internal circuit of the integrated circuit unit 111. The switch SWa and the switch SWb can be configured using a switching element such as a MOSFET, for example. Further, the subsequent stages of the switch SWa and the switch SWb are electrically connected and led to the internal circuit of the integrated circuit unit 111.
ボンディングワイヤ断線検出回路１１６は、ダブルボンディングに使用されているワイヤ１２５ａ、１２５ｂの断線を検出するための回路である。具体的には、第１電源用電極パッド１１２ａと入力信号用電極パッド１１３との間に抵抗ＲａとダイオードＤａとを直列接続し、第２電源用電極パッド１１２ｂと入力信号用電極パッド１１３との間に抵抗ＲｂとダイオードＤｂとを直列接続している。ダイオードＤａ、ダイオードＤｂは、例えば、ダイオード接続されたＭＯＳＦＥＴ等を用いて構成することができ、入力信号用電極パッド１１３方向を順方向とする。 The bonding wire disconnection detection circuit 116 is a circuit for detecting disconnection of the wires 125a and 125b used for double bonding. Specifically, a resistor Ra and a diode Da are connected in series between the first power electrode pad 112a and the input signal electrode pad 113, and the second power electrode pad 112b and the input signal electrode pad 113 are connected. A resistor Rb and a diode Db are connected in series between them. The diode Da and the diode Db can be configured using, for example, a diode-connected MOSFET, and the input signal electrode pad 113 direction is a forward direction.
このとき、抵抗Ｒａの値と抵抗Ｒｂとの値を異ならせておくようにする。あるいは、抵抗Ｒａの値と抵抗Ｒｂとの値を同じにして、ダイオードＤａ、ダイオードＤｂの順方向降下電圧を異ならせるようにしてもよい。さらには、抵抗Ｒａの値と抵抗Ｒｂとの値およびダイオードＤａ、ダイオードＤｂの順方向降下電圧を異ならせるようにしてもよい。ただし、この場合は、第１電源用電極パッド１１２ａと第２電源用電極パッド１１２ｂとに同じ電圧が印加されたときに、抵抗Ｒａを流れる電流と抵抗Ｒｂを流れる電流とが異なる値になるように設定する。 At this time, the value of the resistor Ra is different from the value of the resistor Rb. Alternatively, the forward drop voltage of the diode Da and the diode Db may be made different by making the value of the resistor Ra and the value of the resistor Rb the same. Further, the value of the resistor Ra and the value of the resistor Rb and the forward voltage drop of the diode Da and the diode Db may be made different. However, in this case, when the same voltage is applied to the first power supply electrode pad 112a and the second power supply electrode pad 112b, the current flowing through the resistor Ra and the current flowing through the resistor Rb become different values. Set to.
次に、半導体装置１０のワイヤ断線試験について図２、図３を参照して説明する。図２は、ワイヤ断線が発生していない状態を示している。本図に示すように、半導体装置１０の試験に、半導体試験装置２００が用いられている。半導体試験装置２００は、半導体装置１０の電源用電極リード１２１に電源電圧Ｖｉｎを印加し、入力信号用電極リード１２２から流れる電流を電流センサ２０１で計測し、判定部２０２で、ワイヤ断線状態を判定する。 Next, a wire breakage test of the semiconductor device 10 will be described with reference to FIGS. FIG. 2 shows a state where no wire breakage has occurred. As shown in the figure, a semiconductor test apparatus 200 is used for testing the semiconductor device 10. The semiconductor test apparatus 200 applies the power supply voltage Vin to the power supply electrode lead 121 of the semiconductor device 10, measures the current flowing from the input signal electrode lead 122 with the current sensor 201, and determines the wire breakage state with the determination unit 202. To do.
このように、通常使用時には、外部からの信号を入力する入力信号用電極リード１２２および入力信号用電極パッド１１３を、試験時には、断線検出用の電流出力端子として用いている。これは、入力信号用電極パッド１１３が高入力抵抗となっており、ボンディングワイヤ断線検出回路１１６からの電流をすべて外部に出力することができるからである。なお、通常使用時に、入力信号用電極パッド１１３に入力された信号は、ダイオードＤａおよびダイオードＤｂによって電源用電極パッド１１２方向に流れないようになっている。 As described above, during normal use, the input signal electrode lead 122 and the input signal electrode pad 113 for inputting a signal from the outside are used as a current output terminal for detecting disconnection during the test. This is because the input signal electrode pad 113 has a high input resistance, and all the current from the bonding wire disconnection detection circuit 116 can be output to the outside. During normal use, a signal input to the input signal electrode pad 113 is prevented from flowing in the direction of the power supply electrode pad 112 by the diode Da and the diode Db.
本図に示すように、ワイヤ１２５ａ、１２５ｂのいずれも断線が発生していない場合は、スイッチＳＷａ、スイッチＳＷｂとも導通状態となり、集積回路部１１１の内部回路に正常に電源電圧が供給される。通常使用時においても、スイッチＳＷａ、スイッチＳＷｂとも導通状態となり、集積回路部１１１の内部回路に正常に電源電圧が供給されるため、ボンディングワイヤ断線遮断回路１１５による動作への影響はない。 As shown in this figure, when neither of the wires 125a and 125b is disconnected, both the switch SWa and the switch SWb are in a conductive state, and the power supply voltage is normally supplied to the internal circuit of the integrated circuit unit 111. Even during normal use, both the switch SWa and the switch SWb are in a conductive state, and the power supply voltage is normally supplied to the internal circuit of the integrated circuit unit 111, so that the operation by the bonding wire disconnection cutoff circuit 115 is not affected.
また、抵抗Ｒａには、［数１］に示す電流Ｉａが流れ、抵抗Ｒｂには、［数１］に示す電流Ｉｂが流れる。ここで、ＶＤａは、ダイオードＤａの順方向降下電圧であり、ＶＤｂは、ダイオードＤｂの順方向降下電圧である。このとき、電流Ｉａと電流Ｉｂとは異なる値である。
図３は、第１電源用電極パッド１１２ａに接続されるワイヤ１２５ａにおいてワイヤ断線が発生した状態を示している。この場合、第１電源用電極パッド１１２ａに電圧が印加されないため、スイッチＳＷｂが非導通状態となる。この結果、集積回路部１１１の内部回路に電源電圧が供給されず、半導体装置１０は使用不能となる。このため、半導体試験において不良判定となり、一方のボンディングワイヤが断線した状態で半導体装置１０が使用されることを防ぐことができる。 FIG. 3 shows a state where a wire breakage has occurred in the wire 125a connected to the first power supply electrode pad 112a. In this case, since the voltage is not applied to the first power electrode pad 112a, the switch SWb is turned off. As a result, the power supply voltage is not supplied to the internal circuit of the integrated circuit unit 111, and the semiconductor device 10 becomes unusable. For this reason, it becomes defect determination in a semiconductor test, and it can prevent that the semiconductor device 10 is used in the state in which one bonding wire was disconnected.
なお、試験時において正常であったが、事後的にワイヤが切断状態になった場合であっても半導体装置１０は同様に使用不能となるため、一方のボンディングワイヤが断線した状態で半導体装置１０が使用されることを確実に防ぐことができる。 Although it was normal at the time of the test, the semiconductor device 10 is similarly unusable even when the wire is in a cut state later, so the semiconductor device 10 with one of the bonding wires disconnected. Can be reliably prevented from being used.
また、第１電源用電極パッド１１２ａに電圧が印加されないため、抵抗Ｒａには、電流が流れない。一方、抵抗Ｒｂには、第２電源用電極パッド１１２ｂに印加された電源電圧によって電流が流れる。このため、入力信号用電極リード１２２からは、Ｉｂの電流が出力され、電流センサ２０１で計測される。したがって、判定部２０２は、第１電源用電極パッド１１２ａに接続されるワイヤ１２５ａにおいてワイヤ断線が発生したと判定することができる。これにより、半導体装置１０の使用不能の原因が第１電源用電極パッド１１２ａのワイヤ断線であると特定することができる。 In addition, since no voltage is applied to the first power electrode pad 112a, no current flows through the resistor Ra. On the other hand, a current flows through the resistor Rb due to the power supply voltage applied to the second power supply electrode pad 112b. Therefore, the current Ib is output from the input signal electrode lead 122 and measured by the current sensor 201. Therefore, the determination unit 202 can determine that a wire breakage has occurred in the wire 125a connected to the first power electrode pad 112a. Thereby, it can be specified that the cause of the unusability of the semiconductor device 10 is the wire breakage of the first power supply electrode pad 112a.
第２電源用電極パッド１１２ｂに接続されるワイヤ１２５ｂにおいてワイヤ断線が発生した場合は、スイッチＳＷａが非導通状態となる。この結果、集積回路部１１１の内部回路に電源電圧が供給されず、半導体装置１０は使用不能となる。このため、半導体試験において不良判定となり、一方のボンディングワイヤが断線した状態で半導体装置１０が使用されることを防ぐことができる。 When a wire breakage occurs in the wire 125b connected to the second power electrode pad 112b, the switch SWa is turned off. As a result, the power supply voltage is not supplied to the internal circuit of the integrated circuit unit 111, and the semiconductor device 10 becomes unusable. For this reason, it becomes defect determination in a semiconductor test, and it can prevent that the semiconductor device 10 is used in the state in which one bonding wire was disconnected.
このとき、入力信号用電極リード１２２からは、Ｉａの電流が出力され、電流センサ２０１で計測される。したがって、判定部２０２は、第２電源用電極パッド１１２ｂに接続されるワイヤ１２５ｂにおいてワイヤ断線が発生したと判定することができる。これにより、半導体装置１０の使用不能の原因が第２電源用電極パッド１１２ｂのワイヤ断線であると特定することができる。 At this time, the current Ia is output from the input signal electrode lead 122 and measured by the current sensor 201. Therefore, the determination unit 202 can determine that a wire breakage has occurred in the wire 125b connected to the second power supply electrode pad 112b. Thereby, it can be specified that the cause of the unusability of the semiconductor device 10 is the wire breakage of the second power supply electrode pad 112b.
さらに、ワイヤ１２５ａ、ワイヤ１２５ｂの両方で断線が発生した場合は、半導体装置１０は使用不能となるとともに、入力信号用電極リード１２２から、電流は出力されない。これにより、半導体装置１０の使用不能の原因が両方のワイヤ断線であると特定することができる。 Further, when disconnection occurs in both the wires 125 a and 125 b, the semiconductor device 10 becomes unusable and no current is output from the input signal electrode lead 122. Thereby, it can be specified that the cause of the unusability of the semiconductor device 10 is both wire breaks.
なお、上述の例では、ダブルボンディングについて説明したが、本発明は、１つの電源用電極リードから３つの電源用電極パッドに個別にボンディングされるトリプルボンディング以上のワイヤボンディングに適用することも可能である。 In the above example, double bonding has been described. However, the present invention can also be applied to triple bonding or more wire bonding in which one power supply electrode lead is individually bonded to three power supply electrode pads. is there.
図４は、トリプルボンディングに本発明を適用した場合の構成を示す図である。本図に示すように、半導体装置２０において、パッケージ基板２００に半導体チップ２１０が搭載されており、半導体チップ２１０の周縁部に第１電源用電極パッド２１２ａ、第２電源用電極パッド２１２ｂ、第３電源用電極パッド２１２ｃ、入力信号用電極パッド２１３等の電極パッドが形成されている。 FIG. 4 is a diagram showing a configuration when the present invention is applied to triple bonding. As shown in the figure, in the semiconductor device 20, a semiconductor chip 210 is mounted on a package substrate 200, and a first power supply electrode pad 212 a, a second power supply electrode pad 212 b, and a third power supply pad 212 b are arranged on the periphery of the semiconductor chip 210. Electrode pads such as a power electrode pad 212c and an input signal electrode pad 213 are formed.
パッケージ基板２００には、電源用電極リード２２１、入力信号用電極リード２２２等の電極リードが備えられており、入力信号用電極リード２２２は、入力信号用電極パッド２１３と１本のワイヤでボンディングされている。 The package substrate 200 is provided with electrode leads such as a power electrode lead 221 and an input signal electrode lead 222, and the input signal electrode lead 222 is bonded to the input signal electrode pad 213 with a single wire. ing.
また、電源用電極リード２２１は、ワイヤ２２５ａにより第１電源用電極パッド２１２ａにボンディングされ、ワイヤ２２５ｂにより第２電源用電極パッド２１２ｂにボンディングされ、ワイヤ２２５ｃにより第３電源用電極パッド２１２ｃにボンディングされている。すなわち、１つの電源用電極リード１２１から３つの電源用電極パッド２１２に個別にボンディングされるトリプルボンディングとなっている。 The power supply electrode lead 221 is bonded to the first power supply electrode pad 212a by the wire 225a, bonded to the second power supply electrode pad 212b by the wire 225b, and bonded to the third power supply electrode pad 212c by the wire 225c. ing. That is, triple bonding is performed by individually bonding from one power supply electrode lead 121 to three power supply electrode pads 212.
半導体装置２０の集積回路部２１１には、電源用電極パッド２１２の後段にボンディングワイヤ断線遮断回路２１５が形成され、電源用電極パッド２１２と入力信号用電極パッド２１３との間に、ボンディングワイヤ断線検出回路２１６が形成されている。 In the integrated circuit portion 211 of the semiconductor device 20, a bonding wire disconnection cutoff circuit 215 is formed at the subsequent stage of the power supply electrode pad 212, and the bonding wire disconnection detection is performed between the power supply electrode pad 212 and the input signal electrode pad 213. A circuit 216 is formed.
ボンディングワイヤ断線遮断回路２１５は、トリプルボンディングに使用されているワイヤ２２５ａ、２２５ｂ、２２５ｃのいずれかが断線している場合に、集積回路部２１１の内部回路への電源供給を遮断する回路である。 The bonding wire disconnection cut-off circuit 215 is a circuit that cuts off power supply to the internal circuit of the integrated circuit unit 211 when any of the wires 225a, 225b, and 225c used for triple bonding is cut.
具体的には、第１電源用電極パッドと集積回路部２１１の内部回路への配線との間に、第２電源用電極パッドおよび第３電源用電極パッドに電源電圧が印加された場合に導通状態となるスイッチＳＷａを設け、第２電源用電極パッドと集積回路部２１１の内部回路への配線との間に、第１電源用電極パッドおよび第３電源用電極パッドに電源電圧が印加された場合に導通状態となるスイッチＳＷｂを設け、第３電源用電極パッドと集積回路部２１１の内部回路への配線との間に、第１電源用電極パッドおよび第２電源用電極パッドに電源電圧が印加された場合に導通状態となるスイッチＳＷｃを設けている。 Specifically, when the power supply voltage is applied to the second power supply electrode pad and the third power supply electrode pad between the first power supply electrode pad and the wiring to the internal circuit of the integrated circuit portion 211, the conduction is established. The switch SWa to be in a state is provided, and the power supply voltage is applied to the first power supply electrode pad and the third power supply electrode pad between the second power supply electrode pad and the wiring to the internal circuit of the integrated circuit unit 211. In this case, a switch SWb that is in a conductive state is provided, and a power supply voltage is applied to the first power supply electrode pad and the second power supply electrode pad between the third power supply electrode pad and the wiring to the internal circuit of the integrated circuit unit 211. There is provided a switch SWc that becomes conductive when applied.
各スイッチＳＷを動作させる回路は、例えば、本図に示すように、他の２つの電源用電極パッドの電圧で動作するＡＮＤ（論理積）回路２１４ａ、２１４ｂ、２１４ｃを用いて構成することができる。 A circuit for operating each switch SW can be configured by using, for example, AND (logical product) circuits 214a, 214b, and 214c that operate with the voltages of the other two power supply electrode pads, as shown in FIG. .
ボンディングワイヤ断線検出回路２１６は、第１電源用電極パッド２１２ａと入力信号用電極パッド２１３との間に抵抗ＲａとダイオードＤａとを直列接続し、第２電源用電極パッド２１２ｂと入力信号用電極パッド２１３との間に抵抗ＲｂとダイオードＤｂとを直列接続し、第３電源用電極パッド２１２ｃと入力信号用電極パッド２１３との間に抵抗ＲｃとダイオードＤｃとを直列接続している。この場合も、第１電源用電極パッド２１２ａと第２電源用電極パッド２１２ｂと第３電源用電極パッド２１２ｃとに同じ電圧が印加されたときに、抵抗Ｒａを流れる電流と抵抗Ｒｂを流れる電流と抵抗Ｒｃを流れる電流とが異なる値になるように設定する。 The bonding wire disconnection detection circuit 216 has a resistor Ra and a diode Da connected in series between the first power electrode pad 212a and the input signal electrode pad 213, and the second power electrode pad 212b and the input signal electrode pad. A resistor Rb and a diode Db are connected in series between the resistor 213 and the resistor 213, and a resistor Rc and a diode Dc are connected in series between the third power electrode pad 212 c and the input signal electrode pad 213. Also in this case, when the same voltage is applied to the first power electrode pad 212a, the second power electrode pad 212b, and the third power electrode pad 212c, the current flowing through the resistor Ra and the current flowing through the resistor Rb The current flowing through the resistor Rc is set to have a different value.
半導体装置２０のワイヤ断線試験についても、上述の半導体装置１０のワイヤ断線試験と同様に行なうことができる。すなわち、電源用電極リード２２１に電源電圧を印加し、入力信号用電極リード２２２からの電流値を測定すればよい。このとき、いずれかのワイヤ２２５が断線しておれば、半導体装置２０が使用不能になり、また、入力信号用電極リード２２２から出力される電流の値に基づいて、どのワイヤが断線しているかを判定することができる。 The wire breakage test of the semiconductor device 20 can be performed in the same manner as the wire breakage test of the semiconductor device 10 described above. That is, a power supply voltage may be applied to the power supply electrode lead 221 and the current value from the input signal electrode lead 222 may be measured. At this time, if any one of the wires 225 is disconnected, the semiconductor device 20 becomes unusable, and which wire is disconnected based on the value of the current output from the input signal electrode lead 222. Can be determined.
１０…半導体装置、２０…半導体装置、４０…半導体装置、１００…パッケージ基板、１１０…半導体チップ、１１１…集積回路部、１１２…電源用電極パッド、１１２ａ…第１電源用電極パッド、１１２ｂ…第２電源用電極パッド、１１３…入力信号用電極パッド、１１４…出力信号用電極パッド、１１５…ボンディングワイヤ断線遮断回路、１１６…ボンディングワイヤ断線検出回路、１２１…電源用電極リード、１２２…入力信号用電極リード、１２３…出力信号用電極リード、１２５ａ…ワイヤ、１２５ｂ…ワイヤ、２００…パッケージ基板、２００…半導体試験装置、２０１…電流センサ、２０２…判定部、２１０…半導体チップ、２１１…集積回路部、２１２…電源用電極パッド、２１２ａ…第１電源用電極パッド、２１２ｂ…第２電源用電極パッド、２１２ｃ…第３電源用電極パッド、２１３…入力信号用電極パッド、２１４…論理積回路、２１５…ボンディングワイヤ断線遮断回路、２１６…ボンディングワイヤ断線検出回路、２２１…電源用電極リード、２２２…入力信号用電極リード、２２５ａ…ワイヤ、２２５ｂ…ワイヤ、２２５ｃ…ワイヤ、４００…パッケージ基板、４１０…半導体チップ、４１１…集積回路部、４１２…電源用電極パッド、４１２ａ…第１電源用電極パッド、４１２ｂ…第２電源用電極パッド、４１３…入力信号用電極パッド、４１４…出力信号用電極パッド、４２１…電源用電極リード、４２２…入力信号用電極リード、４２３…出力信号用電極リード、４２５ａ…ワイヤ、４２５ｂ…ワイヤ DESCRIPTION OF SYMBOLS 10 ... Semiconductor device, 20 ... Semiconductor device, 40 ... Semiconductor device, 100 ... Package substrate, 110 ... Semiconductor chip, 111 ... Integrated circuit part, 112 ... Power supply electrode pad, 112a ... 1st power supply electrode pad, 112b ... 1st 2 Electrode pads for power supply, 113... Electrode pad for input signal, 114... Electrode pad for output signal, 115... Bonding wire disconnection circuit, 116. Electrode leads, 123 ... Output signal electrode leads, 125a ... Wire, 125b ... Wire, 200 ... Package substrate, 200 ... Semiconductor test apparatus, 201 ... Current sensor, 202 ... Determining unit, 210 ... Semiconductor chip, 211 ... Integrated circuit unit 212 ... Power supply electrode pads, 212a ... First power supply electrode pads, 212b ... 2 power supply electrode pads, 212c ... third power supply electrode pads, 213 ... input signal electrode pads, 214 ... AND circuit, 215 ... bonding wire breakage cutoff circuit, 216 ... bonding wire breakage detection circuit, 221 ... power supply electrodes Lead, 222 ... Input signal electrode lead, 225a ... Wire, 225b ... Wire, 225c ... Wire, 400 ... Package substrate, 410 ... Semiconductor chip, 411 ... Integrated circuit part, 412 ... Power supply electrode pad, 412a ... First power supply Electrode pads, 412b ... second power supply electrode pads, 413 ... input signal electrode pads, 414 ... output signal electrode pads, 421 ... power supply electrode leads, 422 ... input signal electrode leads, 423 ... output signal electrodes Lead, 425a ... wire, 425b ... wire
Claims (5)
前記電源用電極リードと個別にワイヤボンディングされる複数の電源用電極パッドと、
前記複数の電源用電極パッドを介して動作電源の供給を受ける回路部とを備え、
各電源用電極パッドから前記回路部に至るそれぞれの経路上に、他の電源用電極パッドに電源電圧が印加された場合に導通状態となるスイッチを設けたことを特徴とする半導体装置。 A power electrode lead;
A plurality of power supply electrode pads individually wire-bonded to the power supply electrode leads;
A circuit unit that receives operation power through the plurality of power supply electrode pads,
A semiconductor device comprising: a switch that is turned on when a power supply voltage is applied to another power supply electrode pad on each path from each power supply electrode pad to the circuit portion.
各電源用電極パッドと前記入力信号用電極パッドとの間に、抵抗と、前記入力信号用電極方向を順方向とした整流素子とを直列に接続したことを特徴とする請求項１に記載の半導体装置。 It further comprises an input signal electrode pad,
The resistor and a rectifying element having a forward direction in the direction of the input signal electrode are connected in series between each power supply electrode pad and the input signal electrode pad. Semiconductor device.
前記電源用電極リードに電源電圧を供給する端子と、
前記入力信号用電極パッドから出力される電流の値に基づいて、前記電源用電極リードにボンディングされたワイヤの断線を判定する判定部と、を備えたことを特徴とする半導体試験装置。 A semiconductor test apparatus for testing the semiconductor device according to claim 2,
A terminal for supplying a power supply voltage to the electrode lead for power supply;
A semiconductor testing apparatus comprising: a determination unit that determines a breakage of a wire bonded to the power electrode lead based on a value of a current output from the input signal electrode pad.
前記電源用電極リードに電源電圧を供給する端子と、
前記電源用電極リードにボンディングされたワイヤの断線がない場合に各抵抗を流れるべき電流の値と、前記入力信号用電極パッドから出力される電流の測定値とに基づいて、どのワイヤで断線が生じたかを判定する判定部と、を備えたことを特徴とする半導体試験装置。 A semiconductor test apparatus for testing the semiconductor device according to claim 3,
A terminal for supplying a power supply voltage to the electrode lead for power supply;
Based on the value of the current that should flow through each resistor when there is no disconnection of the wire bonded to the power supply electrode lead, and the measured value of the current output from the input signal electrode pad, which wire is disconnected A semiconductor test apparatus comprising: a determination unit that determines whether the error occurred.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9726709B2 (en) | 2015-02-06 | 2017-08-08 | Toyota Jidosha Kabushiki Kaisha | Semiconductor chip and method for detecting disconnection of wire bonded to semiconductor chip |
| WO2020055772A1 (en) * | 2018-09-14 | 2020-03-19 | Teradyne, Inc. | Method and apparatus for bond wire testing in an integrated circuit |
| JP2021150441A (en) * | 2020-03-18 | 2021-09-27 | 株式会社リコー | Inspection system |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9726709B2 (en) | 2015-02-06 | 2017-08-08 | Toyota Jidosha Kabushiki Kaisha | Semiconductor chip and method for detecting disconnection of wire bonded to semiconductor chip |
| WO2020055772A1 (en) * | 2018-09-14 | 2020-03-19 | Teradyne, Inc. | Method and apparatus for bond wire testing in an integrated circuit |
| US10955465B2 (en) | 2018-09-14 | 2021-03-23 | Teradyne, Inc. | Method and apparatus for bond wire testing in an integrated circuit |
| CN112689768A (en) * | 2018-09-14 | 2021-04-20 | 泰瑞达公司 | Method and apparatus for wire bonding testing in integrated circuits |
| TWI834684B (en) * | 2018-09-14 | 2024-03-11 | 美商泰瑞達公司 | Method and apparatus for bond wire testing in an integrated circuit |
| JP2021150441A (en) * | 2020-03-18 | 2021-09-27 | 株式会社リコー | Inspection system |
| JP7392533B2 (en) | 2020-03-18 | 2023-12-06 | 株式会社リコー | inspection system |
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