JP2007234816A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which the output voltage of its built-in constant voltage circuit can be precisely measured when a rated current is outputted from the circuit. <P>SOLUTION: The semiconductor device (100) of this invention is equipped with a semiconductor chip (110) with an output pad (Cout1), and a package (120) with an external terminal (Out) connected to the output pad (Cout1) with an interconnection (21). The semiconductor chip (110) is furthermore equipped with an external terminal voltage measuring pad (Cout2) for measuring the voltage of the external terminal (Out), the external terminal (Out) and the external terminal voltage measuring pad (Cout2) are connected together, and the voltage of the external terminal (Out) is measured through the intermediary of the external terminal voltage measuring pad (Cout2). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to inspection of a semiconductor device having a built-in constant voltage circuit, and more particularly to a semiconductor device capable of accurately measuring an output voltage of a constant voltage circuit.

  Conventionally, in a semiconductor device incorporating a constant voltage circuit, an output voltage is inspected when a rated current is output.

  FIG. 1 is a measurement circuit diagram of a semiconductor device incorporating a conventional constant voltage circuit. In FIG. 1, the semiconductor device 1 includes a semiconductor chip 10, a package 20, and wirings 21 and 23, and loads are loaded via first and second external terminals Out and TST provided in the package 20. 2 and tester 3.

  The semiconductor chip 10 includes a reference voltage Vref, an error amplification circuit 11, an output transistor M1, a constant voltage circuit 30 including output voltage detection resistors R1 and R2, and switch means SW1, SW2, and SW3. Further, the semiconductor chip 10 includes an output pad Cout1 and a test pad Ctst. The output of the constant voltage circuit 30 is connected to the output pad Cout1.

  The output pad Cout1 is connected to the first external terminal Out on the package 20 via the wiring 21, and the test pad Ctst is connected to the second external terminal TST on the package 20 via the wiring 23. Has been. The wirings 21 and 23 have rewiring formed on the package 20, wire bonding for connecting the pads of the semiconductor chip 10 and the electrodes on the package 20, and through holes formed in the package 20.

  One ends of the switch means SW1, SW2 and SW3 are all connected in common and connected to the test pad Ctst. A signal S1 is connected to the other end of the switch means SW1, an output of the constant voltage circuit 30 is connected to the other end of the switch means SW2, and a signal S3 is connected to the other end of the switch means SW3. The switch means SW1, SW2, and SW3 are selectively turned on / off in synchronization with the measurement items of the tester 3 by a control circuit (not shown). The signals S1 and S3 are signals necessary for the inspection of the semiconductor chip 10, and are electrical information signals such as voltage, current, and resistance value generated in the semiconductor chip 10. Although only two signals S1 and S3 are shown in FIG. 1, any number of signals may actually exist.

  When measuring the output voltage of the constant voltage circuit 30, the switch means SW2 is turned on and the output voltage of the constant voltage circuit 30 is connected to the test pad Ctst, so that the tester 3 is connected to the second external terminal TST. , The output voltage of the constant voltage circuit 30 can be measured.

As described above, a method for measuring the output voltage of the constant voltage circuit via the switch means provided in the semiconductor chip is also disclosed in, for example, Japanese Patent Laid-Open No. 2002-168914 (Patent Document 1).
JP 2002-168914 A

  However, when measuring the output voltage of the constant voltage circuit at the rated current output in the conventional semiconductor device shown in FIG. 1, in addition to the voltage at both ends of the load 2 that should be originally measured at the external terminal Out, There is a problem that a voltage drop due to the wiring 21 from the pad Cout1 to the first external terminal Out appears as an error. For example, when the wiring resistance from the output pad Cout1 to the first external terminal Out is 0.1Ω and the rated current of the constant voltage circuit is 100 mA, the voltage drop due to the resistance of the wiring 21 is 10 mV. The voltage drop increases in proportion to the magnitude of the rated current.

  In recent years, as the operating voltage of semiconductor devices has been lowered, the operating voltage range of semiconductor devices connected as loads has become narrower, and some of them have an extremely narrow operating voltage range of ± 80 mV. In a semiconductor device having such an operating range, a voltage drop that occurs in the wiring 21 described above cannot be ignored.

  In view of the above problems, an object of the present invention is to provide a semiconductor device capable of accurately measuring an output voltage at the time of rated current output of a built-in constant voltage circuit.

  In order to achieve the above object, a semiconductor device of the present invention is a semiconductor device comprising a semiconductor chip having an output pad, and a package having an external terminal connected to the output pad by wiring. The semiconductor chip further includes an external terminal voltage measurement pad for measuring the voltage of the external terminal, and connects the external terminal and the external terminal voltage measurement pad, via the external terminal voltage measurement pad. The voltage of the external terminal is measured.

  Thereby, it is possible to provide a semiconductor device capable of accurately measuring the output voltage at the rated current output of the built-in constant voltage circuit. Note that there may be a plurality of external terminals and corresponding output pads, and a plurality of external terminal voltage measurement pads are provided accordingly.

  In order to achieve the above object, in the semiconductor device of the present invention, the semiconductor chip further includes a test pad for measuring the voltage of the external terminal, and the external terminal voltage measurement pad is It is connected to a test pad.

  As a result, a semiconductor device capable of measuring the output voltage of the built-in constant voltage circuit with an external tester can be provided.

  In order to achieve the above object, in the semiconductor device of the present invention, the semiconductor chip further includes a switch means, and the external terminal voltage measurement pad is connected to the test pad via the switch means. It is characterized by being.

  Thereby, a semiconductor device capable of measuring the output voltage only in a predetermined case, for example, when a rated current is output from a built-in constant voltage circuit can be provided.

  In order to achieve the above object, according to the semiconductor device of the present invention, a voltage drop between the external terminal voltage measurement pad and the external terminal is a voltage drop between the output pad and the external terminal. It is characterized by being smaller than.

  Thereby, when measuring the output voltage of the built-in constant voltage circuit, it is possible to provide a semiconductor device capable of reducing the influence of a voltage drop due to wiring.

  In order to achieve the above object, in the semiconductor device of the present invention, the semiconductor chip further includes a constant voltage circuit, and the output pad is connected to an output of the constant voltage circuit. And

  Thus, it is possible to provide a semiconductor device capable of preventing almost no current from flowing between the external terminal voltage measurement pad for measuring the output voltage of the built-in constant voltage circuit and the external terminal. .

  In order to achieve the above object, the semiconductor device of the present invention includes a wiring between the external terminal voltage measurement pad and the external terminal, and a wiring between the output pad and the external terminal. , Characterized in that they have some common parts.

  Thus, it is possible to provide a semiconductor device capable of sharing a part of wiring between an external terminal voltage measurement pad and an output pad and an external terminal when there is a problem such as a lack of space. Can do. However, such a wiring layout can be obtained only when the operating voltage range of the load connected to the semiconductor device is relatively large.

  In order to achieve the above object, the semiconductor device of the present invention is characterized in that the common part is a wiring including a through hole on the package.

  Thus, it is possible to provide a semiconductor device capable of minimizing the common portion as much as possible when a part of the wiring between the external terminal voltage measurement pad and the output pad and the external terminal is common. Can do.

  In order to achieve the above object, the semiconductor device according to the present invention includes a rewiring in which the wiring between the external terminal voltage measurement pad and the output pad and the external terminal is formed on the package. It is characterized by having.

  Thus, a semiconductor device that can be miniaturized can be provided.

  In order to achieve the above object, the semiconductor device of the present invention is characterized in that the external terminal voltage measurement pad and the wiring between the output pad and the external terminal have wires.

  As a result, it is possible to provide a semiconductor device capable of performing appropriate wiring layout even when rewiring cannot be formed on the package.

  According to the present invention, it is possible to provide a semiconductor device capable of accurately measuring an output voltage when a built-in constant voltage circuit outputs a rated current.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Throughout the drawings, components having the same function are given the same reference numerals.

  FIG. 2 is a measurement circuit diagram of the semiconductor device showing the embodiment of the present invention. In FIG. 2, the semiconductor device 100 includes a semiconductor chip 110, a package 120, and wirings 21, 22, and 23, and the first and second external terminals Out and TST provided in the package 120 are respectively connected. Are connected to the load 2 and the tester 3.

  The semiconductor chip 110 includes a reference voltage Vref, an error amplifier circuit 11, an output transistor M1, a constant voltage circuit 30 including output voltage detection resistors R1 and R2, and switch means SW1, SW2, and SW3. Further, the semiconductor chip 110 includes an output pad Cout1, an external terminal voltage measurement pad Cout2, and a test pad Ctst. The output of the constant voltage circuit 30 is connected to the output pad Cout1.

  The output pad Cout1 and the external terminal voltage measurement pad Cout2 are connected to the first external terminal Out on the package 120 via wirings 21 and 22, respectively, and the test pad Ctst is connected via the wiring 23. The second external terminal TST on the package 20 is connected. The wirings 21, 22, and 23 include rewiring formed on the package 120, wire bonding for connecting pads of the semiconductor chip 110 and electrodes on the package 120, and through holes formed in the package 120.

  One ends of the switch means SW1, SW2 and SW3 are all connected in common and connected to the test pad Ctst. A signal S1 is connected to the other end of the switch means SW1, an external terminal voltage measuring pad Cout2 is connected to the other end of the switch means SW2, and a signal S3 is connected to the other end of the switch means SW3. The switch means SW1, SW2, and SW3 are selectively turned on / off in synchronization with the measurement items of the tester 3 by a control circuit (not shown). Although only two signals S1 and S3 are shown in FIG. 2, any number of signals may actually exist.

  In the semiconductor device of the present invention shown in FIG. 2, an external terminal voltage measurement pad Cout2 is added to the semiconductor chip 110, and wiring is provided between the external terminal voltage measurement pad Cout2 and the first external terminal Out on the package 120. 1 is different from the conventional semiconductor device shown in FIG. Further, in the semiconductor device of FIG. 2, one of the terminals of the switch means SW2 is connected to the added external terminal voltage measurement pad Cout2 instead of the output of the constant voltage circuit 30.

  When the rated current is output from the constant voltage circuit 30 in the semiconductor device of FIG. 2, a large voltage drop occurs in the wiring 21 between the output pad Cout1 and the first external terminal Out. A voltage drop does not occur in the wiring 22 between the pad Cout2 and the first external terminal Out because no current flows. Therefore, the voltage of the external terminal voltage measurement pad Cout2 on the semiconductor chip 110 is the same as the voltage of the first external terminal Out on the package 120. When the switch means SW2 is turned on, the voltage is connected to the test pad Ctst. Therefore, the tester 3 can measure the accurate output voltage of the constant voltage circuit 30 via the second external terminal TST.

  Next, the structure of the semiconductor device of the present invention shown in FIG. 2 will be described with reference to specific examples.

  FIG. 3 is a side view showing the first embodiment of the structure of the semiconductor device of FIG.

  In FIG. 3, the semiconductor device 100 includes a semiconductor chip 110 and a package 120. The package 120 has a semiconductor chip 110 stacked on the upper surface thereof, and bumps Out as external terminals are formed on the rear surface thereof. The semiconductor chip 110 has an output pad Cout1 and an external terminal voltage measurement pad Cout2 formed on the upper surface thereof. Further, the semiconductor device 100 includes first and second wirings 21 and 22. The first wiring 21 has a first wire bonding 31, a rewiring formed on the upper surface of the package 120, and a first through hole 33, and an output pad formed on the upper surface of the semiconductor chip 110. Cout1 and the external terminal Out formed on the back surface of the package 120 are coupled. The second wiring 22 has a second wire bonding 32, a second through hole 34, and a rewiring formed on the back surface of the package 120, and an external terminal voltage formed on the upper surface of the semiconductor chip 110. The measurement pad Cout2 is coupled to the external terminal Out formed on the back surface of the package 120.

  As is apparent from the above, the first and second wirings 21 and 22 are independent of each other and do not have a common part except that they are connected to the external terminal Out. Therefore, the influence of the voltage drop of the first wiring 21 does not reach the second wiring 22. Such a structure is most ideal for accurately measuring the rated voltage of the constant voltage circuit at the rated current output.

  FIG. 4 is a side view showing a second example of the structure of the semiconductor device of FIG.

  In FIG. 4, the semiconductor device 100 includes a semiconductor chip 110 and a package 120. The package 120 has a semiconductor chip 110 stacked on the upper surface thereof, and bumps Out as external terminals are formed on the rear surface thereof. The semiconductor chip 110 has an output pad Cout1 and an external terminal voltage measurement pad Cout2 formed on the upper surface thereof. Further, the semiconductor device 100 includes first and second wirings 21 and 22. The first wiring 21 includes a first wire bonding 31, a rewiring formed on the upper surface of the package 120, and a through hole 41, and an output pad Cout 1 formed on the upper surface of the semiconductor chip 110; The external terminal Out formed on the back surface of the package 120 is coupled. The second wiring 22 has a second wire bonding 32, a rewiring formed on the upper surface of the package 120, and a through hole 41, and an external terminal voltage measurement pad formed on the upper surface of the semiconductor chip 110. Cout2 and the external terminal Out formed on the back surface of the package 120 are coupled.

  In the semiconductor device of FIG. 4, unlike FIG. 3, the first and second wirings 21 and 22 share one through hole 41. When a part of the wiring must be shared due to a problem such as space, the common part can be made as small as possible by using the common part as a through hole. In this case, although a voltage drop also occurs in the wiring 22, it can be ignored when the operating voltage range of the load connected to the constant voltage circuit is relatively large.

  FIG. 5 is a side view showing a third embodiment of the structure of the semiconductor device of FIG.

  In FIG. 5, a semiconductor device 100 includes a semiconductor chip 110 and a package 120, and is configured by a CSP (Chip Size Package). The semiconductor chip 110 has an output pad Cout1 and an external terminal voltage measurement pad Cout2 formed on the upper surface thereof. The package 120 is stacked on the upper surface of the semiconductor chip 110 so as to cover the output pad Cout1 and the external terminal voltage measurement pad Cout2, and a bump Out which is an external terminal is formed on the upper surface. Further, the package 120 includes first and second wirings 21 and 22. The first wiring 21 has a rewiring formed on the upper surface of the package 120, a third through hole 51, and a rewiring formed on the back surface of the package 120, and is formed on the upper surface of the package 120. The external terminal Out and the output pad Cout1 formed on the upper surface of the semiconductor chip 110 are coupled. The second wiring 22 has a fourth through hole 52 and a rewiring formed on the back surface of the package 120, and is formed on the external terminal Out formed on the top surface of the package 120 and on the top surface of the semiconductor chip 110. The external terminal voltage measurement pad Cout2 thus coupled is coupled.

  As described above, the semiconductor device of the present invention can also be configured by a CSP. Since the structure is CSP, unlike the structure shown in FIGS. 3 and 4, wire bonding is not required. Therefore, compared to the case where wire bonding is used, the resistance of the wirings 21 and 22 that couple the pad and the external terminal is reduced, so that the voltage drop generated in the wirings 21 and 22 is also reduced. However, in the structure shown in FIG. 5, since the first and second wirings 21 and 21 do not have a common portion except that they are connected to the external terminal Out, as in FIG. Then there is no voltage drop.

[Modification]
The present invention is not limited to the embodiments described above. For example, the semiconductor device of the present invention is not limited to the structure shown in FIGS. 3, 4, and 5, and can have various structures within the scope of the claims.

  The present invention is not limited to a constant voltage circuit, and can be applied to a semiconductor device in which some circuit is incorporated and its output voltage needs to be accurately measured.

It is a measurement circuit diagram of a conventional semiconductor device incorporating a constant voltage circuit. It is a measurement circuit diagram of a semiconductor device showing an example of the present invention. FIG. 3 is a side view illustrating a first example of the structure of the semiconductor device in FIG. 2. FIG. 3 is a side view illustrating a second example of the structure of the semiconductor device in FIG. 2. FIG. 6 is a side view illustrating a third embodiment of the structure of the semiconductor device in FIG. 2.

Explanation of symbols

1,100 Semiconductor device 2 Load 3 Tester 10, 110 Semiconductor chip 20, 120 Package 21, 22, 23 Wiring 30 Constant voltage circuit 31, 32 Wire bonding 33, 34, 41, 51, 52 Through hole SW1, SW2, SW3 Switch Means Out, TST External terminal Ctst, Cout1, Cout2 Pad

Claims (9)

In a semiconductor device comprising a semiconductor chip having an output pad and a package having an external terminal connected to the output pad by wiring,
The semiconductor chip further includes an external terminal voltage measurement pad for measuring the voltage of the external terminal,
A semiconductor device comprising: connecting the external terminal and the external terminal voltage measurement pad; and measuring the voltage of the external terminal via the external terminal voltage measurement pad. The semiconductor chip further includes a test pad for measuring the voltage of the external terminal,
The semiconductor device according to claim 1, wherein the external terminal voltage measurement pad is connected to the test pad. The semiconductor chip further includes switch means,
3. The semiconductor device according to claim 2, wherein the external terminal voltage measurement pad is connected to the test pad via the switch means.   4. The voltage drop between the external terminal voltage measurement pad and the external terminal is smaller than the voltage drop between the output pad and the external terminal. 5. A semiconductor device according to claim 1. The semiconductor chip further includes a constant voltage circuit,
The semiconductor device according to claim 1, wherein the output pad is connected to an output of the constant voltage circuit.   2. The wiring between the external terminal voltage measurement pad and the external terminal and the wiring between the output pad and the external terminal have a part in common. The semiconductor device according to claim 1.   The semiconductor device according to claim 6, wherein the common part is a wiring including a through hole on the package.   The wiring between the external terminal voltage measurement pad and the output pad and the external terminal includes a rewiring formed on the package. A semiconductor device according to item.   6. The semiconductor device according to claim 1, wherein the wiring between the external terminal voltage measurement pad and the output pad and the external terminal includes a wire.

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