JP5417912B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a test of a rewiring resistance value in a semiconductor device including a semiconductor chip and a package having a rewiring, and relates to a semiconductor device including a test circuit that can be easily and accurately measured.

FIG. 5 is a measurement circuit diagram of a semiconductor device incorporating a conventional constant voltage circuit.
In the figure, 1 is a semiconductor device, 2 is a load connected to a constant voltage circuit in the semiconductor device 1, and 3 is a tester for inspecting the semiconductor device 1. Further, the semiconductor device 1 includes a semiconductor chip 10 and a package 20 having rewiring.

  The semiconductor chip 10 includes a reference voltage Vref, an error amplifier circuit 11, an output transistor M1, a constant voltage circuit composed of output voltage detection resistors R1 and R2, and switch means SW1 to SW3. Further, the semiconductor chip 10 is provided with an output pad Cout1 of the constant voltage circuit, a test pad Ctst, and a pad Cout2 connected to an external terminal.

  The output pad Cout1 is connected to the external terminal Out of the semiconductor device 1 via the wiring 21 on the package 20, and the test pad Ctst is connected to the external terminal TST of the semiconductor device 1 via the wiring 23 on the package 20. Has been.

  The wiring 21 includes wire bonding for connecting the pads of the semiconductor chip 10 and the electrodes on the package 20, through holes provided in the package 20, and the like. The pad Cout2 is connected to the external terminal Out of the package via the wiring 22.

  One ends of the switch means SW1 to SW3 are all connected in common and connected to the test pad Ctst. The signal S1 is connected to the other end of the switch means SW1, and the other end of the switch means SW2 is connected to the pad Cout2. A signal S3 is connected to the other end of the switch means SW3.

  The switch means SW1 to SW3 are selectively ON / OFF controlled by a control circuit (not shown) in synchronization with the measurement items of the tester. The signals S <b> 1 to S <b> 3 are signals necessary for the inspection of the semiconductor chip 10, and are electrical information signals such as voltage, current, and resistance value generated in the semiconductor chip 10. Although only three are shown in FIG. 5, any number is possible.

  When measuring the output voltage of the constant voltage circuit, when the switch means SW2 is turned on, an external terminal is connected to the test pad Ctst, so that the tester 3 determines the external output terminal voltage of the constant voltage circuit via the external terminal TST. Can be measured.

  As described above, a method for measuring the output voltage of the constant voltage circuit via the switch means provided in the semiconductor chip is disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2007-234816).

However, in semiconductor devices with a semiconductor chip and a package with rewiring, the manufacturing variation in rewiring film thickness is as large as ± 20% to 30%, and the output voltage when the rated current is output from the constant voltage circuit is measured. In this case, the variation in voltage drop due to the wiring 21 from the output pad Cout1 to the external terminal Out increases.

  If the wiring resistance from the output pad Cout1 to the external terminal Out is 0.1Ω and the rated load current of the constant voltage circuit is 300 mA, the voltage drop due to the resistance of the wiring 21 should be 30 mV, but 21 mV to 39 mV It will vary by 18 mV. Furthermore, as the rated current increases, the voltage drop increases proportionally.

  In addition, manufacturing variations in the output voltage drop (load stability) of the constant voltage circuit itself are ± 10% to 30%, so even if the drop in the external output terminal voltage is measured, the variation in the rewiring film thickness can be accurately determined. Cannot be detected.

  In recent years, as the operating voltage of semiconductor devices has been lowered, the operating voltage range of semiconductor devices connected as a load has been narrowed, and a severe one of ± 80 mV has come out. In such an operating range, the voltage drop variation caused by the wiring 21 cannot be ignored.

At this time, it is possible to shorten the rewiring length as much as possible to reduce the voltage drop amount . However, since the constant voltage circuit secures the phase margin with the output capacitor Cout and its series equivalent resistance ESR, if the resistance falls below a predetermined resistance value due to variations in the rewiring resistance value, a fatal problem of oscillation occurs. Will occur . Therefore, the rewiring resistance value is not necessarily small.
Regarding rewiring technology, refer to Patent Document 2 (Japanese Patent No. 3856304) if necessary.

  The present invention has been made in consideration of the above-described circumstances, and is a semiconductor device that can easily and accurately detect whether the rewiring resistance value of the constant voltage circuit is within a desired range. The purpose is to provide.

The present invention employs the following configuration in order to achieve the above object.
a) a first aspect of the invention, a first semiconductor chip having a first pad and the second pad and the test pad of the external terminal voltage measurement for at least an output, wherein the semiconductor chip is connected to the loaded and the load A package provided with the external terminals, a first wiring connecting the first pad and the first external terminal, and a second wiring connecting the first external terminal and the second pad. In the semiconductor device in which each of the first and second wirings includes a rewiring formed in the package, switch means for selectively switching and connecting the first pad and the second pad to the test pad And the switch means connects the first pad to the test pad, so that the voltage of the first wiring is passed through the test pad. By connecting the second pad to the test pad by the switch means, the voltage of the first external terminal can be set to the second wiring, the second pad, and the test It is provided so that measurement is possible via a pad . This makes it possible to measure the output voltage of a constant voltage circuit or the like and the accurate voltage of the external terminal.
According to a second aspect of the present invention, there is provided a semiconductor chip having at least a first pad for output and a second pad for measuring an external terminal voltage, a first external terminal on which the semiconductor chip is mounted and connected to a load; A package provided with a second external terminal for voltage measurement, a first wiring connecting the first pad and the first external terminal, and connecting the first external terminal and the second pad. In a semiconductor device comprising a second wiring, wherein each of the first and second wirings includes a rewiring formed in the package, the first pad and the second pad are connected to the second external terminal. Switch means for selectively switching connection is provided, and the first pad is connected to the second external terminal by the switch means, whereby the voltage of the first wiring is reduced to the second external terminal. The second pad is connected to the second external terminal by the switch means, and the voltage of the first external terminal is connected to the second wiring and the switch. It is possible to measure through the means and the second external terminal.
This makes it possible to measure the output voltage of a constant voltage circuit or the like and the accurate voltage of the external terminal.

b) The semiconductor chip further includes a test pad, and the first pad or the second pad can be connected to the test pad . In this case, the external terminals can be accurately measured by a tester provided outside the semiconductor device.

c) The semiconductor chip has switch means, and the first pad, the second pad and the test pad can be connected via the switch means . In this case, the voltage of the external terminal can be measured by a tester provided outside the semiconductor device.

d) In addition, the switch means can selectively connect either the first pad or the second pad to the test pad of the semiconductor chip . In this case, the voltage of the external terminal can be measured by a tester provided outside the semiconductor device by selecting the first pad or the second pad by the switch means.

e) Further, the voltage drop due to the current flowing through the wiring connecting the second pad and the external terminal can be made smaller than the voltage drop due to the current flowing through the wiring connecting the first pad and the external terminal. . In this case, the influence of the voltage drop due to the current flowing in the wiring connecting the second pad and the external terminal can be minimized.

f) Further, the wiring between the first pad and the external terminal and the wiring between the second pad and the external terminal have a part in common, and the common part is on the package. A wiring including a rewiring portion in the through hole can be obtained. In this case, there is a part in common depending on the size of the package and the layout of the external terminals, but the number of wirings including the rewiring part in the through hole is reduced as much as possible.

g) The semiconductor chip may include an electronic circuit, and the first pad may be connected to an output of the electronic circuit . In this case, almost no current flows between the second pad and the external terminal.

h) The semiconductor chip includes a plurality of electronic circuits, each of the electronic circuits has a configuration similar to the first pad, the second pad, and the switch means, and further defines the electronic circuit. It can be a voltage circuit . In this case, the output voltage of the desired electronic circuit (constant voltage circuit) and the external output terminal voltage can be measured by a tester provided outside the semiconductor device. As a result, when an output current is output from the constant voltage circuit to the external load, the output voltage of the constant voltage circuit and the external output terminal voltage can be measured, and the rewiring resistance value between them can be easily detected. It becomes like this.

According to the present invention, the rewiring resistance value between the first pad (output voltage measuring pad) and the second pad (package external output terminal voltage measuring pad) can be easily detected. Can be easily and accurately detected by the tester. As a result, even if the rewiring film thickness varies widely, it is possible to reliably reject non-standard products.

It is a measurement circuit diagram of a semiconductor device showing an example of the present invention. 1 is an example showing a first configuration of a semiconductor device 1. 2 is an example showing a second configuration of the semiconductor device 1; 3 is an example showing a third configuration of the semiconductor device 1. It is a measurement circuit diagram of a semiconductor device incorporating a conventional constant voltage circuit.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a measurement circuit diagram of a semiconductor device showing an embodiment of the present invention.
The difference from FIG. 5 is that the switch means SW4 is added to the semiconductor chip 10, and the pads Cout1 and Cout2 are further connected to the switch means SW2 via the switch means SW4.
As is clear from FIG. 1, the switch means SW4 is configured to turn off the connection between the switch means SW2 and the pad Cout2 when the switch means SW2 is connected to the pad Cout1. Further, the switch means SW4 is configured to turn off the connection between the switch means Sw2 and the pad Cout1 when the switch means Sw2 is connected to the pad Cout2. As described above, the switch means Sw4 can switch-connect the switch means Sw2 to the pads Cout1 and Cout2 as is apparent from FIG.

When a large current is supplied from the constant voltage circuit 30 to the external load 2, a large voltage drop occurs in the first wiring 21 between the pad Cout1 and the external terminal Out (first external terminal), but the pad Cout2 and the external terminal since the second no current flows through the wire 22 between Out, the voltage drop does not occur.

Therefore, the voltage of the pad Cout2 external terminal Out the same voltage and ing. Accordingly, the switch means SW4 is switched and connected to the pad Cout2 side, and the voltage of the pad Cout2 is applied to the tester via the switch means SW4, the switch means SW2, the test pad Ctst, and the external terminal TST (second external terminal). depending on entering, it is possible to measure the output voltage of accurate external terminal Out (first external terminal).

At this time, the switch means SW4 is further switched and connected to the pad Cout1, and the voltage of the pad Cout1 is input to the tester 3 via the switch means SW4, the switch means SW2, the test pad Ctst, and the external terminal TST. Then, the voltage of the pad Cout1 can be measured.
The rewiring resistance value can be easily and accurately detected using the above measurement results.

  FIG. 2 is an example showing a first configuration of the semiconductor device 1. The same functional parts as those in FIG. 1 are given the same numbers and symbols.

In FIG. 2, the semiconductor device 1 includes a semiconductor chip 10 and a package 20. The package 20 has the semiconductor chip 10 mounted on the upper surface thereof, and external terminals Out (bumps Out, that is, first external terminals) are formed on the back surface thereof. The semiconductor chip 10 has an output pad Cout1 (output first pad) and an external terminal voltage measurement pad Cout2 (external terminal voltage measurement second pad) formed on the upper surface (outer surface) thereof.

Further, the semiconductor device 10 includes a first wiring 21 and a second wiring 22.
As is clear from FIG. 2 , the first wiring 21 has a first wire bonding 31 and a rewiring formed on the package 20 . This rewiring is performed by a rewiring portion 21a formed on the upper surface (outer surface) of the package 20 , and a rewiring portion connected to the rewiring portion 21a and formed in the first through hole 33 (inner surface). 33a . The first through hole 33 penetrates from the upper surface (outer surface) to the back surface of the package 20. Further, as is clear from FIG. 2, the rewiring portion 33 a is formed so that the outer surface is in close contact with the inner surface of the first through hole 33. The first broken line 21 having the first wire bonding 31 and the rewiring as described above couples the output pad Cout1 formed on the upper surface of the semiconductor chip 10 and the external terminal Out formed on the back surface of the package 20. To do.

As is apparent from FIG. 2 , the second wiring 22 has a second wire bonding 32 and a rewiring formed on the package 20. As is apparent from FIG. 2, the rewiring is formed in the second through hole 34 and has an axial rewiring 34a whose outer peripheral surface is in close contact with the inner surface of the second through hole 34, and the rewiring 34a. And a rewiring portion 22 a formed on the back surface (outer surface) of the package 20 . The second through hole 34 penetrates from the upper surface (outer surface) to the back surface of the package 20. The second wire bonding 32 and the second wiring 22 having the rewiring include the external terminal voltage measurement pad Cout2 formed on the upper surface of the semiconductor chip 10 and the external terminal Out formed on the back surface of the package 20. And combine.

  As is clear from the above, the first wiring 21 and the second wiring 22 are independent of each other and have no common part except that they are connected to the external terminal Out. Therefore, the influence of the voltage drop of the first wiring 21 does not reach the second wiring 22. Such a structure is most desirable in order to accurately measure the rated voltage of the constant voltage circuit at the rated current output.

  FIG. 3 is an example showing a second configuration of the semiconductor device 1. The same functional parts as those in FIG. 2 are given the same numbers and symbols.

In FIG. 3, the semiconductor device 1 includes a semiconductor chip 10 and a package 20. The package 20 has the semiconductor chip 10 mounted on the upper surface thereof . Further, as is apparent from FIG. 3, protruding external terminals Out (bump Out, ie, first external terminals) are formed on the back surface of the package 20 . The semiconductor chip 10 has an output pad Cout1 and an external terminal voltage measurement pad Cout2 formed on the upper surface thereof.

Further, the semiconductor device 10 includes a first wiring 21 and a second wiring 22. As is apparent from FIG. 3 , the first wiring 21 has a first wire bonding 31 and a rewiring formed on the package 20 . As is apparent from FIG. 3, the rewiring is performed by a rewiring portion 21a formed on the outer surface of the package 20, and a shaft-like rewiring formed in the common through hole 41 and connected to the rewiring portion 21a. It has the wiring part 41a. The common through hole 41 penetrates from the upper surface (outer surface) to the back surface of the package 20. Further, as is clear from FIG. 3, the rewiring portion 41 a is formed so that the outer peripheral surface is in close contact with the inner surface of the common through hole 41. The first wire bonding 31 and the first wiring 21 having rewiring are coupled to the output pad Cout1 formed on the upper surface of the semiconductor chip 10 and the external terminal Out formed on the back surface of the package 20. To do.

As apparent from FIG. 3 , the second wiring 22 has a second wire bonding 32 and a rewiring formed on the package 20 . In this rewiring, a rewiring portion 22a formed on the upper surface (outer surface) of the package 20 and a shaft-shaped rewiring portion 41a connected to the rewiring portion 22a and formed in the common through hole 41 are used. Have. As is clear from FIG. 3, the rewiring portion 41 a in the common through hole 41 is formed so as to be in close contact with the inner surface of the common through hole 41. Further, as is apparent from FIG. 3, the rewiring portion 41a is connected to the rewiring portion 21a of the first wiring 21 and the rewiring portion 22a of the second wiring 22 by one end. It is used as a common part of the rewiring of the first and second wirings 21 and 22. The second wiring 22 having such wire bonding 32 and rewiring couples the external terminal voltage measurement pad Cout2 formed on the upper surface of the semiconductor chip 10 and the external terminal Out formed on the back surface of the package 20. To do.

3 differs from FIG. 2 in that the first wiring 21 and the second wiring 22 share the rewiring portion 41a in the same common through hole 41.
When a part of the wiring must be made common due to a problem such as space, the common part can be made as small as possible by using the common part as the rewiring part 41a in the common through hole 41 .
In this case, a voltage drop also occurs in the second wiring 22, but it can be ignored when the operating voltage range of the load connected to the constant voltage circuit is relatively large, and the rewiring resistance can be detected. Is possible.

  FIG. 4 shows an embodiment in which the third configuration of the semiconductor device 1 is applied to a CSP (chip size package). The same functional parts as those in FIG. 2 are given the same numbers and symbols.

In this example, as is apparent from FIG. 4, the first wiring 21 is a rewiring including rewiring portions 21a, 21b, and 51a, and the second wiring 22 is a rewiring including wiring portions 22a and 52a. . The pads Cout1 and Cout2 provided on the lower surface (back surface) of the semiconductor chip 10 are connected to the film-like rewiring portions 21b and 22a on the lower surface of the package 20, as is apparent from FIG . The rewiring portion 21 b is connected to the lower end of the axial rewiring portion 51 a in the through hole 51, and the rewiring portion 22 a is connected to the lower end of the axial rewiring portion 52 a in the through hole 52. The through holes 51 and 52 penetrate from the upper surface (outer surface) to the back surface of the package 20.
Further, as is apparent from FIG. 4, the rewiring portions 51 a and 52 a are formed so that the outer surfaces are in close contact with the inner surfaces of the through holes 51 and 52. Further, the rewiring portion 5 a in the through hole 51 is connected to the rewiring portion 21 a on the upper surface (outer surface) of the package 20 at the upper end. The rewiring unit 2 a is connected to the external terminal Out on the upper surface of the package 20. Further, the upper end of the rewiring portion 52 a in the through hole 52 is connected to the external terminal Out on the upper surface of the package 20. Thus, the pads Cout1 and Cout2 are connected to the external terminal Out provided on the upper surface of the package 20 via the first and second wirings 21 and 22.

More specifically, in FIG. 4, the semiconductor device 1 includes a semiconductor chip 10 and a package 20 and is configured by CSP (Chip Size Package). The semiconductor chip 10 has an output pad Cout1 and an external terminal voltage measurement pad Cout2 formed on the lower surface thereof.

As is apparent from FIG. 4 , the package 20 is stacked on the upper surface of the semiconductor chip 10 so as to cover the output pad Cout1 and the external terminal voltage measurement pad Cout2, and the upper surface thereof has a protruding (bump) -like external terminal. Out (bump Out) is formed.

Further, the package 20 has a first wiring 21 and a second wiring 22.
As apparent from FIG. 4 , the first wiring 21 has a rewiring formed in the package 20 . This rewiring is performed by a rewiring portion 21a formed on the upper surface (outer surface) of the package 20 , and a rewiring portion 51a connected to the rewiring portion 21a and formed in the third through hole 51 (inner surface). And a rewiring portion 21b that is connected to the rewiring portion 51a and formed on the back surface (outer surface) of the package 20 . The first wiring 21 having such a rewiring couples the external terminal Out formed on the upper surface of the package 20 and the output pad Cout1 formed on the upper surface of the semiconductor chip 10.

As apparent from FIG. 4 , the second wiring 22 has a rewiring formed in the package 20. This rewiring is formed in the fourth through hole 52 and has an axial rewiring portion 52a whose outer surface is in close contact with the inner surface of the fourth through hole 32, and is connected to the rewiring portion 52a and is packaged. And a rewiring 22a formed on the back surface (outer surface) of 120 . The second wiring 22 having such a rewiring couples the external terminal Out formed on the upper surface of the package 120 and the external terminal voltage measurement pad Cout2 formed on the upper surface of the semiconductor chip 110.

As described above, the semiconductor device of the present invention can also be configured by a CSP. Since the structure is CSP, wire bonding is not required unlike the structures shown in FIGS.
Therefore, compared to the case where wire bonding is used, the resistance of the first wiring 21 and the second wiring 22 that couple the pad and the external terminal is reduced, so that the voltage generated in the first wiring 21 and the second 22 is reduced. The descent is also reduced. However, in the structure shown in FIG. 4, since the first wiring 21 and the second wiring 22 do not have a common part except that they are connected to the external terminal Out, as in FIG. At 22 no voltage drop occurs.

  As described above, according to the present invention, the output measurement pad of the constant voltage circuit and the external output terminal measurement pad voltage provided in the package can be measured, and the rewiring resistance value can be easily detected.

  In addition, this invention is not limited to the Example mentioned above. For example, the semiconductor device of the present invention is not limited to the structure shown in FIGS. 2, 3 and 4, and can have various structures within the scope of the claims.

  In the above embodiment, an example is shown in which one constant voltage circuit is built in the semiconductor chip 1 and its output is connected to the output pad Cout1, but two or more constant voltage circuits similar to those in FIG. 1 are built in. Then, the output may be connected to output pads provided corresponding to the outputs.

  In the above embodiments, the constant voltage circuit is described as an example of the electronic circuit for measuring the output voltage. However, the present invention is not limited to the constant voltage circuit, and any circuit that needs to accurately measure the output voltage. It can also be applied to.

1: Semiconductor device 2: Load 3: Tester 10: Semiconductor chip 11: Error amplifier circuit 20: Package
21-23: Wiring
21a: Rewiring section
22a: Rewiring section
22b: Rewiring unit 30: Constant voltage circuit 31, 32: Wire bonding
33, 34: Through hole
33a, 34a: Rewiring unit
41: Common through hole
41a: Rewiring section
51, 52: Through hole
51a, 52a: Rewiring unit
Vref: reference voltage M1: output transistors R1, R2: resistors SW1 to SW4: switch means Out:
TST: External terminal Ctst: Test pad Cout1: Output pad (first pad)
Cout2: Pad (second pad)

JP 2007-234816 A Japanese Patent No. 3856304

Claims (6)

A semiconductor chip having at least a first pad for output, a second pad for measuring external terminal voltage, and a test pad ;
A package on which the semiconductor chip is loaded and provided with a first external terminal connected to the load ;
A first wiring connecting the first pad and the first external terminal;
A second wiring connecting the first external terminal and the second pad;
In the semiconductor device, wherein the first and second wirings each include a rewiring formed in the package ,
Switch means for selectively switching and connecting the first pad and the second pad to the test pad is provided,
By connecting the first pad to the test pad by the switch means, the voltage of the first wiring can be measured through the test pad, and the second pad is provided by the switch means. Is connected to the test pad so that the voltage of the first external terminal can be measured through the second wiring, the second pad, and the test pad. Semiconductor device. A semiconductor chip having at least a first pad for output and a second pad for measuring an external terminal voltage ;
A package on which the semiconductor chip is mounted and provided with a first external terminal connected to the load and a second external terminal for voltage measurement ;
A first wiring connecting the first pad and the first external terminal;
A second wiring connecting the first external terminal and the second pad;
In the semiconductor device, wherein the first and second wirings each include a rewiring formed in the package ,
Switch means for selectively switching and connecting the first pad and the second pad to the second external terminal;
By connecting the first pad to the second external terminal by the switch means, the voltage of the first wiring can be measured via the second external terminal, and by the switch means By connecting the second pad to the second external terminal, the voltage of the first external terminal can be measured via the second wiring, the switch means, and the second external terminal. wherein a is. The semiconductor device according to claim 1 or 2,
The semiconductor device, wherein the semiconductor chip has the switch means . The semiconductor device according to any one of claims 1 to 3 ,
2. A semiconductor device according to claim 1, wherein a voltage drop caused by a current flowing through a wiring connecting the second pad and the external terminal is smaller than a voltage drop caused by a current flowing through a wiring connecting the first pad and the external terminal. The semiconductor device according to any one of claims 1 to 4 ,
The package includes a through hole that penetrates from the upper surface that is the outer surface to the rear surface that is the outer surface,
The rewiring formed in the package includes a film-shaped rewiring portion formed on the outer surface of the package, a continuous connection with the film-shaped rewiring portion, and formed in the through hole, and has an outer peripheral surface. A semiconductor device comprising an axial rewiring portion that is in close contact with the inner surface of the through hole . The semiconductor device according to claim 5,
The rewiring of the first and second wirings includes the shaft-shaped rewiring part formed in the through hole of the package as a common rewiring part .