JP2011158347A - Semiconductor device and inspection system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately inspect a connection state of a semiconductor device without any destruction. <P>SOLUTION: The semiconductor device 1 is configured by mounting a semiconductor chip 3 on a mounting substrate 2 and includes a power transmission section of transmitting power supplied from outside to an internal circuit 30 of the semiconductor chip 3. The power transmission section is provided on the mounting substrate 2 and includes: a power input terminal of inputting power supplied from outside; inspection input terminal of conducting an inspection of a connection condition between the mounting substrate 2 and the semiconductor chip 3, being provided on the mounting substrate 2; a plurality of power circuits of distributing power input from the power input terminal and transmitting the power to the internal circuit 30; a plurality of branched paths each one end of which is connected to each of the power circuits and the other ends of which are joined and connected to the inspection input terminal; and resistances 26 provided on the respective branched paths before joining. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which a component is mounted on a substrate, and an inspection system for inspecting a connection state between the substrate and the component of the semiconductor device.

  As a method for mounting a semiconductor chip (component) on a mounting substrate (substrate), a flip chip method, a wire bonding method, or the like has been conventionally used. In the flip chip method, bumps and terminals are bonded, and in the wire bonding method, wires and terminals are connected. Although the connection mode is different, in any case, the mounting substrate and the semiconductor chip are electrically connected. At this time, if a connection failure occurs between the two, the portion is not electrically connected. Therefore, it is necessary to check the connection state. A technique for performing this inspection (wire bonding) is disclosed in Patent Document 1, for example.

  A semiconductor chip is mounted on a mounting substrate to constitute one package (semiconductor device). When the semiconductor chip is mounted, the connection portion between the mounting substrate and the semiconductor chip is completely enclosed in the package. For this reason, it is not possible to visually check the connection site from the outside, and it is not possible to perform a direct contact inspection.

  For this reason, an indirect inspection is performed from outside the package. The mounting substrate is formed with wirings or terminals that are electrically connected to the semiconductor chip and exposed to the outside, and the connection state is inspected indirectly using the wirings or terminals.

  4 and 5 show a conventional semiconductor device and its inspection system. The semiconductor device (package) 101 is configured by mounting a semiconductor chip 103 on a mounting substrate 102. The mounting substrate 102 and the semiconductor chip 103 are electrically connected, and a portion where this connection is performed is a connection region 104. The connection area 104 is completely enclosed by the package. In addition, an inspection apparatus 105 is connected to the mounting substrate 102.

  The mounting substrate 102 includes a first power input terminal 111, a second power input terminal 112, a signal input terminal 113, a plurality of substrate side first power terminals 114, a plurality of substrate side second power terminals 115, and a substrate side signal terminal 116. It has a general configuration. The first power input terminal 111 inputs a first power from the outside. The second power supply input terminal 112 inputs a second power supply (voltage lower than the first power supply) from the outside. The signal input terminal 113 inputs a predetermined signal from the outside.

  Each board-side first power supply terminal 114 serves as an output terminal that outputs the first power supplied from the first power supply input terminal 111 and distributed to the connection portions C1 to C4. Each board-side second power supply terminal 115 serves as an output terminal that outputs the second power supplied from the second power supply input terminal 112 and distributed to the connection portions C5 to C8. The board-side signal terminal 116 serves as an output terminal for outputting the signal input from the signal input terminal 113 to the connection portion C9. The connection region 104 is composed of C1 to C9, and electrically connects the mounting substrate 102 and the semiconductor chip 103.

  The semiconductor chip 103 includes a plurality of chip-side first power supply terminals 121, a plurality of second power supply input terminals 122, a chip-side signal terminal 123, an internal circuit 124, a first diode 125, and a second diode 126. Yes.

  Each chip side first power supply terminal 121 is connected to the connection portions C1 to C4. Each path connected to the chip-side first power supply terminal 121 is joined to one path L1. Each second power input terminal 122 is connected to the connection portions C5 to C8. Each path connected to the second power input terminal 122 is joined to one path L2. The chip-side signal terminal 123 is connected to the connection portion C9 and is connected to the path L3.

  The paths L1 to L3 are connected to the internal circuit 124. The internal circuit 124 is a circuit that operates by receiving power and signals. The first diode 125 connects the paths L3 and L1, and the second diode 126 connects the paths L2 and L3.

  4 includes a current source 131 and a voltmeter 132. The current source 131 and the voltmeter 132 each have one end connected to the first power input terminal 111 and the other end. Is connected to the signal input terminal 113. The current source 131 generates and outputs a predetermined current. The output current includes the signal input terminal 113, the substrate side signal terminal 116, the connection part C9, the chip side signal terminal 123, the path L3, the first diode 125, the path L1, the plurality of chip side first power supply terminals 121, and the connection part C1. Are input to the inspection apparatus 105 via the plurality of substrate side first power supply terminals 114 and the first power supply input terminal 111.

  The voltmeter 132 measures the voltage between the first power input terminal 111 and the signal input terminal 113, and inspects the connection state between the mounting substrate 102 and the semiconductor chip 103 based on the measured voltage.

  As shown in FIG. 4 and FIG. 5, it is divided into a part where the first power is transmitted and a part where the second power is transmitted across the line (signal input terminal 113 to path L3) where the signal is transmitted. Have the same configuration. That is, although the transmitted power is different, the mechanism for transmitting the power is the same. For this reason, in FIG. 4, inspection of the connection parts C1 to C4 that transmit the first power supply is performed, and in FIG.

  4 connects the signal input terminal 113, the first power input terminal 111, and the inspection device 105 in order to inspect the connecting portions C1 to C4 that transmit the first power, and FIG. 5 illustrates the second power source. The signal input terminal 113, the second power supply input terminal 112, and the inspection device 105 are connected to inspect the connection portions C5 to C8 that transmit the signal.

JP 2000-232141 A

  When the semiconductor chip 103 does not require a large power source, it is not necessary to distribute the power source on the mounting substrate 102. That is, the first power source (second power source) input from the first power source input terminal 111 (second power source input terminal 112) can be transmitted to the internal circuit 124 through a single path. However, since the recent semiconductor chip 103 requires a large power source, the power source must be distributed and transmitted. For this purpose, the power supply is divided into a plurality of paths by the mounting substrate 102 and joined by the semiconductor substrate 103 for use.

  When one power source is transmitted through a single path, the inspection device 105 can be used for simple inspection. That is, in the case of a single path, if a connection failure occurs in the connection region 104, the current output from the current source 131 does not flow and the voltage is not detected by the voltmeter 132. As a result, it is checked whether or not a connection failure has occurred. In other words, the connection failure is detected depending on whether or not the voltage is detected.

  However, as shown in FIGS. 4 and 5, when a plurality of paths (paths including connection parts C1 to C4 and C5 to C8) are used in order to distribute the power in order to increase the supply amount of power, Even if an abnormality occurs in one of the paths, since the current flows through the other path, the value of the voltage detected by the voltmeter 132 hardly changes. This is because there is almost no voltage drop in each path. Therefore, it is impossible to detect a connection failure in a part of the paths, regardless of the connection failure occurring in all of the plurality of paths. That is, it was impossible to accurately check the connection state.

  There is also an inspection method in which the inside of the package is visually recognized using ultrasonic waves or X-rays instead of the inspection device 105. However, since this inspection depends on the performance of the ultrasonic diagnostic apparatus or the X-ray apparatus and also depends on the ability of the inspector, the inspection result becomes uncertain. There are also inspection methods that are performed by opening the package, or inspection methods that are performed by polishing the cross section and visually recognizing the internal state. However, since these involve destruction of the package, they can no longer be used as products.

  Accordingly, an object of the present invention is to accurately inspect the connection state of a semiconductor device without causing destruction.

  In order to solve the above problems, a semiconductor device according to claim 1 of the present invention is configured by mounting a component on a substrate, and includes a power transmission unit that transmits power supplied from the outside to an internal circuit of the component. The power transmission unit is provided on the board, and is provided on the board with a power input terminal for inputting power supplied from the outside, between the board and the component. An inspection input terminal for inspecting a connection state, a plurality of power supply paths for distributing the power input from the power supply input terminal and transmitting it to the internal circuit, one end connected to each power supply path, and the other end joined And a plurality of branch paths connected to the inspection input terminal, and passive elements provided on the respective branch paths and before the branch paths merge.

  According to this semiconductor device, the passive element is provided in each branch path branched from each power supply path. Since the power input terminal and the inspection terminal are connected to the power supply path and the branch path, and the passive element is provided, the passive element can be detected using the power input terminal and the inspection terminal. Depending on the detection state of the passive element, it is possible to accurately detect that a connection failure has occurred in a part of the plurality of power supply paths without causing damage.

  A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the semiconductor device is provided in each of the power supply paths, and is provided between a position where the power supply path branches and a position where the power supply path joins. The switch means is provided.

  According to this semiconductor device, the power supply path is turned on and off by the switch means. By turning on the switch means, power is supplied to the internal circuit and the semiconductor device can be used normally. Further, by turning off the switch means, all the current flows toward the passive element without going to the internal circuit, so that the connection state can be inspected. Thereby, the normal use state and the inspection state can be switched.

  A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the second aspect, wherein the power transmission unit includes a first power transmission unit for transmitting a first power source and the first power source. A second power transmission unit for transmitting a second power supply having a voltage lower than the voltage, and the switch means of the first power transmission unit transmits the second power transmitted by the second power transmission unit. It is a PMOS transistor that switches on and off of the power supply path by inputting power, and the switch means of the second power transmission section inputs the first power transmitted by the first power transmission section and supplies the power supply path. It is an NMOS transistor that switches between ON and OFF.

  According to this semiconductor device, the switch means is a PMOS transistor or an NMOS transistor. And since each transistor inputs the power supply of the other power transmission part and switches on and off, the power supply path is automatically turned on and off based on the first power supply and the second power supply. It will be possible to switch.

  A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the first aspect, wherein the passive element is a resistor, and a combination of all combinations when one or more resistors are selected from a plurality of resistors. The resistance value of each resistor is determined so that all the resistors have different values.

  According to this semiconductor device, a resistor can be applied as a passive element. Since the combined resistance values are different for all the combinations of the plurality of resistors, it becomes possible to easily recognize which resistor has caused the connection failure from the detected combined resistance value.

  A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to the first aspect, wherein the passive element is a capacitor, and a combination of all combinations when one or more capacitors are selected from a plurality of capacitors. It is characterized in that the capacitance value of each capacitor is determined so that the capacitances are all different values.

  According to this semiconductor device, a capacitor can be applied as a passive element. Since the combined capacitance values are different for all of the combinations of the plurality of capacitors, it is possible to easily recognize which capacitor has a connection failure from the detected combined capacitance value.

  An inspection system according to a sixth aspect of the present invention is an inspection system including the semiconductor device according to any one of the first to fifth aspects, wherein the passive element is detected at the power input terminal and the inspection input terminal. The inspection device to be connected is connected.

  According to this inspection system, a connection state can be inspected by connecting an inspection device for detecting a passive element to a power input terminal and an inspection terminal provided in the semiconductor device.

  According to the present invention, by providing each passive element on a branch path branched from each power supply path to which the power input from the power input terminal is distributed, the connection state can be inspected based on detection of each passive element. become.

It is a block diagram which shows schematic structure of the semiconductor device of a test | inspection state. It is a block diagram which shows schematic structure of the semiconductor device of a normal use state. It is a block diagram which shows schematic structure of the semiconductor device in a modification. It is a block diagram which shows the aspect which test | inspects the conventional semiconductor device. It is a block diagram which shows the other aspect which test | inspects the conventional semiconductor device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a semiconductor device 1 of the present invention. The semiconductor device 1 is a semiconductor package configured by mounting a semiconductor chip 3 on a mounting substrate 2. The mounting substrate 2 is a substrate for mounting a semiconductor chip 3 as a component, and the mounting substrate 2 and the semiconductor chip 3 are electrically connected by a connection region 4. An inspection device 5 for inspecting an electrical connection state of the semiconductor device 1 as a package (semiconductor package) is connected to the semiconductor device 1.

  The mounting board 2 includes a first power input terminal 11, a second power input terminal 12, a signal input terminal 13, a plurality of board side first power terminals 14, a plurality of board side second power terminals 15, a board side signal terminal 16, and a first board. 1 inspection input terminal 17, 2nd inspection input terminal 18, board | substrate side 1st inspection terminal 19, and board | substrate side 2nd inspection terminal 20 are comprised roughly.

  The first power supply input terminal 11 inputs a first power supply from the outside, and the second power supply input terminal 12 inputs a second power supply. The signal input terminal 13 inputs a predetermined signal from the outside. The relationship between the first power supply VDD and the second power supply VSS is “VDD> VSS”. The second power supply VSS is not limited to a negative voltage, and may be a positive voltage or 0 volt. In short, the voltage may be lower than the first power supply VDD. In the following description, it is assumed that the first power supply VDD is High and the second power supply VSS is Low.

  The first power supply VDD input from the first power supply input terminal 11 is distributed to the plurality of substrate-side first power supply terminals 14, and the second power supply VSS input from the second power supply input terminal 12 is supplied to the plurality of substrate-side second power supply terminals 15. Distributed to. The first power supply VDD and the second power supply VSS are equally divided into the distributed number. Of course, the first power supply VDD and the second power supply VSS may be distributed in an arbitrary number. When the power is distributed to the four board-side power terminals as shown in FIG. 1, each power source is divided into four equal parts. The number of substrate side first power terminals 14 and the number of substrate side second power terminals 15 may be the same or different.

  Each board | substrate side 1st power supply terminal 14 is connected to the connection parts C1-C4, respectively, and outputs the 1st power supply VDD distributed via the connection parts C1-C4. Each board | substrate side 2nd power supply terminal 15 is connected to the connection parts C5-C8, respectively, and outputs the 2nd power supply VSS distributed via the connection parts C5-C8. The board-side signal terminal 16 outputs the signal input from the signal input terminal 13 to the connection portion C9.

  The first inspection input terminal 17 and the board side first inspection terminal 19 are terminals provided mainly for inspecting the connection state of the connection portions C1 to C4, and the two terminals are electrically connected. . And the board | substrate side 1st test | inspection terminal 19 is connected to the connection part C10. The second inspection input terminal 18 and the board-side second inspection terminal 20 are terminals provided mainly for inspecting the connection state of the connection portions C5 to C8, and the two terminals are electrically connected. . And the board | substrate side 2nd test | inspection terminal 20 is connected to the connection part C11.

  The connection region 4 electrically connects the mounting substrate 2 configured to include the connection portions C <b> 1 to C <b> 11 and the semiconductor chip 3. For example, wires and electrodes are provided in the connection region 4. After the semiconductor chip 3 is mounted on the mounting substrate 2, the connection region 4 is completely included in the semiconductor device 1 and cannot be visually recognized or directly contacted from the outside.

  The semiconductor chip 3 is a component (element) mounted on the mounting substrate 2, and includes a plurality of chip-side first power terminals 21, a plurality of chip-side second power terminals 22, a chip-side signal terminal 23, and a chip-side first inspection terminal. 24, a chip-side second inspection terminal 25, a plurality of first resistors 26, a plurality of first transistors 27, a plurality of second resistors 28, a plurality of second transistors 29, and an internal circuit 30. .

  Each chip-side first power supply terminal 21 is connected to the connection portions C1 to C4, and receives the first power supply VDD distributed through the connection portions C1 to C4. Each chip-side second power supply terminal 22 is connected to the connection portions C5 to C8, and receives the second power supply VSS distributed through the connection portions C5 to C8.

  As shown in FIG. 1, the first power supply VDD and the second power supply VSS are distributed into four, and one path is provided for each distributed power supply. The four paths of the first power supply VDD are referred to as first power supply paths L1 to L4, respectively, and the four paths of the second power supply VSS are respectively referred to as second power supply paths L5 to L8. Since the first power supply paths L1 to L4 are paths after the first power supply VDD is distributed, the first power supply paths L1 to L4 include connection portions C1 to C4. In addition, the second power supply paths L5 to L8 are paths after the second power supply VSS is distributed, and thus include the connecting portions C5 to C8.

  The chip-side signal terminal 23 is connected to the connection portion C9, and inputs a signal through the connection portion C9. One end of the signal path L <b> 9 is connected to the chip-side signal terminal 23 in the semiconductor chip 3, and the other end is connected to the internal circuit 30. The chip-side first inspection terminal 24 is connected to the connection portion C10, and the chip-side second inspection terminal 25 is connected to the connection portion C11.

  The first power supply paths L1 to L4 are branched into branch paths B1 to B4 on the way. A first resistor 26 is provided in each of the branch paths B1 to B4. The branch paths B <b> 1 to B <b> 4 are merged into one merge path L <b> 10 and connected to the chip-side first inspection terminal 24. Further, the second power supply paths L5 to L8 are branched into branch paths B5 to B8, and a second resistor 28 is provided in each of the branch paths B5 to B8. The branch paths B5 to B8 are merged to form one merge path L11 and connected to the chip-side second inspection terminal 25.

  The first power supply paths L1 to L4 are merged into one merge path L21, and the distributed first power supply VDD is restored. The second power supply paths L5 to L8 are merged into one merge path L22, and the distributed second power supply VSS is restored.

  A first transistor 27 is provided between each of the first power supply paths L1 to L4 that branches to the branch paths B1 to B4 and a position that joins the merge path L21. Similarly, the second transistors 29 are respectively provided between locations where the second power supply paths L5 to L8 branch to the branch paths B5 to B8 and locations where the junction paths L21 merge.

  Each first transistor 27 is a PMOS transistor, which turns on the first power supply path when the voltage applied to the gate is Low and turns it off when the voltage is High. Each second transistor 29 is an NMOS transistor, and turns on the second power supply path when the voltage applied to the gate is High and turns it off when the voltage is Low. For this reason, the first transistor 27 and the second transistor 29 function as switching means for switching the power supply path between on and off.

  Merge path L21, merge path L22, and signal path L9 are connected to internal circuit 30. The internal circuit 30 is a circuit that operates in response to input of a power supply and a signal, and a circuit for various purposes is applied. A first power supply VDD, a second power supply VSS, and a signal are input to the internal circuit 30 from the merging paths L21 and L22 and the signal path L9, respectively.

  Any one of the first power supply paths L <b> 1 to L <b> 4 (here, L <b> 4) is branched and input to the gate side of each second transistor 29. This branched path is referred to as a first switch control path L31. Similarly, one of the second power supply paths L5 to L8 (here, L5) is branched in the middle and input to the gate side of the first transistor 27. This branched path is defined as a second switch control path L32.

  The inspection device 5 includes a first inspection device 51 and a second inspection device 52. The first inspection device 51 includes a first current source 53 and a first voltmeter 54, and the second inspection device 52 includes a second current source 55 and a second voltmeter 56. Yes. The first inspection device 51 inspects the connection state of the connection portions C1 to C4, and the second inspection device 52 inspects the connection state of the connection portions C5 to C8. The first inspection device 51 and the second inspection device 52 are detachably connected to the mounting substrate 2.

  The first current source 53 generates and outputs a predetermined current, and the first voltmeter 54 measures the voltage between the first power input terminal 11 and the first inspection input terminal 17. The second current source 55 generates and outputs a predetermined current (which may be the same as or different from the current of the first current source 53), and the second voltmeter 56 is a second power source. The voltage between the input terminal 12 and the second inspection input terminal 18 is measured.

  FIG. 1 shows the state of the semiconductor device 1 when performing an inspection, and FIG. 2 shows the normal use state of the semiconductor device 1. The normal use state does not perform the above-described connection state inspection, but is a state in which the semiconductor device 1 is actually used. In the normal use state, the positive voltage side of the voltage source 71 that generates the predetermined voltage V <b> 1 is connected to the first power supply input terminal 11, and the negative voltage side is connected to the second power supply input terminal 12. That is, “V1 = VDD−VSS”.

  The signal generator 72 generates a signal to be input to the semiconductor chip 3. The signal is a predetermined pulse, and this pulse is given by the voltage V2. The signal generator 72 is connected to the signal input terminal 13, and a pulse (voltage V <b> 2) is applied to the signal input terminal 13, and a signal is input to the internal circuit 30.

  The semiconductor device 1 has a first power transmission for inputting the first power VDD to the internal circuit 30 across a signal transmission line (a path including the signal path L9 from the signal input terminal 13) for transmitting a signal of the voltage V2. The unit 61 and the second power source transmission unit 62 for inputting the second power source VSS to the internal circuit 30 are divided into two parts.

  The first power transmission unit 61 and the second power transmission unit 62 have the same configuration. In other words, the first and second power supply input terminals 11 and 12 and the first and second inspection input terminals 17 and 18 to each of the merging paths L21 and L22 are configured, and the configuration is almost the same. It is. Of course, a circuit configuration may be different by providing other circuits.

  Next, the operation will be described. First, the normal use state will be described. In this case, as shown in FIG. 2, a voltage source 71 is connected to the first power input terminal 11 and the second power input terminal 12, and a signal generator 72 is connected to the signal input terminal 13. . For this reason, the first power supply input terminal 11 receives the first power supply VDD, and the second power supply input terminal 12 receives the second power supply VSS. As shown in FIG. 2, nothing is connected to the first inspection input terminal 17 and the second inspection input terminal 18 in the normal use state.

  The first power VDD input from the first power input terminal 11 of the first power transmission unit 61 is distributed and transmitted to the first power paths L1 to L4 via the connection units C1 to C4. At this time, since the first inspection input terminal 17 is in an open state, no current or voltage is output to the branch paths B1 to B4. That is, each resistor 26 is not functioning. Therefore, all the first power supply VDDs of the first power supply paths L1 to L4 are directed to the first transistor 27.

  The second power transmission unit 62 operates in the same manner. At this time, the second power supply path L5 of the second power supply transmission unit 62 branches to the switch control path L32 and is input to the gate side of each first transistor 27 of the first power supply transmission unit 61. The voltage of the second power supply VSS that transmits the second power supply path L5 is Low. Therefore, the second power supply VSS which is Low is input to the gate side of each first transistor 27.

  The first transistor 27 is a PMOS transistor, and turns on the first power supply paths L1 to L4 when the voltage of the power supply input to the gate side is Low. Therefore, the first power supply VDDs of the first power supply paths L1 to L4 are merged by the merge path L21 and input to the internal circuit 30.

  The second transistor 29 is an NMOS transistor, and the power source input to the gate side is the first power source VDD (High). Therefore, the second power supply paths L5 to L8 are turned on. Then, the second power supply VSS is merged in the merge path L22 and input to the internal circuit 30.

  Next, the inspection state will be described. In this case, the connection mode shown in FIG. That is, the inspection device 5 is connected to the mounting substrate 2. The first current source 53 and the second current source 55 each output a predetermined current. The current output from the first current source 53 is input from the first power supply input terminal 11, distributed to the four board-side first power supply terminals 14, and output to the connection portions C <b> 1 to C <b> 4.

  The current output to the connection portions C1 to C4 is input from the chip-side first power supply terminal 21 and flows through the first power supply paths L1 to L4. Similarly, the current output from the second current source 55 is input from the chip-side second power supply terminal 22 and flows through the second power supply paths L5 to L8.

  Here, the voltage source 71 is not connected between the first power supply input terminal 11 and the second power supply input terminal 12, and therefore a predetermined voltage V1 is not applied between the two terminals. That is, the first power supply VDD and the second power supply VSS are not input to the semiconductor device 1. Therefore, a low voltage is not input to the gate side of the first transistor 27, and a high voltage is not input to the gate side of the second transistor 29. Accordingly, the first transistor 27 and the second transistor 29 turn off the first power supply paths L1 to L4 and the second power supply paths L5 to L8, respectively.

  For this reason, all the currents flowing through the first power supply paths L1 to L4 flow toward the branch paths B1 to B4. Similarly, all currents flowing through the second power supply paths L5 to L8 flow toward the branch paths B5 to B8. That is, current flows through the first resistor 26 and the second resistor 28.

  As described above, the first transistor 27 and the second transistor 29 function as switching means for switching the power supply path between on and off. The power transmitted from the other power transmission unit is input to the gate side of the transistor of one power transmission unit. Thus, the switch means can be automatically switched on / off depending on whether the switch is in the normal use state or the inspection state without providing a means for controlling the switching of a special switch.

  The currents that have flowed through the first resistors 26 of the branch paths B1 to B4 are merged to form a merge path L10, and are output to the first inspection input terminal 17 via the connection portion C10. The currents that have flowed through the second resistors 28 of the branch paths B5 to B8 are merged to form a merge path L11, and are output to the second inspection input terminal 18 via the connection portion C11.

  The current output from the first inspection device 51 passes through the first power supply input terminal 11, the first power supply paths L1 to L4, the branch paths B1 to B4, the merge path L10, the connection portion C10, and the first inspection input terminal 17. Thus, a return path that is returned to the first inspection device 51 is formed. The same applies to the current output from the second inspection device 52.

  A predetermined voltage drop is generated by the resistors 26 provided in the branch paths B1 to B4. As shown in FIG. 1, a first resistor 26 is provided in a path from the feedback path until it is distributed and merged. Therefore, when viewed from the first inspection device 51, the four first resistors 26 are in a parallel connection state. Since the first voltmeter 54 detects the voltage between the first inspection input terminal 17 and the first power supply input terminal 11 and recognizes the current output from the first current source 53 as known, this Thus, the combined resistance of the four first resistors 26 is detected.

Since the four first resistors 26 are connected in parallel, assuming that the resistance values of all the first resistors 26 are r1 and the resistance value of the combined resistor is R1, "R1 = ((1 / r1) × 4) ⁻¹ = r1 / 4 ”. Similarly, if the resistance value of the four second resistors 28 is r2, and the resistance value of the combined resistor is R2, “R2 = ((1 / r2) × 4) ⁻¹ = r2 / 4”.

  If connection failure does not occur in the first power supply paths L1 to L4 including the connection portions C1 to C4, the first inspection device 51 detects the resistance value “R1 = r1 / 4”. However, if a connection failure occurs in a part of the first power supply paths L1 to L4, no current flows through the part and no voltage drop occurs. For example, when a connection failure occurs in the first power supply path L1, no current flows through the first resistor 26 of the branch path B1, and the combined resistance value is detected as r1 / 3. Since this is not a value that should be detected inherently, it is recognized that a connection failure has occurred. The same applies to the second power supply paths L5 to L8.

  Therefore, a resistor is provided on each branch path obtained by branching a plurality of power supply paths, and the combined resistance value is detected. Therefore, when a connection failure occurs in any of the plurality of power supply paths, the semiconductor The connection state of the device 1 can be easily and clearly inspected. Moreover, since no ultrasonic waves, X-rays, or the like are used, an accurate inspection can be performed, and since there is no destruction, the inspected semiconductor device 1 can be used as a product. become.

  In the above description, the plurality of first resistors 26 are all assumed to have the same resistance value, but it is desirable that the resistance values of the first resistors 26 be different. This is because, if all the resistance values are the same, even if it can be recognized that a connection failure has occurred, it cannot be recognized which of the first resistors 26 has a connection failure. The same applies to the second resistor 28.

  At this time, as the resistance values of the plurality of first resistors 26, combinations of all the first resistors 26 that can be selected from each first resistor 26 (a combination including the case where all are selected from the case where one is selected). The resistance values of the first resistors 26 are determined so that the combined resistances are all different values. Thereby, it is easily recognized which of the plurality of first resistors 26 has caused the connection failure. The same applies to the second resistor 28. A more specific description will be given in a modification described later.

  As described above, the first power supply paths L1 to L4 are paths including the connection parts C1 to C4, and the second power supply paths L5 to L8 are paths including the connection parts C5 to C8. The inspection device 5 inspects the connection state of the first power supply paths L1 to L4 and the second power supply paths L5 to L8. In this regard, even when a connection failure occurs in the power supply path other than the connection portion, this is detected.

  In addition, the first transistor 27 uses the second power supply VSS and the second transistor 29 uses the first power supply VDD to perform switch switching control, thereby automatically performing the switching control. Play. However, any switching means other than the transistor can be provided as long as the power supply path can be switched on and off depending on whether it is in the normal use state or the inspection state.

  For example, a switching element that switches a simple power supply path between connection and disconnection is applied as a switch means, and the switching element is determined depending on whether or not the voltage source 71 is connected to the first power supply input terminal 11 and the second power supply input terminal 12. Means for switching may be provided.

  Further, the first inspection device 51 and the second inspection device 52 can inspect the connection state at the same time, or can inspect at different timings. In the example shown in FIG. 1, the first inspection device 51 and the second inspection device 52 are prepared and inspected at the same time. However, only one inspection device is prepared and the inspection is performed twice. The inspection can be performed separately.

  In FIG. 1, the first inspection device 51 and the second inspection device 52 detect the value of the combined resistance by measuring the voltage between the terminals using a current source and a voltmeter, respectively. (A voltage source different from the voltage source 71: a voltage source for inspection) and an ammeter may be used. When the inspection voltage source measures a predetermined voltage, a current flows through each first resistor 26 and each second resistor 28. Then, the combined resistance can be measured by measuring the current value using an ammeter. As a result, the connection state can be inspected.

  Next, a modified example will be described with reference to FIG. The configuration of this modification is almost the same as that of the above-described embodiment, but a first capacitor 81 is provided instead of the first resistor 26, and a second capacitor 82 is provided instead of the second resistor 28. The first inspection device 51 and the second inspection device 52 are provided with a first capacitance detection unit 83 and a second capacitance detection unit 84 instead of a current source and a voltmeter.

  That is, the connection state of the connection portions C1 to C4 and C5 to C8 is inspected by measuring the capacitance instead of the resistance. In this case, since it is not a resistor but a capacitance, the sum of the capacitance values (capacitance values) of the four capacitors is the combined capacitance. Although the respective capacitance values may be the same value, as described above, the combined capacities for all combinations of capacities selectable from the four first capacities 81 provided in the branch paths B1 to B5 are all different values. Thus, the capacitance value of each first capacitor 81 is determined.

  The capacitance value F of the combined capacitance detected by the capacitance detector 81 is “F = f1 + f2 + f3 + f4”, where the capacitances of the capacitors 81 are f1 to f4. At this time, for example, f1 = 1, f2 = 5, f3 = 10, and f4 = 20 (all units are farads). In this case, the combinations of selectable capacities (including the case where only one is selected) are 16 types in total. The combined capacity F of each combination is F = (0, 1, 5, 10, 20, 1 + 5 = 6, 1 + 10 = 11, 1 + 20 = 21, 5 + 10 = 15, 5 + 20 = 25, 10 + 20 = 30, 1 + 5 + 10 = 16, 1 + 5 + 20 = 26, 1 + 10 + 20 = 31, 5 + 10 + 20 = 35, 1 + 5 + 10 + 20 = 36).

  Therefore, when a connection failure occurs in any of the first capacitors 81 or the plurality of first capacitors 81, not only the connection failure occurs but also the defective first capacitor. Can be specified. The same applies to the second capacitor 82.

  As described above, in the embodiment, a connection failure is detected using a resistor, and in the modification, a connection failure is detected using a capacitor. Resistors and capacitors are passive elements in the circuit, and the present invention detects each passive element by providing each passive element in a branch path branched from the power supply path. Thereby, the connection failure between the board | substrate and component of a semiconductor device comes to be detected.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Mounting board 3 Semiconductor chip 4 Connection area 5 Inspection apparatus 11 1st power input terminal 12 2nd power input terminal 13 Signal input terminal 14 Substrate side 1st power terminal 15 Substrate side 2nd power terminal 16 Substrate side signal terminal 17 First inspection input terminal 18 Second inspection input terminal 19 Substrate side first inspection terminal 20 Substrate side second inspection terminal 21 Chip side first power supply terminal 22 Chip side second power supply terminal 23 Chip side signal terminal 24 Chip side first Inspection terminal 25 Chip side second inspection terminal 26 First resistor 27 First transistor 28 Second resistor 29 Second transistor 30 Internal circuit 61 First power transmission unit 62 Second power transmission unit 81 First capacitor 82 Second capacitor

Claims (6)

A semiconductor device comprising a power supply transmission unit configured by mounting a component on a substrate and transmitting power supplied from the outside to an internal circuit of the component,
The power transmission unit is
A power input terminal provided on the substrate for inputting power supplied from outside;
An inspection input terminal provided on the substrate for inspecting a connection state between the substrate and the component;
A plurality of power supply paths for distributing the power input from the power input terminal and transmitting the power to the internal circuit;
A plurality of branch paths, one end of which is connected to each power supply path, the other end is joined and connected to the inspection input terminal,
A passive element provided on each branch path and before each branch path merges;
A semiconductor device comprising: 2. The semiconductor device according to claim 1, further comprising switch means provided in each of the power supply paths and provided between a location where the power supply route branches and a location where the power supply route joins. The power transmission unit includes a first power transmission unit for transmitting a first power source, and a second power transmission unit for transmitting a second power source having a voltage lower than the voltage of the first power source. Have
The switch means of the first power transmission unit is a PMOS transistor that inputs a second power transmitted by the second power transmission unit and switches a power supply path on and off,
3. The switch means of the second power transmission unit is an NMOS transistor that inputs a first power transmitted by the first power transmission unit and switches a power supply path on and off. The semiconductor device described. The passive element is a resistor;
2. The semiconductor device according to claim 1, wherein the resistance values of the resistors are determined so that the combined resistances for all combinations when one or more resistors are selected from the plurality of resistors are different from each other. The passive element is a capacitor;
2. The semiconductor device according to claim 1, wherein the capacitance value of each capacitor is determined such that the combined capacitances for all combinations when one or more capacitors are selected from the plurality of capacitors have different values. An inspection system comprising the semiconductor device according to any one of claims 1 to 5,
An inspection system for detecting the passive element is connected to the power input terminal and the inspection input terminal.

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