JP5780498B2 - Inspection method and inspection apparatus for CMOS logic IC package - Google Patents

Description

The present invention relates to an inspection method and an inspection apparatus of a CMOS logic IC package having an inspection electrode, more specifically, CMOS having the inspection electrode and the buffer gate in the package (Complementary Metal Oxide Semiconductor) logic IC package and IC The present invention relates to an inspection method and an inspection apparatus for an open failure (including a disconnection failure and a semi-disconnection failure) between a connection electrode pad in a package and an electrode land (mounting portion) of a printed wiring board.

  Conventionally, a test using a power supply current (IDDQ test) has been performed as a method for facilitating the test of a CMOS integrated circuit. In this test, the power supply current of the CMOS integrated circuit is measured, and the quality of the test target CMOS integrated circuit is determined based on the measured value. In a normal CMOS integrated circuit, only a very small leakage current flows in a stable state where input / output data is fixed. Therefore, an open fault can be detected by a change in the power supply current even if it is a minor defect.

  The inventors have performed a circuit test in which a power supply current of a circuit flowing through the logic element is measured in a state where an AC electric field is supplied to the circuit including the logic element, and the presence or absence of a circuit failure is determined based on the power supply current. A method was proposed (Non-Patent Document 1). This test method is detected by turning on / off the gate capacitance of a transistor whose gate signal input line is disconnected by propagating an alternating electric field in an electronic device including a circuit having an open circuit. The quality of the electronic device is determined by measuring the power supply current component. Patent Documents 1 and 2 are patent gazettes related to some of the authors of Non-Patent Document 1.

Japanese Patent No. 3657834 Japanese Patent No. 3696507

Masao Takagi, Masaki Hashizume, Masahiro Ichinomiya, Hiroyuki Yoyanagi, “Applied AC Voltage for Detecting Lead Lift in CMOS LSIs by Current Test when AC Electric Field is Applied” Journal of Japan Institute of Electronics Packaging Vol.10 No.3 (2007) P219 ~ 228

With the recent miniaturization of electronic devices, it has become difficult to detect failures that occur in the manufacturing process of logic circuits mounted on printed wiring boards. There are mainly short-circuit faults and open faults as faults that occur in the manufacturing process, and the present invention aims to detect open faults. Here, the open fault for the purpose of detection by the present invention includes not only a disconnection fault but also a half-open type open fault caused by a soldering failure or the like.
Examples of the inspection method for open faults include an inspection method based on logical value measurement, an inspection method based on image processing, and an electrical inspection method. However, it is difficult to reliably detect open faults by the inspection method based on logical value measurement, and in particular, it is impossible to detect semi-open type open faults. Also, in the inspection by image processing, there are cases where it seems that the external connection is properly connected, but it is not electrically connected correctly. It is not possible to detect an open fault at a position where it cannot. Therefore, in the present invention, an open fault is detected by an electrical inspection.

According to the test method described in Non-Patent Document 1, it is possible to reliably detect a lead lift that is an open failure between a lead of an IC package and a land of a printed wiring board. However, this test method has a problem that the value of the induced voltage does not reach a threshold value (for example, 1.4 volts) unless a large AC voltage of several tens to hundreds of volts is applied to the external electrode. That is, since it is necessary to apply an inspection signal with a large voltage, there is a risk that when the external electrode comes into contact with another circuit element at the time of inspection, a normal IC is broken or the whole substrate is broken.
An object of the present invention is to make it possible to detect an open fault without applying a test signal having a large voltage.

In the BGA (Ball Grid Array) package, ball-shaped terminals (bumps) are soldered to electrode lands attached to a printed wiring board, but the soldered part is hidden under the chip. It is difficult to confirm and an alternating electric field cannot be applied from the external electrode. As far as the inventor is aware, there has been no electrical inspection method capable of quickly and easily confirming whether the ball-shaped terminal is normally soldered.
Similarly, there has been no electrical inspection method capable of quickly and easily confirming whether the signal connection between each IC chip in the package in SiP (System in Package) is normally soldered.
An object of the present invention is to make it possible to electrically detect open faults (including disconnection faults and half disconnection faults) in BGA packages and SiPs.

An object of the present invention is to provide an inspection method and an inspection apparatus for a CMOS logic IC package having an inspection electrode, which can solve the above-described problems.

  The present invention provides technical means for confirming proper connection when a CMOS logic IC package is soldered. That is, the present invention is constituted by the following technical means.

[1] A CMOS logic IC package including a test electrode and a buffer gate provided at positions close to each connection electrode pad in the package is provided, and the test electrode of the CMOS logic IC package mounted on a printed wiring board CMOS logic IC package that inspects a half-break failure between a connection electrode pad in a package and an electrode land of a printed wiring board by measuring a power supply current when an inspection signal having a waveform with a steep rise in low voltage is applied to Inspection method. Here, the waveform having a steep rise means, for example, a waveform whose angle between the rise and the horizontal line is 70 degrees or more (preferably 80 degrees or more), and may be alternating current or direct current.

[2] The CMOS logic IC package inspection method of [1], wherein the inspection signal is substantially a rectangular wave.
[3] A CMOS logic IC package including a test electrode and a buffer gate provided at positions close to each connection electrode pad in the package is provided, and the test electrode of the CMOS logic IC package mounted on a printed wiring board By measuring the power supply current when a low-voltage inspection signal is applied to the capacitor, an open failure between the connection electrode pad in the package and the electrode land of the printed wiring board and an open failure between the FC (Flip Chip) in the SiP Inspection method of CMOS logic IC package to be inspected.
Here, for example, the voltage of the inspection signal is preferably 10 volts or less, more preferably several volts or less in peak value. Incidentally, in the case of the power supply voltage 3.3 [V], for example, the pp value is 4.6 [V] and the peak value is 2.3 [V]. If the power supply voltage is [5V], the peak value is about 3.5 [V]. The capacitance changes depending on the distance and area between the connection electrode pad and the inspection electrode, and the applied voltage also changes.
[4] The CMOS logic IC package inspection method according to [3], wherein the inspection signal is an AC signal having a constant frequency, a DC pulsating voltage, or a rectangular voltage.

[5] A CMOS logic IC package having an IC chip wire-bonded in the package, a connection electrode pad and a buffer gate, and a printed wiring board connection terminal electrically connected to the connection electrode pad. A CMOS logic IC package comprising a test electrode for applying a test signal provided at a position close to each connection electrode pad in the package.
[6] A CMOS logic IC package having an IC chip flip-chip bonded in the package and a buffer gate, and a printed wiring board connection terminal electrically connected to a connection electrode made of TSV, which is inspected A CMOS logic IC package characterized in that a test electrode for applying a signal is configured by electrically connecting a part of TSV.
[7] The CMOS logic IC package according to [5] or [6], wherein the printed wiring board connection terminal is a BGA.

According to the present invention, it is possible to greatly reduce the inspection man-hour relating to the open failure, and consequently to significantly reduce the mounting cost of the CMOS logic IC package.
In addition, since a low voltage signal may be applied to the inspection electrode, there is no risk of damage to a normal IC or the entire substrate due to the inspection.
Furthermore, it is also possible to detect an open failure (including a disconnection failure and a half disconnection failure) in a BGA package or SiP, which has not conventionally been effective detection means.

It is explanatory drawing of the direct current | flow characteristic of a buffer gate. It is explanatory drawing of the principle of lead floating detection. It is a schematic diagram of an open failure due to QFP lead floating or BGA soldering failure. This is an equivalent circuit when an AC signal for inspection is applied when a protective diode is included in the fault circuit. It is a graph which shows the relationship between induced v _F (t) and power supply current I _DD (t) It is a block diagram of the lead float inspection apparatus by the conventional power supply current test method. It is a figure which shows the mounting aspect of a CMOS logic IC package. It is a figure which shows the example of 1 structure of the CMOS logic IC package based on this invention. FIG. 9 is a side view of the CMOS logic IC package of FIG. 8. It is a graph (1) and (2) which show the power supply current waveform and inspection signal waveform of a failure circuit concerning Example 1. It is a graph (3) and (4) which show the power supply current waveform and inspection signal waveform of the failure circuit concerning Example 1. It is a graph (5) (6) which shows the power supply current waveform and inspection signal waveform of the failure circuit which concerns on Example 1. FIG. It is a graph (7) and (8) which show the power supply current waveform and inspection signal waveform of the normal circuit concerning Example 1. FIG. 4 is an equivalent circuit when a rectangular wave signal for inspection is applied when the failure is a half-broken failure. It is a wiring diagram of the input part of the experimental circuit performed in order to test | inspect the half-broken fault which concerns on Example 2. FIG. It is a graph (1) which shows the power supply current waveform and inspection signal waveform of a normal circuit and a failure circuit concerning Example 2.

1. DC Characteristics of Buffer Circuit FIG. 1 shows input / output voltage static characteristics of a CMOS buffer gate. From FIG. 1 (b), it can be seen that if V _i is V _DD or GND, no power supply current flows through the buffer gate. If V _i is V _DD , V _out is V _DD , and if V _i is GND, V _out is GND. That is, the output signal line of the buffer gate is connected to the V _DD line or the GND line. If an open failure has not occurred in the input signal line of the CMOS buffer gate, the static power supply current will not flow.
When an open failure occurs in the input signal line of the CMOS buffer gate, the failure input signal line is not connected to either the V _DD line or the GND line, so that the potential of the failure input signal line becomes indefinite. Therefore, it cannot be predicted whether the logical value of the failure input signal line is 0 or 1. That is why it is difficult to detect open faults in the inspection method based on logical value measurement. Even if an inspection method by measuring the power supply current of a circuit is used, the failure input line does not always take the potential at which both the pMOS and nMOS connected to the failure input signal line are ON. However, the power supply current does not flow, and there is a possibility of overlooking the failure. In any case, the instability of the potential of the failure input signal line is a cause of missing an open failure.
In the inspection method, an AC electric field E (t) is applied from the outside of the circuit to be inspected, and is controlled from the outside of the circuit so that the potential of the failure input signal line does not become unstable. Then, both the nMOS and pMOS connected to the failure input lead are turned on, and the power supply current flowing thereby is measured to detect an open failure. FIG. 2B shows an equivalent circuit when an open failure (lead floating) occurs in the input lead of the buffer gate of FIG. 2A and an AC electric field E (t) is applied from the outside of the circuit. An induced voltage v _F (t) is generated by an alternating electric field E (t) generated by applying v _E (t) between the electrodes, and the gate voltages of the nMOS and pMOS in the buffer gate change with time. If the induced voltage v _F (t) is within a voltage range where both the nMOS and the pMOS in the buffer gate are turned on, the power supply current flows through the nMOS and the pMOS. Then, the potential of the failure input lead changes with time. The range is V _i1 ≦ Vi ≦ V _{i2 in} the case of the buffer gate having the DC characteristic shown in FIG.

2. Detection of open failure due to poor soldering between IC package terminals and printed circuit board lands with test electrodes for application of AC voltage inside When the test AC signal is applied, signal electrode pads in the IC chip In the meantime, the induced voltage v _F (t) of FIG. 5 is induced. When v _F (t) is V _i1 ≦ v _F (t) ≦ V _i2 , an abnormal power supply current I _DD (t) that is a through current flows. Here, the reason why the lower side of v _F (t) is missing is because a protective diode is included as shown in FIG. 4 (although omitted in FIG. 2). In this case, due to the effect of D2, the voltage drop of the diode is V _di and not lower than −V _di .

5 (a) is one in which v peak value V _a1 of _F (t) showed v waveform _F power supply current I _DD flowing through (t) (t) where V _i2 smaller. v _F (t) is When it is smaller than V _{i1, the} pMOS is ON, but the power supply current does not flow because the nMOS is OFF. v _F (t) is When V _i1 ≦ v _F (t), the nMOS is turned on and a current flows, and the power supply current I _DD (t) becomes the maximum at the threshold value of v _F (t). When v _F (t) exceeds the threshold value, the current flowing through the pMOS decreases and becomes the minimum at the peak of v _F (t). When v _F (t) decreases, the current flowing through the pMOS increases and reaches the maximum again at the threshold. When v _F (t) decreases and v _F (t) <V _i1 , the nMOS is turned off and the power supply current does not flow.

5 (b) is intended to peak value V _a2 of v _F (t) showed v waveform _F power supply current I _DD flowing through (t) (t) of greater than V _i2. v _F (t) is When V _i2 <v _F (t), the pMOS is turned off, so the power supply current does not flow once. When v _F (t) falls and v _F (t) ≤ V _i2 , the pMOS is turned on. The power supply current I _DD (t) flows again and becomes the maximum at the threshold value. When v _F (t) <V _i1 , the nMOS is turned off and the power supply current _stops flowing.

3. Outline of Inspection Method Non-Patent Document 1 discloses that a lead float is inspected by an inspection apparatus shown in FIG. In this experiment, the external electrode placed on the lead to be inspected is a square metal block made of 10 mm in thickness with a square bottom of 50 mm on the bottom, and placed in contact with the package resin. The thickness is 12 mm below the printed wiring board. An external electrode covered with 85 μm thick vinyl is arranged on a brass metal plate.
The basic configuration of the inspection apparatus of the present invention is the same as that shown in FIG. However, in the present invention, it is not necessary to dispose external electrodes above and below the printed wiring board. This is because, in the present invention, instead of the external electrodes arranged above and below the printed wiring board, an IC in which an inspection electrode for applying an alternating voltage is provided is used. By using such an IC, the present invention makes it possible to detect an abnormal power supply current even when the applied AC voltage is a low voltage (for example, about 0.7 times the power supply voltage of the IC). That is, in the present invention, if an alternating voltage of a low voltage of several volts or less is applied, an induced voltage exceeding the threshold can be induced when an open circuit failure occurs, and an abnormal power supply current can be detected. it can.

  The magnitude of the AC voltage to be applied depends on the magnitude of the capacitance (capacitor) constituted by the AC voltage application inspection electrode and the open-circuit failure signal line connection electrode pad provided inside the IC. The capacitance is inversely proportional to the distance between the inspection electrode and the connection electrode pad, and is proportional to the area of the electrode. Therefore, it is preferable to adjust the voltage of the inspection signal to an optimum value before starting the inspection. In the experiment, it was confirmed that an abnormal power supply current began to flow at a voltage lower than the power supply voltage of the IC, and that a detectable power supply current flowed at a voltage about 0.7 times the power supply voltage (see Example 1 described later).

4). Inspection Object A CMOS logic IC package to be inspected by the present invention will be described.
In the present invention, a CMOS logic IC package, for example, a QFP (Quad Flat Package), BGA, SiP (System in Package) package, or the like is an inspection target. A receiver buffer circuit is provided at the input portion of an FPGA or CPLD (Complex Programmable Logic Device) of these packages. In the present invention, a test electrode for applying an AC signal is provided at a position close to the input signal line and its connection electrode pad in the IC chip, and an AC voltage or a rectangular wave voltage is applied to the test electrode to receive a buffer for the receiver. An open circuit failure is determined by detecting an abnormal power supply current flowing in the gate circuit.

Hereinafter, a specific example will be described.
SiP (System in Package) is a common name for a package containing a plurality of chips, and it seems that many manufacturers use MCP when incorporating only the same type of chip, and SiP when incorporating different types of chips. . There are a plane type in which a plurality of chips are arranged on the same plane and a stack type in which the chips are stacked. As a mounting mode of a plurality of terminals extending (protruding) outward from the chip body, insertion mounting for inserting a pin into a through hole, lead (QFP) or solder bump (BGA) is installed on a land (connection terminal). There is surface mounting. FIG. 7 (1) shows an example of mounting in QFP, and (2) shows an example of mounting by BGA.

  In the case of an IC package having a plurality of leads, all signal input lines (lines electrically connecting connection electrode pads to lands) are provided in close proximity to the interior of the package body. The inspection electrode is preferably disposed immediately above or directly below the connection electrode pad. However, the position may be slightly shifted as long as an AC electric field can be applied. On the other hand, in order to keep the applied AC voltage or rectangular wave voltage low, an inspection electrode is provided as close as possible to the signal input line.

8 and 9 show a configuration example of the CMOS logic IC package according to the present invention. This IC package includes inspection electrodes 3 that overlap all signal input lines at close positions (cross in the horizontal direction). In FIG. 8, the rectangular inspection electrode 3 provided along the outer edge of the IC chip 1 is disclosed, but the inspection electrode shape is not limited to this, and may be a plate shape or an annular shape. When a conductive shield plate is built in the package, it can be used as a substitute for the inspection electrode, and connected to GND (ground) after inspection to be used as a shield.
When the IC chips are hierarchized, it is necessary to provide inspection electrodes 3 corresponding to the respective chips. As shown in FIG. 9, the inspection electrode 3 is provided so as to be laminated via the signal line connecting electrode pad 4 and the die pad 2 which is an insulating material. Although the connection terminals are not shown in FIG. 9, the package substrate 5 is provided with leads or bumps and mounted on the printed wiring board. Usually, each member on the package substrate 5 is sealed with resin.

  A BGA (Ball Grid Array) has ball-shaped terminals (solder bumps) provided in a grid pattern on the bottom of the package. Compared to QFP, it is a technology that can provide a larger number of terminals and can reduce the mounting area because leads do not protrude around the periphery. The IC package of the present invention includes inspection electrodes in the proximity of the signal input lines (lines electrically connecting the connection electrode pads to the lands) and inside the package body. The inspection electrode is disposed in the sealing resin, in the IC chip, or in the die pad. As the inspection electrode in the die pad, for example, a via described later can be used.

TSV (Through Silicon Via) connection is a technique for three-dimensional mounting in which a plurality of IC chips are stacked by through electrodes (TSV) formed through a silicon substrate, and is achieved by connecting the chips at the shortest distance. Functions and high-speed operation can be realized. For example, a through-hole of several tens of μmφ is opened on a silicon substrate, copper is filled in the through-hole as a conductive material, and when stacking chips, bumps are formed to connect the lower chip to the upper chip. By connecting them, vertical stacking is possible without using wires.
The number of TSVs is generally provided redundantly, and 100 × 100 or more may be provided on one chip. In the present invention, paying attention to the fact that there are a large number of unused TSVs, a plurality of TSVs adjacent to or close to the TSVs used for signal connection are electrically connected to form an inspection electrode. That is, adjacent or adjacent through electrodes are connected in a broad sense to form an inspection electrode. After the inspection, it is desirable to connect the inspection electrode to GND (ground) so as not to be affected by noise or to deteriorate the transmission characteristics.

The present invention described above has the following features.
In the present invention, when there is even one open failure in the circuit, it is assumed that the IC chip is determined to be defective. Therefore, it is not necessary to specify a signal line in which an open failure has occurred. In other words, the inspection method of the present invention is based on the premise that a single product and a multiple failure are not distinguished and determined as defective.

In the inspection method of the present invention, it is not necessary to change the frequency of the inspection signal. Experiments have shown that it is easier to detect abnormal power supply current when the induced voltage changes around the threshold over time. In addition, if the frequency is increased and the time for changing from the Low level to the High level (or from the High level to the Low level) is accelerated, the value near the threshold value is shortened, and the time for the abnormal power supply current to flow is shortened. Was able to be confirmed to be difficult. From this, a preferable frequency range is exemplified by several kHz to several tens of kHz.
The electrical signal for inspection applied to the inspection electrode may be a direct current signal such as half-wave rectification instead of an alternating current signal. That is, any signal can be used as long as it can induce a signal that changes from the Low level to the High level beyond the threshold (or from the High level to the Low level beyond the threshold).
In addition, when detecting a half-broken fault, a waveform (preferably a rectangular wave) with a steep rise is input instead of a sine wave. FIG. 14 shows an equivalent circuit in the case where there is a half-break in the circuit containing the protection diode. Since the inspection input unit including a half-break fault when a rectangular wave is applied to the inspection electrode can be regarded as a differentiating circuit, the rectangular wave is input to the inspection electrical signal, and the threshold value is changed to the high level by exceeding the threshold value. A signal that subsequently changes from a high level to a low level beyond a threshold value can be induced.

  Hereinafter, details of the present invention will be described with reference to examples, but the scope of the present invention is not limited to the examples.

  In a sample (VDEC-PC492-BU7084-AA) provided with an inspection electrode, an abnormal signal with a 33 pin lead floating is used to apply an inspection signal with a frequency of 1 kHz to the inspection electrode to generate an AC electric field, It was measured. The power supply voltage is 3.3 [V]. The configuration of the inspection apparatus is the same as that of FIG. 6 except that the inspection electrodes 11 and 12 are not provided. 10 to 12 show measurement results with an oscilloscope in the fault circuit. In each figure, Ch2 is a power supply current and Ch3 is an inspection signal.

(1) shown in FIG. 10 shows no pulsation in the power supply current when the voltage of the inspection signal is 61.87 mV in pp (peak to peak) value. (2) is a case where the voltage of the inspection signal is 2.019 V in the pp value, and shows a place where the power supply current starts to flow.
(3) shown in FIG. 11 is the case where the voltage of the inspection signal is pp value 4.288V, and (4) is the case where the voltage of the inspection signal is pp value 4.393V. A pulsation of the power supply current in synchronization with is observed.
(5) shown in FIG. 12 is the case where the voltage of the inspection signal is 4.517 V in terms of pp value, and (6) is the case where the voltage of the inspection signal is 4.777 V in terms of pp value. The pulsation of the power source current (measured in the AC range) synchronized with is observed, but the peak of the pulsation waveform is depressed. As can be seen from FIG. 2, this is because the through power supply current becomes maximum when the input voltage of the CMOS gate is Vth. That is, when the input voltage exceeds the threshold value, the through power supply current decreases and becomes the minimum in the peak of the inspection signal, and when the inspection signal voltage decreases, the through power supply current increases and becomes maximum when the input voltage of the CMOS gate becomes Vth. . When the input voltage further decreases, the through power supply current decreases, and when Vi1 is reached, the through power supply current does not flow. Since the voltage of the inspection signal must be such that the voltage induced by the input signal causing the open failure exceeds the threshold value, it is necessary to set an optimum input voltage for each inspection sample.

  (7) and (8) shown in FIG. 13 are results obtained by applying a test signal having a frequency of 1 kHz to the test electrode of the normal circuit (lead 33 = GND) and measuring the power supply current. Ch2 is a power supply current (measured in a DC range), and it is observed that a static power supply current flows but an abnormal power supply current does not flow.

  As described above, according to this example, it was confirmed that an abnormal power supply current can be detected by applying an inspection signal of about 4 V to a sample provided with an inspection electrode.

In a sample (EPM7064AETC100-10) provided with an inspection electrode, an AC electric field was generated by applying a rectangular wave inspection signal to the inspection electrode using a fault circuit with pin 71 as a0, and the power supply current was measured. The power supply voltage is 3.3 [V].
Since the inspection electrode cannot be provided in the IC, the NC terminal (unconnected terminal) next to the terminal into which the half-breakage failure was inserted was used as the inspection electrode (see FIG. 15). A half-break failure was created by connecting a resistor between a properly soldered input terminal and ground. The resistance value of the variable resistor at the time of inspection was 200 ohms. Capacitance between the NC terminal signal line and the two signals inserted with a half-break fault is unknown. Since the time constant of the differential pulse is small only by the capacitance between the signals, a 0.01 μF titacon (ceramic capacitor) was connected in parallel. Therefore, C is a value obtained by adding 0.01 μF to the capacitance between signals.

FIG. 16A shows a measurement waveform of a normal circuit. The range of the current probe is 5 A / V, and the current waveform of Ch2 is measured by DC. When a rectangular wave inspection signal with a voltage of pp (peak-to-peak) of 3.627 V is applied, the power supply current flows through the static power supply current I _DDQ of about 15 mA, and the abnormal power supply current I _DD (t) flows. There wasn't.
FIG. 16 (2) shows a measurement waveform of the fault circuit measured under the same conditions as in (1). When a rectangular wave inspection signal having a pp (peak to peak) voltage of 3.642 V is applied, the static power supply current I _DDQ flows about 15 mA, and the abnormal power supply current I _DD (t) reaches a peak of about 4 mA. It was confirmed that it was flowing.

In Example 2, when the amplitude of the input rectangular wave was increased and the differential waveform was set to exceed the threshold, it was confirmed that an abnormal power supply current I _DD (t) flows. Thereby, it turned out that the detection of a half-broken fault is possible by the power supply current test which concerns on Example 2. FIG. In addition, when an experiment was performed by changing the resistance value of the variable resistor, it was confirmed that it was possible to detect a half-break failure in the order of at least 10 ohms.

  Moreover, according to the method of the present embodiment, the inspection time can be greatly shortened. For example, when semi-judgment line detection is performed using the TDR inspection method (Pulse reflection type cable length measurement / diagnostic device (Time Domain Reflectometer)), it is difficult to detect and it is necessary to check one terminal at a time. It takes. In this regard, according to the inspection method of the present embodiment, detection is easy, and at the moment when the inspection signal is input, failure inspection of almost all terminals can be performed, so that the inspection time is greatly shortened. When the so-called screening test is performed by the test method of this embodiment and the IC repels as a defective product and it is necessary to know which terminal is an open failure, an additional test may be performed by the TDR test method.

1 IC chip 2 Die pad 3 Inspection electrode 4 Connection electrode pad 5 Package substrate 6 Inspection lead wire (or bonding wire)
7 Lead wire for connection (or bonding wire)
11,12 Inspection electrode

Claims (6)

In a CMOS logic IC package inspection method using a power supply current test method,
A plurality of electrode pads for connection provided in the package, and the inspection electrode provided at a position close to all of the connection electrode pads, CMOS logic IC package and a buffer gate, the inspection signal source, and, Providing a printed wiring board on which the CMOS logic IC package is mounted ;
Electrically connecting all of the inspection electrodes to an inspection signal source;
By measuring the power supply current when an inspection signal having a waveform of substantially rectangular wave at 10 volts or less is applied to the inspection electrodes of the CMOS logic IC package mounted on the printed wiring board, all the connection electrodes A method for inspecting a CMOS logic IC package for collectively inspecting a half-break failure between a pad and an electrode land of a printed wiring board. 2. The CMOS logic IC package inspection method according to claim 1, wherein the CMOS logic IC package is a BGA package . The CMOS logic IC package includes a TSV used for signal connection and a number of unused TSVs adjacent to or close to the TSV used for signal connection;
  3. The CMOS logic IC package according to claim 1, wherein the inspection electrode is configured by electrically connecting a number of unused TSVs adjacent to or close to the TSV used for the signal connection. Inspection method. In an inspection method for detecting an open failure of a CMOS logic IC package which is a SiP (System in Package) having FC (Flip Chip) inside by a power supply current test method,
A plurality of connecting electrodes Bad provided within the package, and the inspection electrode provided at a position close to all of the connection electrode pads, CMOS logic IC package and a buffer gate, the inspection signal source, and, Providing a printed wiring board on which the CMOS logic IC package is mounted ;
Electrically connecting all of the inspection electrodes to an inspection signal source;
By measuring the power supply current at the time of applying a test signal of substantially waveform is a square wave at 10 volts or less to the inspection electrode, the opening between the all connection electrode pad and the printed circuit board electrode lands A method for inspecting a CMOS logic IC package for collectively inspecting failures and open failures between FCs in a SiP. 5. The method of inspecting a CMOS logic IC package according to claim 4 , wherein the inspection signal is an AC signal having a constant frequency or a rectangular voltage. In an inspection apparatus that includes an inspection signal source and a waveform signal analysis apparatus, and detects an open failure of a CMOS logic IC package mounted on a printed wiring board by a power supply current test method.
The CMOS logic IC package includes a wire-bonded IC chip provided in the package, a connection electrode pad and a buffer gate, a printed wiring board connection terminal electrically connected to the connection electrode pad, and a package and a test electrode for applying a test signal in a position adjacent to the interconnecting electrode pads,
Electrically connecting all of the inspection electrodes to an inspection signal source;
By measuring the power supply current when a waveform inspection signal having a waveform of substantially rectangular wave at 10 volts or less is applied to the inspection electrode, a waveform signal analyzer measures all of the connection electrode pads and the printed wiring board. Inspection device for CMOS logic IC package that can collectively check for a half-break failure between electrode lands .