JPH11121683A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH11121683A
JPH11121683A JP9275741A JP27574197A JPH11121683A JP H11121683 A JPH11121683 A JP H11121683A JP 9275741 A JP9275741 A JP 9275741A JP 27574197 A JP27574197 A JP 27574197A JP H11121683 A JPH11121683 A JP H11121683A
Authority
JP
Japan
Prior art keywords
bonding wire
power transistor
integrated circuit
semiconductor integrated
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9275741A
Other languages
Japanese (ja)
Inventor
Shigeyuki Kiyota
茂之 清田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissan Motor Co Ltd
Original Assignee
Nissan Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissan Motor Co Ltd filed Critical Nissan Motor Co Ltd
Priority to JP9275741A priority Critical patent/JPH11121683A/en
Publication of JPH11121683A publication Critical patent/JPH11121683A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit of power transistors having overcurrent detector circuit which do not require provisions for separating shunt resistance for detecting the overcurrent, thereby suppressing the resistance increase of a main current line. SOLUTION: Bonding wires 317 which are always necessary for mounting a semiconductor chip 302 are used as detecting resistances of overcurrent detector circuits. There is no need for inserting new shunt resistances in series in a main current line, hence avoids increasing the on-resistance of the entire semiconductor integrated circuit is avoided, resolves the problem of requiring a complicated manufacturing process, and reduces the integrated circuit area just by the portion of the area for the shunt resistances.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、外部負荷を駆動す
るパワートランジスタに過電流検知回路を備えた半導体
集積回路に関する。
The present invention relates to a semiconductor integrated circuit having an overcurrent detection circuit in a power transistor for driving an external load.

【0002】[0002]

【従来の技術】従来の外部負荷を駆動するパワートラン
ジスタに過電流検知回路を備えた半導体集積回路として
は、例えば特開平7−77546号公報に記載されたも
のがある。上記の従来装置においては、外部負荷とパワ
ートランジスタと電源とを経由する主電流路の途中にシ
ャント抵抗を挿入し、比較回路を用いて該シャント抵抗
の両端に生じる電位差と所定の基準値とを比較し、上記
電位差が基準値以上になった場合に、シャント抵抗に流
れる電流値、すなわち負荷やパワートランジスタに流れ
る負荷電流が基準値を越えたものと判断し、パワートラ
ンジスタをオフにするように構成されている。
2. Description of the Related Art As a conventional semiconductor integrated circuit having an overcurrent detecting circuit in a power transistor for driving an external load, there is one disclosed in, for example, Japanese Patent Application Laid-Open No. 7-77546. In the above-described conventional device, a shunt resistor is inserted in the middle of a main current path passing through an external load, a power transistor, and a power supply, and a potential difference generated at both ends of the shunt resistor and a predetermined reference value are compared using a comparison circuit. In comparison, when the potential difference is equal to or greater than the reference value, it is determined that the current value flowing through the shunt resistor, that is, the load current flowing through the load or the power transistor exceeds the reference value, and the power transistor is turned off. It is configured.

【0003】[0003]

【発明が解決しようとする課題】上記のように従来の装
置においては、負荷やパワートランジスタと直列にシャ
ント抵抗が挿入されるので、シャント抵抗の分だけオン
抵抗が大きくなる。そしてシャント抵抗の両端の電位差
を比較器で基準値と比較するためには、電位差として少
なくとも200mV程度は必要なので、通常、シャント
抵抗値は数十mΩ程度の値が必要となる。この値はパワ
ートランジスタのオン抵抗と同程度なので、全体のオン
抵抗が2倍弱になる。上記のように全体のオン抵抗が大
きくなると、負荷に流れる電流が小さくなるという問題
がある。また、ソレノイド負荷ではLRの直列回路とな
るので、時定数が大きくなって立上りも悪くなるという
問題も生じる。さらに、チップに集積する際に、シャン
ト抵抗の分だけチップ面積が大きくなる。特に、シャン
ト抵抗は低抵抗であり、かつ大電流が流れるので、大き
な面積が必要となるため、全体の面積が大きくなり、か
つ集積回路にシャント抵抗を組み込むために複雑な製造
工程を必要とするという問題もある。
As described above, in the conventional device, the shunt resistor is inserted in series with the load and the power transistor, so that the on-resistance is increased by the amount of the shunt resistor. In order to compare the potential difference between both ends of the shunt resistor with the reference value by the comparator, at least about 200 mV is required as the potential difference. Therefore, the shunt resistance value usually needs to be about several tens mΩ. Since this value is substantially equal to the on-resistance of the power transistor, the overall on-resistance is less than twice. As described above, when the overall on-resistance increases, there is a problem that the current flowing to the load decreases. In addition, since a solenoid load forms a series circuit of LR, there is also a problem that the time constant becomes large and the rise becomes poor. Further, when integrated on a chip, the chip area is increased by the amount of the shunt resistor. In particular, since the shunt resistor has a low resistance and a large current flows, a large area is required, so that the entire area becomes large and a complicated manufacturing process is required to incorporate the shunt resistor into the integrated circuit. There is also a problem.

【0004】本発明は上記のごとき従来技術の問題を解
決するためになされたものであり、別個のシャント抵抗
を設ける必要がなく、主電流路の抵抗増加を抑制するこ
との出来る半導体集積回路を提供することを目的とす
る。
SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and there is no need to provide a separate shunt resistor, and a semiconductor integrated circuit capable of suppressing an increase in the resistance of the main current path. The purpose is to provide.

【0005】[0005]

【課題を解決するための手段】上記の目的を達成するた
め、本発明においては、特許請求の範囲に記載するよう
に構成している。すなわち、請求項1に記載の発明にお
いては、半導体チップを実装しようとする場合に必ず必
要となるボンディングワイヤを過電流検知回路の検出抵
抗として用いるように構成している。ボンディングワイ
ヤは半導体チップと実装部材の接続部(例えばパッケー
ジのパッド)とを接続する金属線であり、その抵抗値は
小さいが、主電流路(例えば、電源−外部負荷−パワー
トランジスタ−接地)には大電流が流れるので、その経
路に接続されたボンディングワイヤの両端の電圧降下は
比較器で十分検出できる程度の値となる。なお、比較器
は入力インピーダンスが大きいので殆ど電流が流れず、
そのため比較器に接続されたボンディングワイヤの電圧
降下は無視できる。したがって主電流路に流れる電流を
正確に検出することが出来る。上記のように構成すれ
ば、新たにシャント抵抗を主電流路に直列に挿入する必
要がないため、半導体集積回路全体のオン抵抗を増大さ
せることがなく、また複雑な製造工程を必要とするとい
う問題も解決することができ、かつシャント抵抗分だけ
集積回路の面積を小さくできる。
Means for Solving the Problems In order to achieve the above object, the present invention is configured as described in the claims. That is, according to the first aspect of the present invention, a bonding wire, which is necessary when mounting a semiconductor chip, is used as a detection resistor of the overcurrent detection circuit. A bonding wire is a metal wire that connects a semiconductor chip and a connection portion of a mounting member (for example, a pad of a package) and has a small resistance value, but is connected to a main current path (for example, a power supply-external load-power transistor-ground). Since a large current flows, the voltage drop across the bonding wire connected to the path has a value that can be sufficiently detected by the comparator. Since the comparator has a large input impedance, almost no current flows.
Therefore, the voltage drop of the bonding wire connected to the comparator can be ignored. Therefore, the current flowing in the main current path can be accurately detected. With the above configuration, it is not necessary to newly insert a shunt resistor in series with the main current path, so that the on-resistance of the entire semiconductor integrated circuit does not increase and a complicated manufacturing process is required. The problem can be solved, and the area of the integrated circuit can be reduced by the shunt resistance.

【0006】また、請求項2に記載の発明は、請求項1
のより具体的な構成を示すものであり、パワートランジ
スタの二つの主端子のうちの第1の主端子と実装部材の
接続部とを接続する第1のボンディングワイヤの他に、
制御手段の電源端子と実装部材の接続部とを接続する第
2のボンディングワイヤを別個に設けたものである。上
記パワートランジスタの二つの主端子とは、例えばバイ
ポーラトランジスタではコレクタとエミッタ、MOSト
ランジスタではドレインとソースに相当する。また、第
1の主端子とは、上記二つの主端子のどちらでも可能で
ある。なお、この構成は、例えば後記図1〜図6に示す
実施の形態に相当する。
[0006] The invention described in claim 2 is the invention according to claim 1.
In addition to the first bonding wire connecting the first main terminal of the two main terminals of the power transistor and the connection portion of the mounting member,
A second bonding wire for separately connecting the power supply terminal of the control means and the connection portion of the mounting member is provided separately. The two main terminals of the power transistor correspond to, for example, a collector and an emitter in a bipolar transistor and a drain and a source in a MOS transistor. Further, the first main terminal can be any of the above two main terminals. This configuration corresponds to, for example, an embodiment shown in FIGS.

【0007】また、請求項3に記載の発明は、第1、第
2の二つのボンディングワイヤの他に、一端が前記実装
部材の接続部に接続された第3のボンディングワイヤを
設け、第3のボンディングワイヤの他端の電位と第1の
ボンディングワイヤのパワートランジスタ側端部の電位
との差の電位を、過電流検知用の電位差として検出する
ように構成したものである。なお、この構成は、例えば
後記図3、図4、図6に示す実施の形態に相当する。こ
のように構成することにより、第3のボンディングワイ
ヤには実質的に電流が流れないので、制御手段の消費電
流に関わりなく、常に正確に過電流検知用の電位差を検
出することが出来る。
According to a third aspect of the present invention, in addition to the first and second two bonding wires, a third bonding wire having one end connected to a connection portion of the mounting member is provided. The potential of the difference between the potential of the other end of the bonding wire and the potential of the first bonding wire on the side of the power transistor is detected as a potential difference for overcurrent detection. This configuration corresponds to, for example, an embodiment shown in FIGS. 3, 4, and 6 described later. With this configuration, since substantially no current flows through the third bonding wire, the potential difference for overcurrent detection can always be accurately detected regardless of the current consumption of the control means.

【0008】また、請求項4に記載の発明は、パワート
ランジスタを流れる電流の1/Nの電流が流れるモニタ
用トランジスタと、該モニタ用トランジスタの二つの主
端子のうちの第1の主端子と実装部材の接続部とを接続
する第4のボンディングワイヤを設け、いわゆるミラー
回路を用いたものである。なお、この構成は、例えば後
記図5、図6の実施の形態に相当する。このように構成
することにより、過電流の検出電流値の設計自由度を増
すことができるので、過電流の検出電流値を製造ばらつ
き等にあまり左右されない精度のよい設計とすることが
できる。
According to a fourth aspect of the present invention, there is provided a monitoring transistor through which 1 / N of the current flowing through the power transistor flows, and a first main terminal of the two main terminals of the monitoring transistor. A so-called mirror circuit is provided by providing a fourth bonding wire for connecting the connection portion of the mounting member. This configuration corresponds to, for example, an embodiment shown in FIGS. 5 and 6 described later. With this configuration, the degree of freedom in designing the overcurrent detection current value can be increased, so that the overcurrent detection current value can be designed with high accuracy that is not significantly affected by manufacturing variations and the like.

【0009】[0009]

【発明の効果】上記のように本発明においては、半導体
チップを実装しようとする場合に必ず必要となるボンデ
ィングワイヤを過電流検知回路の検出抵抗として用いる
ように構成したことにより、新たに検出用のシャント抵
抗を直列に挿入する必要がないので、半導体集積回路全
体のオン抵抗が高くなるという問題を解決することがで
き、また半導体チップにシャント抵抗を組み込む必要が
ないので、複雑な製造工程も不要になると共に、シャン
ト抵抗分だけ集積回路の面積を小さくできる、という効
果が得られる。
As described above, according to the present invention, a bonding wire, which is always necessary when a semiconductor chip is to be mounted, is used as a detection resistor of an overcurrent detection circuit. Since it is not necessary to insert a shunt resistor in series, it is possible to solve the problem that the on-resistance of the entire semiconductor integrated circuit is increased. This eliminates the need for the shunt resistor and reduces the area of the integrated circuit by the shunt resistance.

【0010】また、請求項3においては、上記の効果に
加えて、制御手段の消費電流に関わりなく、常に正確に
過電流検知用の電位差を検出することが出来る、という
効果が得られる。また、請求項4においては、過電流の
検出電流値の設計自由度を増すことができるので、過電
流の検出電流値を製造ばらつき等にあまり左右されない
精度のよい設計とすることができる、という効果が得ら
れる。
According to the third aspect of the present invention, in addition to the above effect, an effect is obtained that the potential difference for overcurrent detection can always be accurately detected regardless of the current consumption of the control means. According to the fourth aspect, the degree of freedom in designing the overcurrent detection current value can be increased, so that the overcurrent detection current value can be designed with high accuracy that is not significantly affected by manufacturing variations and the like. The effect is obtained.

【0011】[0011]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

(第1の実施の形態)図1は、本発明によるパワートラ
ンジスタに過電流検知回路を備えた半導体集積回路の第
1の実施の形態を示す回路図である。まず、構成を説明
する。破線で囲んだ部分301は半導体集積回路のパッ
ケージ実装範囲を示している。また破線で囲んだ部分3
02は、パワートランジスタ100と処理回路303を
集積した半導体集積回路の半導体チップの部分である。
処理回路303(破線で囲んだ部分)は、制御回路30
4と比較回路305と基準電圧回路306からなってい
る。また308〜312は、それぞれ半導体チップ30
2のボンディングパッドであり、313〜316は、そ
れぞれパッケージのボンディングパッドである。317
〜321は、それぞれ半導体チップのボンディングパッ
ド308〜312とパッケージのボンディングパッド3
13〜316とを接続するボンディングワイヤである。
また、330はパワートランジスタ100に駆動される
外部負荷である。
(First Embodiment) FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor integrated circuit provided with an overcurrent detection circuit in a power transistor according to the present invention. First, the configuration will be described. A portion 301 surrounded by a broken line indicates a package mounting range of the semiconductor integrated circuit. Part 3 surrounded by a broken line
Reference numeral 02 denotes a semiconductor chip portion of a semiconductor integrated circuit in which the power transistor 100 and the processing circuit 303 are integrated.
The processing circuit 303 (portion surrounded by a broken line) includes the control circuit 30
4 and a comparison circuit 305 and a reference voltage circuit 306. 308 to 312 are the semiconductor chips 30 respectively.
2, bonding pads 313 to 316 are bonding pads of the package. 317
321 are bonding pads 308 to 312 of the semiconductor chip and bonding pads 3 of the package, respectively.
13 to 316.
Reference numeral 330 denotes an external load driven by the power transistor 100.

【0012】次に作用を説明する。通常動作時は、パワ
ートランジスタ100は、制御回路304によって入力
端子310の信号に対応してオンオフ制御され、外部負
荷330を駆動する。また、パワートランジスタ100
のソース端子に接続されたボンディングワイヤ317の
両端の電位差と基準電圧回路306の基準電圧とを比較
回路305で比較している。そして異常時、例えば外部
負荷330がショートするなど、パワートランジスタ1
00に過電流が流れた場合には、ボンディングワイヤ3
17の両端の電位差が基準電圧より大きくなったことを
比較回路305で検出し、制御回路304により入力端
子310の信号の如何にかかわらず、パワートランジス
タ100をオフさせ、過電流によるパワートランジスタ
100やボンディングワイヤ317、321の焼損など
の故障を防止する。
Next, the operation will be described. During normal operation, the power transistor 100 is turned on and off by the control circuit 304 according to the signal of the input terminal 310, and drives the external load 330. In addition, the power transistor 100
The comparison circuit 305 compares the potential difference between both ends of the bonding wire 317 connected to the source terminal of the reference voltage circuit and the reference voltage of the reference voltage circuit 306. When an abnormality occurs, for example, the external load 330 is short-circuited.
00, an overcurrent flows through the bonding wire 3
The comparison circuit 305 detects that the potential difference between both ends of the terminal 17 becomes larger than the reference voltage, and the control circuit 304 turns off the power transistor 100 irrespective of the signal of the input terminal 310, and the power transistor 100 Failure such as burning of the bonding wires 317 and 321 is prevented.

【0013】上記のように、ボンディングワイヤ317
は、過電流の検出を行う検出抵抗となっている。すなわ
ち、処理回路303の接地用パッド309は、パワート
ランジスタ100用のボンディングワイヤ317とは別
個に設けられたボンディングワイヤ318によってパッ
ケージのボンディングパッド313と接続されている。
そして処理回路303からボンディングワイヤ318を
介して流れる電流は、パワートランジスタ100からボ
ンディングワイヤ317を介して流れる電流に比較して
大幅に小さい。例えば、ボンディングワイヤ317を介
して流れる電流は数A〜数十A程度であるのに対し、ボ
ンディングワイヤ318を介して流れる電流は一般に数
mA程度である。そのためボンディングワイヤ317の
両端の電位差は数百mVになるのに対し、ボンディング
ワイヤ318の両端の電位差はその1000分の1程度
であり、それによる誤差は無視できる。
As described above, the bonding wire 317
Are detection resistors for detecting overcurrent. That is, the grounding pad 309 of the processing circuit 303 is connected to the bonding pad 313 of the package by the bonding wire 318 provided separately from the bonding wire 317 for the power transistor 100.
The current flowing from the processing circuit 303 via the bonding wire 318 is significantly smaller than the current flowing from the power transistor 100 via the bonding wire 317. For example, the current flowing through the bonding wire 317 is about several A to several tens A, whereas the current flowing through the bonding wire 318 is generally about several mA. Therefore, while the potential difference between both ends of the bonding wire 317 is several hundred mV, the potential difference between both ends of the bonding wire 318 is about 1/1000 of the potential difference, and the error due to this is negligible.

【0014】例えば、ボンディングワイヤ317を、直
径38μmで長さ3mmのAuワイヤを3本並列で構成
すると、その抵抗値は21mΩであり、過電流の検出電
流値が10Aの場合には、基準電圧値を0.21Vとす
ればよい。このとき比較回路305の入力インピーダン
スは極めて大きいため、処理回路用のボンディングワイ
ヤ318に流れる電流は一般的に数mAなので、ボンデ
ィングワイヤ318の両端に生じる電位差による誤差は
無視できる。
For example, when three Au wires each having a diameter of 38 μm and a length of 3 mm are formed in parallel as the bonding wires 317, the resistance value is 21 mΩ, and when the overcurrent detection current value is 10 A, the reference voltage is The value may be set to 0.21V. At this time, since the input impedance of the comparison circuit 305 is extremely large, the current flowing through the bonding wire 318 for the processing circuit is generally several mA, so that the error due to the potential difference generated at both ends of the bonding wire 318 can be ignored.

【0015】なお、ボンディングワイヤ317の抵抗の
温度係数を考慮して、基準電圧回路306に温度係数を
持たせるように設計すれば、過電流の検出電流値の温度
特性を補償することも可能である上記のように、本発明
によるパワートランジスタに過電流検知回路を備えた半
導体集積回路によれば、半導体チップを実装しようとす
る場合に必ず必要となるボンディングワイヤを過電流検
知回路の検出抵抗として用いるように構成したことによ
り、新たに検出用のシャント抵抗を直列に挿入する必要
がないので、半導体集積回路全体のオン抵抗が高くなる
という問題を解決することができ、また半導体チップに
シャント抵抗を組み込む必要がないので、複雑な製造工
程も不要になると共に、シャント抵抗分だけ集積回路の
面積を小さくできる。
If the reference voltage circuit 306 is designed to have a temperature coefficient in consideration of the temperature coefficient of the resistance of the bonding wire 317, the temperature characteristic of the overcurrent detection current value can be compensated. As described above, according to the semiconductor integrated circuit including the overcurrent detection circuit in the power transistor according to the present invention, the bonding wire that is necessarily required when mounting the semiconductor chip is used as the detection resistor of the overcurrent detection circuit. With this configuration, it is not necessary to newly insert a shunt resistor for detection in series, so that the problem that the on-resistance of the entire semiconductor integrated circuit becomes high can be solved. Since there is no need to incorporate an integrated circuit, complicated manufacturing steps are not required, and the area of the integrated circuit can be reduced by the amount of the shunt resistor. .

【0016】次に、図2は、図1の回路のより具体的な
構成を示す回路図である。なお、ボンディングワイヤは
電気的に有意なもののみを示している。また、抵抗の形
で示したボンディングワイヤ106、107以外の結線
は実効的に電気抵抗がないものとして説明する。
FIG. 2 is a circuit diagram showing a more specific configuration of the circuit of FIG. Note that only electrically significant bonding wires are shown. Also, the description will be made on the assumption that the connections other than the bonding wires 106 and 107 shown in the form of resistors have no effective electrical resistance.

【0017】図2において、100はパワートランジス
タ、101は外部負荷となるソレノイド(図1の330
に相当)、102は信号入力端子(310に相当)、1
03はアンド回路(304に相当)、104は比較器
(305に相当)、105は基準電圧回路(306に相
当)、106はパワートランジスタ100の電流が流れ
るボンディングワイヤ(317に相当)、107は処理
回路の電流が流れるボンディングワイヤ(318に相
当)である。
In FIG. 2, reference numeral 100 denotes a power transistor, and 101 denotes a solenoid (330 in FIG. 1) serving as an external load.
, 102 are signal input terminals (corresponding to 310), 1
03 is an AND circuit (corresponding to 304); 104 is a comparator (corresponding to 305); 105 is a reference voltage circuit (corresponding to 306); 106 is a bonding wire (corresponding to 317) through which the current of the power transistor 100 flows; This is a bonding wire (equivalent to 318) through which the current of the processing circuit flows.

【0018】図2の回路において、ボンディングワイヤ
106のパワートランジスタ100側の電位(ボンディ
ングワイヤ106両端の電位差)と基準電圧回路105
の基準電圧とを比較器104で比較し、ボンディングワ
イヤ106の電位が基準電圧以上になると比較器104
の出力が“Low”になり、入力端子102の入力信号
に関わりなく、アンド回路103の出力は“Low”に
なる。そのためパワートランジスタ100はオフにな
り、過電流による故障を防止することが出来る。ここ
で、比較器105の入力インピーダンスは極めて高いの
で、処理回路側のボンディングワイヤ107に流れる電
流は非常に小さく、したがってこの抵抗による誤差は無
視できる程度である。
In the circuit shown in FIG. 2, the potential of the bonding wire 106 on the power transistor 100 side (potential difference between both ends of the bonding wire 106) and the reference voltage circuit 105
Is compared with the reference voltage by the comparator 104. When the potential of the bonding wire 106 becomes higher than the reference voltage, the comparator 104
Becomes "Low", and the output of the AND circuit 103 becomes "Low" regardless of the input signal of the input terminal 102. Therefore, the power transistor 100 is turned off, and a failure due to an overcurrent can be prevented. Here, since the input impedance of the comparator 105 is extremely high, the current flowing through the bonding wire 107 on the processing circuit side is very small, and therefore, the error due to this resistance is negligible.

【0019】(第2の実施の形態)図3は、本発明によ
るパワートランジスタに過電流検知回路を備えた半導体
集積回路の第2の実施の形態を示す回路図である。第2
の実施の形態の構成や作用のうち前記第1の実施の形態
と異なる点は、半導体チップ302のボンディングパッ
ド401とボンディングワイヤ402を追加し、パッケ
ージ301の接地用ボンディングパッド313の電位を
半導体チップ302に入力するようにし、ボンディング
ワイヤ317のパワートランジスタ側電位(ボンディン
グパッド308の電位)とボンディングパッド401か
ら入力されるボンディングパッド313の電位との差電
圧を基準電圧と比較させるように構成した点である。
(Second Embodiment) FIG. 3 is a circuit diagram showing a second embodiment of a semiconductor integrated circuit provided with an overcurrent detection circuit in a power transistor according to the present invention. Second
The second embodiment differs from the first embodiment in the configuration and operation of the third embodiment in that a bonding pad 401 and a bonding wire 402 of a semiconductor chip 302 are added, and the potential of a ground bonding pad 313 of a package 301 is reduced. 302, and a difference voltage between the potential of the bonding wire 317 on the power transistor side (the potential of the bonding pad 308) and the potential of the bonding pad 313 input from the bonding pad 401 is compared with a reference voltage. It is.

【0020】第1の実施の形態で得られた効果は、第2
の実施の形態でも同様に得ることができる。さらに第2
の実施の形態においては、次のごとき作用、効果があ
る。
The effect obtained in the first embodiment is the second effect.
In the embodiment described above, the same can be obtained. Second
The embodiment has the following operation and effect.

【0021】第1の実施の形態では、処理回路の消費電
流がボンディングワイヤ318に流れ、その両端に電位
差が生じる。前記のごとく、一般的にはこの電位差によ
る誤差は無視できる程度であるが、第2の実施の形態に
おいては、ボンディングワイヤ318に流れる電流によ
る誤差もなくし、より正確な過電流検知を行なうように
したものである。すなわち、ボンディングワイヤ402
には実質的に電流が流れないので、その両端には電位差
が生じることがなく、ボンディングパッド401から入
力される電位はボンディングパッド313の電位と一致
する。したがって、この値とボンディングワイヤ317
のパワートランジスタ側電位との差の電位を求めれば、
ボンディングワイヤ317の両端の電位差を正確に検出
することが出来、処理回路の消費電流によってボンディ
ングワイヤ318の両端に生じる電位差に関わりなく、
正確に過電流検知を行なうことが出来る。
In the first embodiment, the current consumed by the processing circuit flows through the bonding wire 318, and a potential difference occurs between both ends. As described above, the error due to the potential difference is generally negligible, but in the second embodiment, the error due to the current flowing through the bonding wire 318 is eliminated, and more accurate overcurrent detection is performed. It was done. That is, the bonding wire 402
Since substantially no current flows through the bonding pad 401, there is no potential difference between both ends, and the potential input from the bonding pad 401 matches the potential of the bonding pad 313. Therefore, this value and the bonding wire 317
By calculating the potential difference from the power transistor side potential of
The potential difference between both ends of the bonding wire 317 can be accurately detected, and regardless of the potential difference generated between both ends of the bonding wire 318 due to current consumption of the processing circuit.
Overcurrent detection can be performed accurately.

【0022】なお、図3においては、ボンディングワイ
ヤ317のパワートランジスタ側電位とボンディングパ
ッド401から入力されるボンディングパッド313の
電位とを直接に比較回路305に入力するように記載し
ているが、実際には、後記図4で説明するように、差動
増幅器等を用いて上記両電位の差の電位を求め、それを
比較回路305に入力する。
Although FIG. 3 shows that the potential of the bonding wire 317 on the power transistor side and the potential of the bonding pad 313 input from the bonding pad 401 are directly input to the comparison circuit 305, in practice, As described later with reference to FIG. 4, the potential difference between the two potentials is obtained using a differential amplifier or the like, and is input to the comparison circuit 305.

【0023】次に、図4は、図3の回路のより具体的な
構成を示す回路図である。なお、ボンディングワイヤは
電気的に有意なもののみを示している。また、抵抗の形
で示したボンディングワイヤ106、107、108以
外の結線は実効的に電気抵抗がないものとして説明す
る。
FIG. 4 is a circuit diagram showing a more specific configuration of the circuit of FIG. Note that only electrically significant bonding wires are shown. Also, the description will be made on the assumption that the connections other than the bonding wires 106, 107, and 108 shown in the form of resistors have no effective electrical resistance.

【0024】図4において、108はパッケージの接地
用パッドに接続されたボンディングワイヤ(図3の40
2に相当)、109は差動増幅器(図3の305の一部
に相当)である。差動増幅器109は、例えば演算増幅
器と抵抗とによって構成する。この差動増幅器でボンデ
ィングワイヤ106のパワートランジスタ100側の電
位とボンディングワイヤ108の電位との差を検出し、
それを比較器104に与え、基準電圧と比較する。ここ
で、ボンディングワイヤ108には実質的に電流が流れ
ないので、この両端には電位差が生じない。したがって
この電位とボンディングワイヤ106のパワートランジ
スタ100側の電位との差を求めることにより、パワー
トランジスタ100を流れる電流によってボンディング
ワイヤ106の両端に生じた電位差を正確に検出するこ
とが出来る。そして、この関係はボンディングワイヤ1
07を流れる処理回路の消費電流に影響されないので、
処理回路の消費電流に関わりなく、正確な過電流検知を
行なうことが出来る。
In FIG. 4, reference numeral 108 denotes a bonding wire (40 in FIG. 3) connected to a ground pad of the package.
Reference numeral 109 denotes a differential amplifier (corresponding to a part of 305 in FIG. 3). The differential amplifier 109 includes, for example, an operational amplifier and a resistor. The differential amplifier detects the difference between the potential of the bonding wire 106 on the power transistor 100 side and the potential of the bonding wire 108,
This is supplied to a comparator 104 and compared with a reference voltage. Here, since substantially no current flows through the bonding wire 108, there is no potential difference between both ends. Therefore, by calculating the difference between this potential and the potential of the bonding wire 106 on the power transistor 100 side, the potential difference generated at both ends of the bonding wire 106 by the current flowing through the power transistor 100 can be accurately detected. And this relationship is bonding wire 1
07 is not affected by the current consumption of the processing circuit flowing through
Accurate overcurrent detection can be performed regardless of the current consumption of the processing circuit.

【0025】なお、これまでの説明においては、パワー
トランジスタのソース端子に接続したボンディングワイ
ヤを検出抵抗として用いた例を説明してきたが、ドレイ
ン端子側のボンディングワイヤ321を検出抵抗として
用いても構わない。
In the above description, an example in which a bonding wire connected to the source terminal of the power transistor is used as the detection resistor has been described. However, the bonding wire 321 on the drain terminal side may be used as the detection resistor. Absent.

【0026】また、半導体集積回路としては、パワート
ランジスタと処理回路が1個の例で説明してきたが、パ
ワートランジスタと処理回路が複数個集積していても構
わない。また、パワートランジスタとして電界効果トラ
ンジスタを用いた例で説明してきたが、パイポーラトラ
ンジスタなど他のパワートランジスタ用デバイスでも構
わない。また、半導体集積回路をパッケージ実装した例
で示したが、ペアチップ実装でも構わない。何れにして
もパワートランジスタの主電流が流れる端子と実装部材
の接続部とを接続するボンディングワイヤを検出抵抗と
するように構成すればよい。
Further, the semiconductor integrated circuit has been described by using one power transistor and one processing circuit, but a plurality of power transistors and processing circuits may be integrated. Further, although an example using a field effect transistor as the power transistor has been described, other power transistor devices such as a bipolar transistor may be used. Further, although an example is shown in which the semiconductor integrated circuit is packaged, it may be mounted in a pair chip. In any case, the configuration may be such that the bonding wire connecting the terminal of the power transistor through which the main current flows and the connection portion of the mounting member is used as the detection resistor.

【0027】(第3の実施の形態)図5は、本発明によ
るパワートランジスタに過電流検知回路を備えた半導体
集積回路の第3の実施の形態を示す回路図である。第3
の実施の形態の構成のうち第1の実施の形態との異なる
点は、パワートランジスタ100の代わりに、面積が
1:Nの比になっているモニタ用パワートランジスタ5
02とメインパワートランジスタ501を設け、モニタ
用パワートランジスタ502のソース用ボンディングパ
ッド503とボンディングワイヤ504を追加し、モニ
タ用パワートランジスタ502のソース電位(ボンディ
ングワイヤ504のモニタ用パワートランジスタ側の電
位)を比較回路305で基準電圧と比較するように構成
した点である。
(Third Embodiment) FIG. 5 is a circuit diagram showing a third embodiment of a semiconductor integrated circuit having a power transistor and an overcurrent detection circuit according to the present invention. Third
The difference between the configuration of the second embodiment and the first embodiment is that the power transistor 100 is replaced with a monitoring power transistor 5 having an area ratio of 1: N.
02 and a main power transistor 501, a source bonding pad 503 and a bonding wire 504 of the monitor power transistor 502 are added, and the source potential of the monitor power transistor 502 (the potential of the bonding wire 504 on the monitor power transistor side) is increased. The difference is that the comparison circuit 305 is configured to compare with the reference voltage.

【0028】次に作用を説明する。本回路において、モ
ニタ用パワートランジスタ502には、メインパワート
ランジスタ501を流れる電流の1/Nの電流が流れて
いる。この1/Nの電流でボンディングワイヤ504に
生じる電位が予め定められた基準電圧より大きくなった
ことを比較回路305で検出する。その他の作用は前記
図1と同様である。
Next, the operation will be described. In this circuit, 1 / N of the current flowing through the main power transistor 501 flows through the monitoring power transistor 502. The comparison circuit 305 detects that the potential generated on the bonding wire 504 by the 1 / N current becomes higher than a predetermined reference voltage. Other operations are the same as those in FIG.

【0029】前記第1の実施の形態で得られた効果は、
第3の実施の形態でも同様に得ることができる。さら
に、第3の実施の形態では、メインパワートランジスタ
501を流れる電流の1/Nの電流が流れるモニタ用パ
ワートランジスタ502を設け、モニタ用パワートラン
ジスタ502に接続されたボンディングワイヤの電位を
検出電位とするように構成したので、過電流の検出電流
値の設計自由度を増すことができる。すなわち、第1の
実施の形態では、過電流の検出電流値を設計する場合、
ボンディングワイヤ317の直径や長さはパワートラン
ジスタ100のレイアウトや流す電流値によりほぼ決定
されてしまう。したがって過電流の検出値を設定するに
は基準電圧値で調整するしかない。その点、第3の実施
の形態では、過電流の検出電流値を設計する場合には、
モニタ用パワートランジスタ502とメインパワートラ
ンジスタ501の面積比1:Nや、モニタ用パワートラ
ンジスタ502のレイアウトにも自由度があるので、ボ
ンディングワイヤ504の直径や長さも、設計用パラメ
ータとして用いることができる。
The effect obtained in the first embodiment is as follows.
The same can be obtained in the third embodiment. Further, in the third embodiment, a monitoring power transistor 502 through which 1 / N of the current flowing through the main power transistor 501 flows is provided, and the potential of a bonding wire connected to the monitoring power transistor 502 is determined as a detection potential. Therefore, the degree of freedom in designing the overcurrent detection current value can be increased. That is, in the first embodiment, when designing the overcurrent detection current value,
The diameter and length of the bonding wire 317 are almost determined by the layout of the power transistor 100 and the value of the flowing current. Therefore, the only way to set the overcurrent detection value is to adjust the reference voltage value. In this regard, in the third embodiment, when designing the overcurrent detection current value,
Since the area ratio of the monitor power transistor 502 to the main power transistor 501 is 1: N and the layout of the monitor power transistor 502 is flexible, the diameter and length of the bonding wire 504 can also be used as design parameters. .

【0030】上記の構成においては、過電流の検出電流
値の設計自由度を増すことができるので、過電流の検出
電流値を製造ばらつき等にあまり左右されない精度のよ
い設計とすることができる、という効果が得られる。
In the above configuration, since the degree of freedom in designing the overcurrent detection current value can be increased, the overcurrent detection current value can be designed with high accuracy which is not significantly affected by manufacturing variations and the like. The effect is obtained.

【0031】(第4実施の形態)図6は、本発明による
パワートランジスタに過電流検知回路を備えた半導体集
積回路の第4の実施の形態を示す回路図である。第4の
実施の形態の構成および作用は、第2の実施の形態と第
3の実施の形態とを合わせたものである。そして第4の
実施の形態では、第2の実施の形態および第3の実施の
形態で得られた効果を両方得ることができる。
(Fourth Embodiment) FIG. 6 is a circuit diagram showing a fourth embodiment of a semiconductor integrated circuit provided with an overcurrent detection circuit in a power transistor according to the present invention. The configuration and operation of the fourth embodiment are obtained by combining the second embodiment and the third embodiment. In the fourth embodiment, both effects obtained in the second embodiment and the third embodiment can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施の形態を示す回路図。FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

【図2】第1の実施の形態のより具体的な回路図。FIG. 2 is a more specific circuit diagram of the first embodiment.

【図3】本発明の第2の実施の形態を示す回路図。FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

【図4】第2の実施の形態のより具体的な回路図。FIG. 4 is a more specific circuit diagram of the second embodiment.

【図5】本発明の第3の実施の形態を示す回路図。FIG. 5 is a circuit diagram showing a third embodiment of the present invention.

【図6】本発明の第4の実施の形態を示す回路図。FIG. 6 is a circuit diagram showing a fourth embodiment of the present invention.

【符号の説明】[Explanation of symbols]

100…パワートランジスタ 101…外部
負荷となるソレノイド 102…信号入力端子 103…アン
ド回路 104…比較器 105…基準
電圧回路 106…パワートランジスタ100の電流が流れるボン
ディングワイヤ 107…処理回路の電流が流れるボンディングワイヤ 108…パッケージの接地用パッドに接続されたボンデ
ィングワイヤ 109…差動増幅器 301…半導体集積回路のパッケージ実装範囲 302…半導体集積回路の半導体チップ 303…処理回路 304…制御
回路 305…比較回路 306…基準
電圧回路 308〜312、401、503…半導体チップのボン
ディングパッド 313〜316…パッケージのボンディングパッド 317〜321、402、504…ボンディングワイヤ 330…外部負荷 501…メインパワートランジスタ 502…モニ
タ用トランジスタ
DESCRIPTION OF SYMBOLS 100 ... Power transistor 101 ... Solenoid used as an external load 102 ... Signal input terminal 103 ... AND circuit 104 ... Comparator 105 ... Reference voltage circuit 106 ... Bonding wire through which the current of the power transistor 100 flows 107 ... Bonding wire through which the current of the processing circuit flows Reference numeral 108: bonding wire connected to the ground pad of the package 109: differential amplifier 301: package mounting range of the semiconductor integrated circuit 302: semiconductor chip of the semiconductor integrated circuit 303: processing circuit 304 ... control circuit 305 ... comparison circuit 306: reference Voltage circuits 308 to 312, 401, 503: bonding pads of semiconductor chips 313 to 316, bonding pads of packages 317 to 321, 402, 504, bonding wires 330, external loads 501, In power transistor 502 ... monitor transistor

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】外部の負荷を駆動するパワートランジスタ
と、 前記パワートランジスタに流れる電流、もしくはそれに
比例した電流が流れる検出抵抗と、 前記検出抵抗の両端に生じた電位差を検出し、該電位差
が所定の値以上になった場合に前記パワートランジスタ
をオフにする制御手段と、 を備えた半導体集積回路であって、 前記検出抵抗として、前記半導体集積回路を形成した半
導体チップと実装部材の接続部とを接続するボンディン
グワイヤを用いたことを特徴とする半導体集積回路。
1. A power transistor for driving an external load, a detection resistor through which a current flowing in the power transistor or a current proportional thereto is detected, and a potential difference between both ends of the detection resistor is detected. And control means for turning off the power transistor when the value becomes equal to or more than the value of the semiconductor integrated circuit, wherein, as the detection resistor, a connection portion between a semiconductor chip on which the semiconductor integrated circuit is formed and a mounting member; A semiconductor integrated circuit characterized by using a bonding wire for connecting the semiconductor integrated circuit.
【請求項2】前記パワートランジスタの二つの主端子の
うちの第1の主端子と前記実装部材の接続部とを接続す
る第1のボンディングワイヤと、前記制御手段の電源端
子と前記実装部材の接続部とを接続する第2のボンディ
ングワイヤとを別個に設け、前記第1のボンディングワ
イヤの前記パワートランジスタの第1の主端子側端部の
電位と前記実装部材の接続部の電位との電位差を検出す
るように構成したことを特徴とする請求項1に記載の半
導体集積回路。
A first bonding wire for connecting a first main terminal of the two main terminals of the power transistor to a connection portion of the mounting member; a power supply terminal of the control means; A second bonding wire for connecting to the connection portion is provided separately, and a potential difference between a potential of the first bonding wire on the side of the first main terminal of the power transistor and a potential of the connection portion of the mounting member. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is configured to detect
【請求項3】前記第1、第2の二つのボンディングワイ
ヤの他に、一端が前記実装部材の接続部に接続された第
3のボンディングワイヤを設け、前記第3のボンディン
グワイヤの他端の電位と前記第1のボンディングワイヤ
の前記パワートランジスタの第1の主端子側端部の電位
との差の電位を、前記過電流検知用の電位差として検出
するように構成したことを特徴とする請求項2に記載の
半導体集積回路。
3. A third bonding wire, one end of which is connected to a connection portion of the mounting member, in addition to the first and second bonding wires, and the other end of the third bonding wire is provided. The apparatus according to claim 1, wherein a potential difference between a potential and a potential of an end portion of the first bonding wire on the first main terminal side of the power transistor is detected as the potential difference for detecting the overcurrent. Item 3. A semiconductor integrated circuit according to item 2.
【請求項4】前記パワートランジスタを流れる電流の1
/Nの電流が流れるモニタ用トランジスタと、該モニタ
用トランジスタの二つの主端子のうちの第1の主端子と
前記実装部材の接続部とを接続する第4のボンディング
ワイヤを設け、該第4のボンディングワイヤを前記検出
抵抗として用いるように構成したことを特徴とする請求
項1乃至請求項3の何れかに記載の半導体集積回路。
4. The power transistor according to claim 1, wherein
/ N, and a fourth bonding wire for connecting the first main terminal of the two main terminals of the monitoring transistor to the connection portion of the mounting member, and 4. The semiconductor integrated circuit according to claim 1, wherein said bonding wire is used as said detection resistor.
JP9275741A 1997-10-08 1997-10-08 Semiconductor integrated circuit Pending JPH11121683A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9275741A JPH11121683A (en) 1997-10-08 1997-10-08 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9275741A JPH11121683A (en) 1997-10-08 1997-10-08 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH11121683A true JPH11121683A (en) 1999-04-30

Family

ID=17559753

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9275741A Pending JPH11121683A (en) 1997-10-08 1997-10-08 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH11121683A (en)

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US11728801B2 (en) 2013-11-20 2023-08-15 Rohm Co., Ltd. Switching device and electronic circuit
US11936369B2 (en) 2013-11-20 2024-03-19 Rohm Co., Ltd. Switching device and electronic circuit

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