JP2013210646A - Driver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a voltage drop by a wiring layer in a semiconductor integrated circuit device even when the number of output terminals of a driver is increased.SOLUTION: The driver comprises: a film substrate on which a first wiring layer and a second wiring layer are formed; and a semiconductor chip mounted on the film substrate by a chip-on film method. The first wiring layer is connected to an input terminal formed on an outer periphery of the film substrate, and the second wiring layer is connected among a plurality of terminals of the semiconductor chip. The first wiring layer and the second wiring layer are connected to each other. Power for the semiconductor chip or clock is transmitted via the first wiring layer and the second wiring layer, and the second wiring layer is formed between the semiconductor chip and the film substrate.

Description

  The present invention relates to a driver, and more particularly to a technique effective when applied to video signal line driving means (drain driver) of a liquid crystal display device capable of multi-gradation display.

2. Description of the Related Art An active matrix liquid crystal display device having an active element (for example, a thin film transistor) for each pixel and switching driving the active element is widely used as a display device such as a notebook personal computer.
This active matrix type liquid crystal display device applies a video signal voltage (a gray scale voltage corresponding to display data; hereinafter referred to as a gray scale voltage) to the pixel electrode through an active element. Therefore, it is not necessary to use a special driving method for preventing crosstalk as in a simple matrix liquid crystal display device, and multi-gradation display is possible.
One of the active matrix type liquid crystal display devices includes a TFT (Thin Film Transistor) type liquid crystal display panel (TFT-LCD), a drain driver disposed on the upper side of the liquid crystal display panel, and a side surface of the liquid crystal display panel. A TFT type liquid crystal display module including a gate driver and an interface unit is known.

FIG. 24 is a block diagram showing a schematic configuration of an example of a conventional TFT liquid crystal display module.
As shown in the drawing, a plurality of drain drivers 130 are arranged on one side of the long side of the liquid crystal panel (TFT-LCD) 10, and a plurality of gate drivers 140 are arranged on one side of the short side of the liquid crystal display panel 10.
Red (R), green (G), and blue (B) display data (video signal), clock signal, display timing signal, and sync signal (horizontal sync signal, vertical) output from the host computer such as a personal computer A control signal including a synchronization signal is input to the display control device (TFT controller) 110 via the interface connector.
Control signals, display data, and the like from the display control device 110 are input to each drain driver 130 via the TFT controller substrate 301 and the drain driver substrate 302.
A control signal from the display control device 110 is input to each gate driver 140 via the TFT controller substrate 301 and the gate driver substrate 303.
In FIG. 24, the wiring layer on the TFT controller substrate is not shown.
Further, on the drain driver substrate and the gate driver substrate, wiring layers other than the wiring layers shown in FIG. 24 are also provided. In FIG. 24, four drain driver substrates 302 and two gate driver substrates 303 are provided. Only the wiring layer of the book is illustrated.

The drain driver 130 and the gate driver 140 are constituted by semiconductor chips (IC), and these semiconductor chips (IC) are mounted on a film substrate by a so-called tape carrier method or a chip-on-film method.
As shown in FIG. 25, a wiring layer (COFA) is formed on the film substrate 310 from the periphery, and terminals (BUMP) provided around the semiconductor chip (IC) are bonded to the wiring layer (COFA). The
Here, the terminal (BUMP) of the drain driver is generally provided in the periphery thereof, and FIG. 26 shows an example.
As shown in FIG. 26, the input terminal (BUMP2) is arranged on one side so that the wiring from the drain driver substrate 302 can be connected, and the output terminal (BUMP1) is the other three sides or the input terminal (BUMP2). ) Are arranged in the peripheral part of the four sides including the left and right spaces of the arranged side.
Also, the output circuits 330 inside the drain driver corresponding to each output terminal (BUMP1) are generally arranged in a line in accordance with the output terminal position.
Such a liquid crystal display device is described in, for example, Patent Document 1 below.

JP-A-9-281930

In recent years, in liquid crystal display devices such as TFT liquid crystal display modules, the number of pixels of liquid crystal display panels has been increasing and high definition has been accompanied by demands for larger liquid crystal display panels. The number of gate signal lines and drain signal lines is also increasing, and the number of input / output terminals of the drain driver has to be increased.
For example, in an XGA specification liquid crystal display panel, the number of drain signal lines is 3072 (= 1024 × 3 (RGB)), and a drain driver having 384 output terminals is used. Therefore, the number of necessary drain drivers is 8 (= 3072/384).
On the other hand, as the definition of UXGA increases, the number of drain signal lines is 4800 (= 1600 × 3 (RGB)), and the drain driver having 384 output terminals is the same as described above. Is used, the number of drain drivers required for a UXGA type liquid crystal display panel is 12.5 (= 4800/384).
As described above, as the definition of the liquid crystal display panel increases, the number of drain lines per liquid crystal display panel increases and the number of necessary drain drivers increases.
As a result, the load capacity of the display control device 110 increases and the drain driver 130 cannot be driven.

In order to prevent the number of drain drivers from changing even if the liquid crystal display panel has a higher definition, it is necessary to increase the number of output terminals per drain driver.
In general, a semiconductor chip (IC) that constitutes a drain driver has a horizontally long outer shape, but if the number of output terminals (BUMP) per drain driver is increased, the semiconductor chip (IC) It is necessary to increase the lateral length.
In addition, a plurality of semiconductor chips (IC) are formed on a single semiconductor wafer and then separated, but as a horizontally long semiconductor chip (IC) having a longer lateral length, a single wafer is formed. As a result, the number of chips that can be obtained from the semiconductor device decreases, and the price of a single semiconductor chip (IC) increases.
Further, when a laterally long semiconductor chip (IC) having a longer lateral length is formed, when the semiconductor chip (IC) is formed on one semiconductor wafer surface by so-called step-and-repeat exposure, the exposure range is reduced. There is concern that it will be exceeded.
In order to solve this, it is necessary to use a more expensive exposure apparatus, and the price of one semiconductor chip (IC) becomes high.
On the other hand, as the market matures, liquid crystal display devices are required to be lower in price. However, when the semiconductor chip (IC) constituting the drain driver 130 becomes higher, the price of the liquid crystal display device increases. There is.

Further, as the number of drain signal lines increases, the pitch of the output terminals (BUMP1) of the drain driver 130 inevitably tends to decrease, and there is a concern that probing at the time of selection of the semiconductor chip (IC) becomes difficult. Yes.
Furthermore, as the number of drain signal lines increases, the circuit scale of one drain driver 130 tends to increase, and there is concern that a voltage drop due to wiring impedance inside the semiconductor chip (IC) cannot be ignored.
The present invention has been made to solve the problems of the prior art, and the object of the present invention is to sufficiently cope with an increase in the number of pixels of a liquid crystal display element in a liquid crystal display device. In addition, an object is to provide a technology that can reduce the price.
Another object of the present invention is to provide a technique capable of easily inspecting a liquid crystal display device even if the number of output terminals of the semiconductor integrated circuit device of the video line driving means is increased. is there.
Another object of the present invention is to prevent a voltage drop due to a wiring layer inside the semiconductor integrated circuit device even if the number of output terminals of the semiconductor integrated circuit device of the video line driving means increases in the liquid crystal display device. It is to provide a technology that becomes possible.
The above objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
That is, the present invention relates to a liquid crystal display element having a plurality of pixels and a plurality of video signal lines for applying gradation voltages corresponding to display data to the plurality of pixels, and corresponding to the display data for each of the video signal lines. And a video signal line driving unit that supplies a gradation voltage to be supplied. The video line driving unit includes a semiconductor integrated circuit device, and the semiconductor integrated circuit device includes, for example, the semiconductor integrated circuit device. A first output terminal portion provided in a longitudinal direction of the semiconductor integrated circuit device at a central portion in a short direction of the circuit device; and both sides of the first output terminal portion in the short direction of the semiconductor integrated circuit device. And a pair of output circuit units for generating gradation voltages to be supplied to the video signal lines.

  According to another aspect of the invention, there is provided a liquid crystal display element having a plurality of pixels and a plurality of video signal lines for applying gradation voltages corresponding to display data to the plurality of pixels, and the display data corresponding to the video signal lines. And a video signal line driving unit that supplies a gradation voltage to be supplied. The video line driving unit includes a plurality of semiconductor integrated circuit devices, and each of the semiconductor integrated circuit devices includes the semiconductor An input circuit portion provided in the short direction of the integrated circuit device; and a first output terminal portion provided in the longitudinal direction of the semiconductor integrated circuit device on both sides of the input circuit portion in the longitudinal direction of the semiconductor integrated circuit device; And a pair of output circuit portions that are provided on both sides of the first output terminal portion in the short direction of the semiconductor integrated circuit device and generate gradation voltages to be supplied to the video signal lines. To do.

In a preferred embodiment of the present invention, the second output provided at least along the peripheral portions of the two short sides of the semiconductor integrated circuit device in a region other than the first output terminal portion and the output circuit portion. It has a terminal part.
In a preferred embodiment of the present invention, the pair of output circuit units includes a positive output circuit unit that generates a positive gradation voltage and a negative output circuit unit that generates a negative gradation voltage. It is characterized by being provided alternately.
In a preferred embodiment of the present invention, one output circuit unit of the pair of output circuit units is provided with a positive output circuit unit that generates a positive gradation voltage, and the pair of output circuit units The other output circuit section is provided with a negative output circuit section for generating a negative gradation voltage.
In a preferred embodiment of the present invention, the output circuit section includes a buffer circuit, a decoder circuit, a data latch section, and a shift register circuit, and the buffer circuit, the decoder circuit, the data latch section, and the shift circuit The register circuit is arranged in the order of the buffer circuit, the decoder circuit, the data latch unit, and the shift register circuit in the short direction of the semiconductor integrated circuit from the first output terminal unit.

  According to another aspect of the invention, there is provided a liquid crystal display element having a plurality of pixels and a plurality of video signal lines for applying gradation voltages corresponding to display data to the plurality of pixels, and the display data corresponding to the video signal lines. And a video signal line driving unit that supplies a gradation voltage to be supplied. The video line driving unit includes a plurality of semiconductor integrated circuit devices, and each of the semiconductor integrated circuit devices includes the semiconductor An input circuit portion provided in the short direction of the integrated circuit device; a plurality of output terminal portions provided in the longitudinal direction of the semiconductor integrated circuit device on both sides of the input circuit portion in the longitudinal direction of the semiconductor integrated circuit device; For each of the output terminal units, a pair of output circuit units that are provided on both sides of the output terminal unit in the short direction of the semiconductor integrated circuit device and generate gradation voltages to be supplied to the video signal lines, Features having To.

  According to another aspect of the invention, there is provided a liquid crystal display element having a plurality of pixels and a plurality of video signal lines for applying gradation voltages corresponding to display data to the plurality of pixels, and the display data corresponding to the video signal lines. A liquid crystal display device including a video signal line driving means for supplying a gradation voltage to be provided, wherein the video line driving means is mounted on the film substrate on which a plurality of wiring layers are formed, and the film substrate. A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device has a plurality of bump electrodes provided in a longitudinal direction of the semiconductor integrated circuit device in a region other than a peripheral portion of the semiconductor integrated circuit device; A part of the wiring layer is provided with one end connected to each bump electrode of the semiconductor integrated circuit device, extended from the one end to the periphery of the film substrate, and includes the one end Min and being covered by said semiconductor integrated circuit device.

According to another aspect of the present invention, there is provided a liquid crystal display element having a pair of substrates and a liquid crystal sandwiched between the pair of substrates, a plurality of pixels, and a gradation voltage corresponding to display data in the plurality of pixels of the liquid crystal layer. A liquid crystal display device comprising: a liquid crystal display element having a plurality of video signal lines for applying a voltage; and video signal line driving means for supplying a gradation voltage corresponding to display data to each video signal line, The video line driving means includes a semiconductor integrated circuit device mounted on one of the pair of substrates, and the semiconductor integrated circuit device is located in a region other than a peripheral portion of the semiconductor integrated circuit device. A plurality of bump electrodes provided in a longitudinal direction of the device, and a part of the video signal line formed on the one substrate has a terminal portion connected to each bump electrode of the semiconductor integrated circuit device; Area including terminal There characterized in that it is covered by the semiconductor integrated circuit device.
In a preferred embodiment of the present invention, the plurality of bump electrodes are formed in a plurality of rows in the longitudinal direction of the semiconductor integrated circuit device.
Also, in a preferred embodiment of the present invention, the bump electrodes in a part of the plurality of rows have a length in the longitudinal direction of the semiconductor integrated circuit device, and the wiring layer of the film substrate is extended from the row. The bump electrodes in a row in the direction are longer than the length in the longitudinal direction of the semiconductor integrated circuit device.

According to another aspect of the invention, there is provided a liquid crystal display element having a plurality of pixels and a plurality of video signal lines for applying gradation voltages corresponding to display data to the plurality of pixels, and the display data corresponding to the video signal lines. A liquid crystal display device including a video signal line driving means for supplying a gradation voltage to be provided, wherein the video line driving means is mounted on the film substrate on which a plurality of wiring layers are formed, and the film substrate. A semiconductor integrated circuit device, the semiconductor integrated circuit device has a plurality of bump electrodes, and some of the plurality of bump electrodes are electrically connected to each other by a wiring layer provided on the film substrate; It is characterized by.
According to another aspect of the invention, there is provided a liquid crystal display element having a plurality of pixels and a plurality of video signal lines for applying gradation voltages corresponding to display data to the plurality of pixels, and the display data corresponding to the video signal lines. A liquid crystal display device including a video signal line driving means for supplying a gradation voltage to be provided, wherein the video line driving means is mounted on the film substrate on which a plurality of wiring layers are formed, and the film substrate. A semiconductor integrated circuit device, the semiconductor integrated circuit device has a plurality of bump electrodes, a part of the plurality of bump electrodes are electrically connected to each other by a wiring layer provided on the film substrate; An input signal from the outside is applied to the wiring layer connecting the bump electrodes.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
(1) According to the present invention, the cost of the liquid crystal display device can be reduced.
(2) According to the present invention, inspection of a liquid crystal display device can be simplified.
(3) According to the present invention, it is possible to prevent a voltage drop due to a wiring layer inside the semiconductor integrated circuit device.

It is a block diagram which shows schematic structure of the liquid crystal display module of the TFT system to which this invention is applied. It is a figure which shows the equivalent circuit of an example of the liquid crystal display panel shown in FIG. It is a figure which shows the equivalent circuit of the other example of the liquid crystal display panel shown in FIG. It is a figure for demonstrating the polarity of the liquid-crystal drive voltage output to a drain signal line (D) from a drain driver, when a dot inversion method is used as a drive method of a liquid crystal display module. FIG. 2 is a block diagram illustrating a schematic configuration of an example of a drain driver illustrated in FIG. 1. FIG. 6 is a block diagram for specifically explaining the configuration of an example of the drain driver shown in FIG. 5. FIG. 6 is a block diagram for more specifically explaining the configuration of another example of the drain driver shown in FIG. 5. FIG. 8 is a circuit diagram illustrating a schematic configuration of an example of a high-voltage decoder circuit and a low-voltage decoder circuit illustrated in FIGS. 6 and 7. FIG. 8 is a circuit diagram illustrating a schematic configuration of an example of a high-voltage amplifier circuit and a low-voltage amplifier circuit illustrated in FIGS. 6 and 7. FIG. 10 is a circuit diagram showing a differential amplifier circuit used in the operational amplifier of the low voltage amplifier circuit shown in FIG. 9. FIG. 10 is a circuit diagram showing a differential amplifier circuit used in the operational amplifier of the high voltage amplifier circuit shown in FIG. 9. FIG. 8 is a circuit diagram illustrating a circuit configuration of a selection circuit as an example of the output selection circuit illustrated in FIG. 7. It is a figure which shows the layout of the internal circuit of the semiconductor chip (IC) which comprises the drain driver of Example 1 of this invention. It is a figure which shows the layout of the wiring layer (COFA) on the film board | substrate of Example 1 of this invention. It is a figure which shows the layout of the internal circuit of the semiconductor chip (IC) which comprises the drain driver of Example 2 of this invention. It is a schematic diagram which shows the structure of the conventional decoder circuit in a semiconductor chip (IC). It is a schematic diagram which shows the structure of the decoder circuit of Example 2 of this invention in a semiconductor chip (IC). It is a figure which shows the layout of the internal circuit of the semiconductor chip (IC) which comprises the drain driver of Example 3 of this invention. It is a figure which shows the layout of the wiring layer (COFA) on the film board | substrate of Example 3 of this invention. It is a figure for demonstrating arrangement | positioning of the output terminal (BUMP1) of the semiconductor chip (IC) which comprises the drain driver of Example 4 of this invention. It is a figure for demonstrating a part of terminal (BUMP) of the semiconductor chip (IC) which comprises the drain driver of Example 5 of this invention, and a part of wiring layer (COFB) formed in the film substrate. It is a figure for demonstrating the modification of FIG. It is a figure for demonstrating the modification of FIG. It is a block diagram which shows schematic structure of an example of the conventional TFT liquid crystal display module. It is a figure which shows the conventional film board | substrate with which the drain driver was mounted. It is a figure which shows the terminal part structure of the conventional drain driver.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
In all the drawings for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof is omitted. Also, the following examples are not intended to limit the interpretation of the scope of the claims of the present invention.
[Example 1]
<Basic configuration of display device to which the present invention is applied>
FIG. 1 is a block diagram showing a schematic configuration of a TFT liquid crystal display module to which the present invention is applied.
The liquid crystal display module (LCM) shown in FIG. 1 has a drain driver 130 disposed on one side of the long side of the liquid crystal display panel (TFT-LCD) 10 and a gate on one side of the short side of the liquid crystal display panel 10. A driver 140 is arranged.
The liquid crystal display panel 10 includes, for example, 1600 × 800 × 3 pixels.
Here, one pixel means one pixel (Pix) of red (R), green (G), and blue (B).

Red (R), green (G), and blue (B) display data (video signal), clock signal, display timing signal, and sync signal (horizontal sync signal, vertical) output from the host computer such as a personal computer A control signal including a synchronization signal is input to the display control device (TFT controller) 110 via the interface connector.
In this embodiment, the interface unit 100 is shown in the TFT controller substrate 301 shown in FIG. 24, the drain driver 130 is shown in the drain driver substrate 302 shown in FIG. 24, and the gate driver 140 is shown in FIG. Mounted on the gate driver substrate 303.
Here, the semiconductor chip (IC) constituting the drain driver 130 and the gate driver 140 is mounted on the film substrate 310 by a so-called tape carrier (Tape Carrier Package) method or a chip on film (Chip On Film) method. .
Note that the semiconductor chip (IC) described above may be directly mounted on one transparent substrate of the liquid crystal display panel 10 by a chip on glass method.

<Configuration of Liquid Crystal Display Panel 10 Shown in FIG. 1>
FIG. 2 is a diagram showing an equivalent circuit of an example of the liquid crystal display panel 10 shown in FIG.
As shown in FIG. 2, the liquid crystal display panel 10 has a plurality of pixels formed in a matrix.
Each pixel includes two adjacent signal lines (drain signal line (D) or gate signal line (G)) and two adjacent signal lines (gate signal line (G) or drain signal line (D)). It is arranged in the intersection area.
Each pixel has a thin film transistor (TFT1, TFT2), and the source electrode of the thin film transistor (TFT1, TFT2) of each pixel is connected to the pixel electrode (ITO1).
In addition, since the liquid crystal layer is provided between the pixel electrode (ITO1) and the common electrode (ITO2), the liquid crystal capacitance (CLC) is equivalent between the pixel electrode (ITO1) and the common electrode (ITO2). Connected.
Further, an additional capacitor (CADD) is connected between the source electrode of the thin film transistor (TFT1, TFT2) and the previous gate signal line (G).
FIG. 3 is a diagram showing an equivalent circuit of another example of the liquid crystal display panel 10 shown in FIG.
In the example shown in FIG. 2, an additional capacitor (CADD) is formed between the previous gate signal line (G) and the source electrode, but in the equivalent circuit of the example shown in FIG. 3, the common signal line (CN) A storage capacitor (CSTG) is formed between the source electrode and the source electrode.

The present invention can be applied to both. In the former method, the gate signal line (G) pulse in the former stage jumps into the pixel electrode (ITO1) via the additional capacitor (CADD), whereas the latter method. Then, since there is no dive, better display is possible.
2 and 3 show an equivalent circuit of a vertical electric field liquid crystal display panel. In FIGS. 2 and 3, AR is a display region.
2 and 3 are circuit diagrams, which are drawn corresponding to an actual geometric arrangement.
In the liquid crystal display panel 10 shown in FIGS. 2 and 3, the drain electrodes of the thin film transistors (TFT1, TFT2) of the pixels arranged in the column direction are connected to the drain signal lines (D), respectively, and the drain signal lines (D ) Is connected to a drain driver 130 for applying a gradation voltage to the liquid crystal of each pixel in the column direction.
In addition, the gate electrodes of the thin film transistors (TFT1, TFT2) in each pixel arranged in the row direction are connected to the gate signal line (G), respectively, and each gate signal line (G) has one horizontal scanning time in the row direction. It is connected to a gate driver 140 that supplies a scanning drive voltage (positive bias voltage or negative bias voltage) to the gate electrode of the thin film transistor (TFT1, TFT2) of each pixel.

<Configuration and Operation Overview of Interface Unit 100 shown in FIG. 1>
The interface unit 100 illustrated in FIG. 1 includes a display control device 110 and a power supply circuit 120.
The display control device 110 is composed of one semiconductor integrated circuit (LSI), and each display control signal and display data of a clock signal, a display timing signal, a horizontal synchronization signal, and a vertical synchronization signal transmitted from the computer main body side. The drain driver 130 and the gate driver 140 are controlled and driven based on the data (R, G, B).
When the display timing signal is input, the display control device 110 determines that this is a display start position, and outputs a start pulse (display data capture start signal) to the first drain driver 130 via the signal line 135. In addition, the received simple one-column display data is output to the drain driver 130 via the display data bus line 133.
At that time, the display control device 110 displays a display data latch clock (CL2) (hereinafter simply referred to as clock (CL2)) which is a display control signal for latching display data in the data latch circuit of each drain driver 130. ) Is output via the signal line 131.
Also in this embodiment, as shown in FIG. 24 described above, control signals and display data from the display control device 110 are input to each drain driver 130 via the TFT controller substrate 301 and the drain driver substrate 302. Is done.

The display data from the main computer is, for example, 6 bits and transferred in units of one pixel, that is, red (R), green (G), and blue (B) as one set. The
Further, the latch operation of the data latch circuit in the first drain driver 130 is controlled by the start pulse input to the first drain driver 130.
When the latch operation of the data latch circuit in the first drain driver 130 is completed, a start pulse is input from the first drain driver 130 to the second drain driver 130, and the second drain driver 130 The latch operation of the data latch circuit is controlled.
Similarly, the latch operation of the data latch circuit in each drain driver 130 is controlled to prevent erroneous display data from being written to the data latch circuit.

The display control device 110 determines that the display data for one horizontal line has ended when the input of the display timing signal ends or when a predetermined fixed time has passed after the display timing signal is input, and each drain driver 130 Output timing control clock (CL1) (hereinafter simply referred to as clock (CL1)), which is a display control signal for outputting the display data stored in the data latch circuit in FIG. 2 to the drain signal line (D) of the liquid crystal display panel 10. .) Is output to each drain driver 130 via the signal line 132.
When the first display timing signal is input after the vertical synchronization signal is input, the display control device 110 determines that the first display timing signal is the first display line and transmits the frame to the gate driver 140 via the signal line 142. A start instruction signal is output.
Further, the display control device 110 sets the signal line 141 so as to sequentially apply a positive bias voltage to each gate signal line (G) of the liquid crystal display panel 10 every horizontal scanning time based on the horizontal synchronization signal. The clock (CL3), which is a shift clock of one horizontal scanning time period, is output to the gate driver 140.
As a result, the plurality of thin film transistors (TFT1, TFT2) connected to the gate signal lines (G) of the liquid crystal display panel 10 are conducted for one horizontal scanning time.
With the above operation, an image is displayed on the liquid crystal display panel 10.

<Configuration of Power Supply Circuit 120 shown in FIG. 1>
The power supply circuit 120 illustrated in FIG. 1 includes a positive voltage generation circuit 121, a negative voltage generation circuit 122, a common electrode (counter electrode) voltage generation circuit 123, and a gate electrode voltage generation circuit 124.
Each of the positive voltage generation circuit 121 and the negative voltage generation circuit 122 includes a series resistance voltage dividing circuit. The positive voltage generation circuit 121 generates a positive five-value gradation reference voltage (V "0 to V" 4). The negative voltage generation circuit 122 outputs negative five-value gradation reference voltages (V "5 to V" 9).
The positive polarity reference voltage (V ″ 0 to V ″ 4) and the negative polarity reference voltage (V ″ 5 to V ″ 9) are supplied to each drain driver 130.
Further, the polarity inversion signal (AC signal; M) from the display control device 110 is also supplied to each drain driver 130 via the signal line 134.
The common electrode voltage generation circuit 123 is a drive voltage to be applied to the common electrode (ITO2), and the gate electrode voltage generation circuit 124 is a drive voltage to be applied to the gate electrodes of the thin film transistors (TFT1 and TFT2) (positive bias voltage and negative bias voltage). ) Is generated.

<AC drive method of liquid crystal display module shown in FIG. 1>
In general, when the same voltage (DC voltage) is applied to the liquid crystal layer for a long time, the inclination of the liquid crystal layer is fixed, resulting in an afterimage phenomenon and shortening the life of the liquid crystal layer.
In order to prevent this, in the liquid crystal display module, the voltage applied to the liquid crystal layer is changed to AC every certain time, that is, the voltage applied to the pixel electrode with reference to the voltage applied to the common electrode, It is made to change to the positive voltage side / negative voltage side for every fixed time.
As a driving method for applying an AC voltage to the liquid crystal layer, two methods, a common symmetry method and a common inversion method, are known.
The common inversion method is a method of alternately inverting the voltage applied to the common electrode and the voltage applied to the pixel electrode to positive and negative.
The common symmetry method is a method in which the voltage applied to the common electrode is constant and the voltage applied to the pixel electrode is alternately inverted to positive and negative with reference to the voltage applied to the common electrode. .
In the common symmetry method, the amplitude of the voltage applied to the pixel electrode (ITO1) is twice that of the common inversion method, and a low breakdown voltage driver cannot be used unless a liquid crystal with a low threshold voltage is developed. Although there are drawbacks, the dot inversion method or the N-line inversion method, which is excellent in terms of low power consumption and display quality, can be used.

Hereinafter, the dot inversion method will be described.
FIG. 4 shows a case where the liquid crystal display module is applied to the liquid crystal driving voltage (that is, the pixel electrode (ITO1)) output from the drain driver 130 to the drain signal line (D) when the dot inversion method is used. It is a figure for demonstrating the polarity of (gradation voltage).
When the dot inversion method is used as the driving method of the liquid crystal display module, as shown in FIG. 4, for example, in the odd line of the odd frame, the drain driver 130 supplies the common to the odd drain signal line (D). The liquid crystal drive voltage (shown by ● in FIG. 4) is negative with respect to the liquid crystal drive voltage (VCOM) applied to the electrode (ITO2), and the common electrode (ITO2 is applied to the even-numbered drain signal line (D). ) Is applied to the liquid crystal drive voltage (VCOM) applied to () in FIG.
Further, in the even-numbered line of the odd-numbered frame, the positive polarity liquid crystal driving voltage is supplied from the drain driver 130 to the odd-numbered drain signal line (D), and the negative-polarity liquid crystal driving voltage is applied to the even-numbered drain signal line (D). Is applied.

Further, the polarity of each line is inverted for each frame, that is, as shown in FIG. 4, in the odd lines of the even frames, the positive polarity liquid crystal drive is applied from the drain driver 130 to the odd drain signal lines (D). A voltage and a negative liquid crystal driving voltage are applied to the even-numbered drain signal lines (D).
Further, in the even-numbered line of the even-numbered frame, a negative liquid crystal driving voltage is applied from the drain driver 130 to the odd-numbered drain signal line (D), and a positive-polarity liquid crystal driving voltage is applied to the even-numbered drain signal line (D). Is applied.
By using this dot inversion method, the voltage applied to the adjacent drain signal line (D) has a reverse polarity, so that the current flowing through the gate electrode of the common electrode (ITO2) or thin film transistor (TFT1, TFT2) is adjacent. Compete with each other and reduce power consumption.
Further, since the current flowing through the common electrode (ITO2) is small and the voltage drop does not increase, the voltage level of the common electrode (ITO2) is stabilized, and the deterioration of display quality can be minimized.

<Configuration of the drain driver 130 shown in FIG. 1>
FIG. 5 is a block diagram showing a schematic configuration of an example of the drain driver 130 shown in FIG.
The drain driver 130 is composed of one semiconductor integrated circuit (LSI).
In the figure, the gradation voltage generation circuit 151 is based on the positive five-value gradation reference voltage (V "0 to V" 4) input from the positive voltage generation circuit 121 and has 64 positive gradations. And 64 negative gradation voltages with negative polarity based on the negative five-value gradation reference voltages (V "5 to V" 9) input from the negative voltage generation circuit 122. , And 64 grayscale voltages having positive and negative polarities are output to the decoder circuit 157 via the voltage bus line.
The shift register circuit 153 generates a data capture signal based on the shift clock that is output from the clock control circuit 152 and is synchronized with the clock (CL2), and outputs the data capture signal to the latch circuit (1) 155.

Display data input from the display control device 110 is temporarily latched by the input latch circuit 154.
The input latch circuit 154 latches display data based on the clock from the clock control circuit 152.
The latch circuit (1) 155 is for each color output from the input latch circuit 154 in synchronization with the clock (CL2) input from the display control device 110 based on the data fetch signal output from the shift register circuit 153. 6-bit display data is latched by the number of outputs.
The latch circuit (2) 156 latches the display data in the latch circuit (1) 155 in accordance with the clock (CL1) input from the display control device 110.
The display data fetched by the latch circuit (2) 156 is inputted to the decoder circuit 157 via the internal level shift circuit.
The decoder circuit 157 generates one gradation voltage (one gradation out of 64 gradations) corresponding to display data from a gradation gradation voltage having a positive polarity of 64 gradations or a gradation gradation voltage having a negative polarity of 64 gradations. Voltage) is selected and output to the buffer circuit 158.
The buffer circuit 158 amplifies (current amplifies) the input gradation voltage and outputs it to each drain signal line (D).

FIG. 6 is a block diagram for more specifically explaining the configuration of an example of the drain driver 130 shown in FIG.
5, reference numeral 153 denotes a shift register circuit shown in FIG. 5, 157 denotes a decoder circuit shown in FIG. 5, and a data latch unit 262 includes a latch circuit (1) 155 and a latch circuit (2) shown in FIG. ) 156, and the level shift circuit 263 represents a level shift circuit inside the latch circuit (2) shown in FIG.
Further, the amplifier circuit 264 and the output selection circuit 265 for switching the output of the amplifier circuit 264 constitute the buffer circuit 158 shown in FIG.
Here, the display data selection circuit 261 and the output selection circuit 265 are controlled based on the polarity inversion signal (M).
Y1, Y2, Y3, Y4, Y5, and Y6 indicate the first, second, third, fourth, fifth, and sixth drain signal lines (D), respectively. .
In the drain driver 130 shown in FIG. 6, the display data selection circuit 261 switches the data capturing signal input to the data latch unit 262 (more specifically, the latch circuit (1) 155 shown in FIG. 5), and continuously Display data to be input is input to the adjacent data latch unit 262.

The decoder circuit 157 selects each of the data latch units 262 (more specifically, the latch circuit (2) 156 shown in FIG. 5) from the positive gradation voltages of 64 gradations supplied from the gradation voltage generation circuit 151. A high-voltage decoder circuit 251 that selects a positive gradation voltage corresponding to display data output from the terminal and a negative gradation voltage of 64 gradations supplied from the gradation voltage generation circuit 151. , And a low voltage decoder circuit 252 for selecting a negative gradation voltage corresponding to display data output from each data latch unit 262.
The high voltage decoder circuit 251 and the low voltage decoder circuit 252 are provided for each adjacent data latch unit 262.
The amplifier circuit 264 includes a high voltage amplifier circuit 271 and a low voltage amplifier circuit 272.
The positive voltage gradation voltage generated by the high voltage decoder circuit 251 is input to the high voltage amplifier circuit 271, and the high voltage amplifier circuit 271 outputs the positive gradation voltage.
The low voltage amplifier circuit 272 receives the negative gradation voltage generated by the low voltage decoder circuit 252, and the low voltage amplifier circuit 272 outputs the negative gradation voltage.

  In the dot inversion method, the gradation voltages of continuous display data have opposite polarities, and the arrangement of the amplifier circuits 264 is as follows: high voltage amplifier circuit 271 → low voltage amplifier circuit 272 → high voltage amplifier circuit 271 → low. Since the voltage amplifier circuit 272 is used, the display data selection circuit 261 switches the display data input to the data latch unit 262, and the continuous display data is alternately input to the adjacent data latch units 262. A drain signal line (D) for switching the output voltage output from the high voltage amplifier circuit 271 or the low voltage amplifier circuit 272 by the output selection circuit 265 and outputting the gradation voltage of continuous display data, for example, Each drain is output to the first drain signal line (Y1) and the second drain signal line (Y2). It is possible to output a positive polarity or negative polarity gray scale voltages to the signal lines (D).

FIG. 7 is a block diagram for more specifically explaining the configuration of another example of the drain driver 130 shown in FIG.
In the example shown in FIG. 7, the display data selection circuit 261 switches display data input to the data latch unit 262 by utilizing the fact that the gradation voltages of display data of adjacent colors have opposite polarities. The display data for each color is input to the adjacent data latch unit 262, and the output voltage output from the high voltage amplifier circuit 271 or the low voltage amplifier circuit 272 is switched by the output selection circuit 265 accordingly, Are output to the drain signal line (D) from which the grayscale voltage is output, for example, the first drain signal line (Y1) and the fourth drain signal line (Y4).
In the example shown in FIG. 6 and FIG. 7, the chip size of the semiconductor chip (IC) is reduced by reducing the number of low voltage circuits and the high voltage circuits to the number of terminals, not the total number of output terminals. I am trying.

FIG. 8 is a circuit diagram showing a schematic configuration of an example of the high voltage decoder circuit 251 and the low voltage decoder circuit 252 shown in FIGS.
In the example shown in FIG. 8, the high-voltage decoder circuit 251 or the low-voltage decoder circuit 252 shown in FIG. 6 includes a transistor string (TRP2, TRP3) in which an enhancement MOS transistor and a depletion MOS transistor are connected in series.
The high voltage amplifier circuit 271 and the low voltage amplifier circuit 272 shown in FIGS. 6 and 7 include, for example, an inverting input terminal (BUMP) (−) and an output terminal (of an operational amplifier (OP)) as shown in FIG. And a non-inverting input terminal (BUMP) (+) as an input terminal (BUMP).
Here, the operational amplifier (OP) used in the low-voltage amplifier circuit 272 is constituted by, for example, a differential amplifier circuit as shown in FIG. 10, and further, the operational amplifier (OP) used in the high-voltage amplifier circuit 271. ) Is constituted by, for example, a differential amplifier circuit as shown in FIG.

FIG. 12 is a circuit diagram showing a circuit configuration of one example of the output selection circuit 265 shown in FIG.
As shown in FIG. 7, one selection circuit of the output selection circuit 265 shown in FIG. 7 includes a PMOS transistor (PM1) connected between the high voltage amplifier circuit 271 and the nth drain signal (Yn), The PMOS transistor (PM2) connected between the high voltage amplifier circuit 271 and the (n + 3) th drain signal (Yn + 3), and the low voltage amplifier circuit 272 and the (n + 3) th drain signal (Yn + 3). An NMOS transistor (NM1) connected in between, and an NMOS transistor (NM2) connected between the low voltage amplifier circuit 272 and the nth drain signal (Yn).
The output of the NOR circuit (NOR1) inverted by the inverter (INV) is applied to the gate electrode of the PMOS transistor (PM1), and the NOR circuit inverted by the inverter (INV) is applied to the gate electrode of the PMOS transistor (PM2). The output of the circuit (NOR2) is level-shifted by the level shift circuit (LS) and input.

Similarly, the output of the NAND circuit (NAND2) inverted by the inverter (INV) is applied to the gate electrode of the NMOS transistor (NM1), and the output of the NAND transistor (NM2) is inverted by the inverter (INV). The output of the NAND circuit (NAND1) is level-shifted by the level shift circuit (LS) and input.
Here, the polarity inversion signal (M) is supplied to the NAND circuit (NAND1) and the NOR circuit (NOR1), and the polarity inversion signal inverted by the inverter (INV) is supplied to the NAND circuit (NAND2) and the NOR circuit (NOR2). (M) is input.
The NAND circuit (NAND1, NAND2) receives the output enable signal (ENB), and the NOR circuit (NOR1, NOR2) receives the output enable signal (ENB) inverted by the inverter (INV).
Table 1 shows the truth table of the NAND circuit (NAND1, NAND2) and the NOR circuit (NOR1, NOR2), and the on / off states of the MOS transistors (PM1, PM2, NM1, NM2) at that time.

表１から分かるように、出力イネーブル信号（ＥＮＢ）がＬｏｗレベル（以下、Ｌレベル）の時に、ナンド回路（ＮＡＮＤ１，ＮＡＮＤ２）はＨｉｇｈレベル（以下、Ｈレベル）、ノア回路（ＮＯＲ１，ＮＯＲ２）はＬレベルとなり、各ＭＯＳトランジスタ（ＰＭ１，ＰＭ２，ＮＭ１，ＮＭ２）はオフ状態となる。
走査ラインの切り替わり時には、高電圧用アンプ回路２７１と低電圧用アンプ回路２７２とも不安定の状態にある。
この出力イネーブル信号（ＥＮＢ）は、走査ラインの切り替わり期間内に、各アンプ回路（２７１，２７２）の出力が、各ドレイン信号線（Ｄ）に出力されるのを防止するために設けられている。
なお、本実施例では、この出力イネーブル信号（ＥＮＢ）として、クロック（ＣＬ１）の反転信号を使用しているが、クロック（ＣＬ２）をカウントする等して内部で生成することも可能である。

As can be seen from Table 1, when the output enable signal (ENB) is at the low level (hereinafter, L level), the NAND circuit (NAND1, NAND2) is at the high level (hereinafter, H level), and the NOR circuit (NOR1, NOR2) is at It becomes L level and each MOS transistor (PM1, PM2, NM1, NM2) is turned off.
At the time of scanning line switching, both the high voltage amplifier circuit 271 and the low voltage amplifier circuit 272 are in an unstable state.
This output enable signal (ENB) is provided to prevent the output of each amplifier circuit (271, 272) from being output to each drain signal line (D) during the scanning line switching period. .
In this embodiment, an inverted signal of the clock (CL1) is used as the output enable signal (ENB), but it can also be generated internally by counting the clock (CL2).

As can be seen from Table 1, when the output enable signal (ENB) is at the H level, each NAND circuit (NAND1, NAND2) is at the H level or the L level according to the H level or L level of the polarity inversion signal (M). The level and each NOR circuit (NOR1) becomes H level or L level.
As a result, the PMOS transistor (PM1) and the NMOS transistor (NM1) are turned off or on, the PMOS transistor (PM2) and the NMOS transistor (NM2) are turned on or off, and the output of the high voltage amplifier circuit 271 is the drain signal line (Yn + 3). The output of the low voltage amplifier circuit 272 is the drain signal line (Yn), the output of the high voltage amplifier circuit 271 is the drain signal line (Yn), and the output of the low voltage amplifier circuit 272 is the drain signal line. Output to (Yn + 3).

<Characteristic configuration of the liquid crystal display module of this embodiment>
FIG. 13 is a diagram showing a layout of an internal circuit of a semiconductor chip (IC) constituting the drain driver 130 of this embodiment.
As shown in the figure, in this embodiment, an output circuit block composed of a shift register circuit 153, a data latch unit 262, a decoder circuit 157, and a buffer circuit 158 is divided into a short number of semiconductor chips (ICs) by the number of output terminals. It is characterized by being arranged in two stages in the direction.
As shown in FIG. 13, an output terminal (bump electrode) region (a) 20 is provided at the center in the short direction of the semiconductor chip (IC), and the output circuit block arranged in two stages is as follows. From the output terminal area (a) 20, the buffer circuit 158, the decoder circuit 157, the data latch unit 262, and the shift register circuit 153 are provided in this order.
In addition, an input circuit / wiring region 23 is provided in the central portion of the semiconductor chip (IC) in the longitudinal direction so that display data, a clock, and the like are supplied to an output circuit block arranged in two stages. Yes.
As described above, in this embodiment, by arranging the output terminal portions having the same shape in the adjacent region (output terminal region (a)), the useless space can be reduced and the area of the output terminal portion can be reduced. it can. Reference numeral 22 denotes an input terminal area.

In this embodiment, the shift register circuit 153 is arranged for each stage because the output circuit blocks are arranged in two stages.
Therefore, as compared with the drain driver 130 shown in FIGS. 6 and 7, the shift driver circuit formation region is increased in the drain driver 130 of this embodiment.
However, the shift register circuit 153 is a low-voltage circuit that can be manufactured by a low withstand voltage process, and because the circuit scale is small, an increase in area is negligible even when the circuit is doubled.
As described above, in this embodiment, the grayscale voltage output circuit portion occupying most of the semiconductor chip (IC) constituting the drain driver 130 is divided into two, so that the longitudinal direction of the chip of the semiconductor chip (IC) The grayscale voltage output circuit shown in FIG. 26 can be halved (1/2 times) in length in the (lateral direction) as compared to a configuration in which the grayscale voltage output circuits shown in FIG.
However, in the present embodiment, the length of the semiconductor chip (IC) in the short direction is approximately equal to the configuration in which the grayscale voltage output circuits shown in FIG. 26 are arranged in a line in the longitudinal direction of the chip. Doubled.
In other words, in this embodiment, the external shape of the semiconductor chip (IC) constituting the drain driver 130 is not a long and narrow plate shape, but closer to a square.

Therefore, in this embodiment, the number of chips that can be obtained from a single wafer can be increased as compared to a conventional elongated plate-like one, and so-called step-and-repeat exposure is performed on one semiconductor wafer surface. Therefore, when forming a semiconductor chip (IC), an inexpensive device can be used, so that the cost of the semiconductor chip (IC) can be reduced.
In this embodiment, the arrangement of the output terminals (BUMP1) is determined by the semiconductor chip (IC) size, the number of output terminals, and the distance between the output terminals. When the semiconductor chip (IC) size is large, the buffer circuit Arrangement in the output terminal region (a) 20 in FIG. 13 closest to 158 has the smallest area of the semiconductor chip (IC).
When the semiconductor chip (IC) size is small, the output terminal region (b) 21 may be used.

In this embodiment, since the output terminal (BUMP1) is arranged near the center of the semiconductor chip (IC), when the semiconductor chip (IC) is mounted on the film substrate by the chip-on-film method, the semiconductor The wiring layer (COFA) on the film substrate for connecting the output terminal (BUMP1) of the chip (IC) and the drain line (D) of the liquid crystal display panel 10 is partially overlaid with the semiconductor chip (IC). Wrap.
Therefore, in this embodiment, the wiring layer (COFA) on the film substrate has a layout as shown in FIG. 14, so that the wiring layer (COFA) of the film substrate 310 and the semiconductor chip (see FIG. 13). The output terminal (BUMP1) of the semiconductor chip (IC) and the drain line (D) of the liquid crystal display panel 10 can be electrically connected without contact with the output terminal (BUMP1) of the IC.
The provision of a terminal region at the center of a semiconductor chip is known for semiconductor memories and the like. The reason for providing a terminal region at the center of this semiconductor memory is mainly to reduce wiring delay in the chip. Yes, unlike the present invention, it does not reduce the cost of the semiconductor chip.

[Example 2]
FIG. 15 is a diagram showing an internal circuit layout of a semiconductor chip (IC) constituting the drain driver 130 according to the second embodiment of the present invention.
In the present embodiment, each of the output circuit blocks arranged in the two stages described in the first embodiment is generated with an output circuit block that outputs a positive gradation voltage and a negative gradation voltage. The output circuit block is separated.
That is, the decoder circuit 157 is the high voltage decoder circuit 251 and the amplifier circuit 264 is the high voltage amplifier circuit 271, which corresponds to the upper output circuit block in FIG. The decoder circuit 157 is a low-voltage decoder circuit 252 and the amplifier circuit 264 is a low-voltage amplifier circuit 272 (corresponding to the lower output circuit block in FIG. 16). , And LV)).
Note that the shift register 153 operates based on the shift clock generated by the shift clock generation circuit 254 in the clock control circuit, and the shift direction of the shift register circuit 153 is indicated by a dotted arrow in FIG.
In FIG. 15, the numbers appended to the decoder circuit portion correspond to the output terminal (BUMP1), and the numbers in FIG. 15 correspond to the level (H level or L level) of the polarity inversion signal (M). For example, No. 1 is no. 2, no. 2 is No.2. 1 is replaced.
For this reason, in this embodiment, the shift register circuit 153 needs to output a data capturing signal once every three output terminals (BUMP1).
In the above-described embodiment, the shift register circuit 153 outputs a data capturing signal once every six output terminals (BUMP1).

In this embodiment, the circuit area is reduced in the decoder circuit 157 having 64 gradations × 2 = 128 voltage bus lines and the data latch unit 262 having 6 bits × 6 = 36 display data buses. Can do.
FIG. 16 is a schematic diagram showing the structure of a conventional decoder circuit 157 in a semiconductor chip (IC).
As shown in FIG. 16, in the related art, the decoder circuit 157 has a total of 128 aluminum wirings (hereinafter referred to as AL) of a 64 voltage bus line on the low voltage side and a 64 voltage bus line on the high voltage side. A switch element is arranged under 150.
Here, for example, focusing on the high voltage side (shown as high in the figure), only 64 of the 128 voltage bus lines are used for 64 gradations on the high voltage side, so the remaining The space for 64 on the low voltage side is a useless area if the size of the switch element is not a constraint. The same applies to the low voltage side, and the area at this time is (a × b).

FIG. 17 is a schematic diagram showing the structure of the decoder circuit 157 of this embodiment in the semiconductor chip (IC).
As shown in FIG. 17, the switch element of the high voltage decoder 271 is arranged under the high voltage side 64 gradation wiring, and the switch element of the low voltage decoder 272 is arranged under the low voltage side 64 gradation wiring. Is done.
Therefore, in this embodiment, there is no useless area unlike the conventional decoder circuit 157 shown in FIG.
In the current manufacturing process, the AL wiring 150 is often dominant with respect to the area, and the switch element can be sufficiently disposed under the AL wiring 150.
The area at this time is (a × b) / 2, which is half (1/2) of the conventional decoder circuit 157 shown in FIG.
Thus, in this embodiment, the circuit area can be halved even though the functions are the same.
In the data latch unit 262, the circuit area can be halved for the same reason, and therefore the area of the entire drain driver can be greatly reduced.

[Example 3]
FIG. 18 is a diagram showing a layout of an internal circuit of a semiconductor chip (IC) constituting the drain driver 130 according to the third embodiment of the present invention.
In this embodiment, the output circuit blocks described in the first embodiment are arranged in four stages.
Also in the present embodiment, by arranging the output terminals (BUMP1) having the same shape in the adjacent areas, it is possible to reduce a useless space and to reduce the area of the output terminal area 20.
However, in this embodiment, the area is increased by the decoder circuit 157 and the data latch unit 262 as compared with the two-stage configuration of the first embodiment described above, but the length in the longitudinal direction (lateral direction) is further shortened. be able to.
For this reason, as the number of output terminals increases, when a semiconductor chip (IC) is formed on the wafer by step-and-repeat exposure, it is possible to fit within the exposure range.

In this embodiment, since the output terminal (BUMP1) is arranged in two stages near the center of the semiconductor chip (IC), when the semiconductor chip (IC) is mounted on the film substrate by the chip-on-film method. The wiring layer (COFA) on the film substrate for connecting the output terminal (BUMP1) of the semiconductor chip (IC) and the drain line (D) of the liquid crystal display panel 10 is partially a semiconductor chip (IC ).
Therefore, in this embodiment, the wiring layer (COFA) on the film substrate has a layout as shown in FIG. 19, so that the wiring layer (COFA) and the semiconductor chip (COFA) of the film substrate 310 are shown in FIG. The output terminal (BUMP1) of the semiconductor chip (IC) and the drain line (D) of the liquid crystal display panel 10 can be electrically connected without contact with the terminal (BUMP1) of the IC.

[Example 4]
FIG. 20 is a diagram for explaining the arrangement of the output terminals (BUMP1) of the semiconductor chip (IC) constituting the drain driver 130 according to the fourth embodiment of the present invention.
As shown in the figure, in this embodiment, the output terminals (BUMP1) are formed in two rows, and these output terminals (BUMP1) are formed on a liquid crystal display panel by a wiring layer (COFA) formed on the film substrate 310. 10 drain lines (D) are electrically connected.
In this case, when the output terminals (BUMP1) are formed in a plurality of rows, the interval between the wiring layers (COFA) formed on the film substrate 310 is narrowed. The gap with BUMP1) becomes small, and there is a problem that the probability of occurrence of a short circuit failure becomes high.
Therefore, in the present embodiment, the second row terminal (BUMP1) in the row closer to the drawing direction of the wiring layer (COFA) of the film substrate 310 (that is, the second row terminal (BUMP1) in FIG. The terminal in the column (BUMP1)) and the length of the output terminal (BUMP1) in the column direction are shortened, so that the gap between the wiring layer (COFA) of the film substrate 310 and the adjacent output terminal (BUMP1) (see FIG. 20 La) is lengthened to avoid the occurrence of short circuit failure.

Further, as the interval (pitch) between the output terminals (BUMP1) becomes smaller, a defect due to the displacement between the probe and the output terminal (BUMP1) occurs when the probe inspection is performed.
Therefore, in this embodiment, when the probe is performed every n pins on the output terminals (BUMP1) arranged in n (n> 1) stages, the wiring layer (COFA) formed on the film substrate 310 is drawn from the drawing direction. By increasing the length of the output terminal (BUMP1) arranged far away (the output terminal (BUMP1) in the first column in FIG. 15) in the column direction, and performing the probe inspection in this column, the probe and the output terminal The trouble at the time of the probe inspection due to the deviation of (BUMP1) is avoided.
As described above, in this embodiment, the output terminals in the column that are closer to the direction in which the wiring layer (COFA) formed on the film substrate 310 is pulled out (the output terminal (BUMP1) in the first column in FIG. 20) are closer in the column direction. By shortening the length, it is possible to avoid a short circuit failure between the output terminal (BUMP1) and the wiring layer (COFA) formed on the film substrate 310. Further, the probe and the output terminal (BUMP1) are not aligned during the probe test. The trouble at the time of connection by can be avoided.

[Example 5]
FIG. 21 illustrates a part of the terminal (BUMP) of the semiconductor chip (IC) constituting the drain driver 130 according to the fifth embodiment of the present invention and a part of the wiring layer (COFB) formed on the film substrate 310. FIG.
The wiring layer (COFB) shown in FIG. 21 connects the terminals (BUMP) of the semiconductor chip (IC) mounted on the film substrate 310.
As the liquid crystal display device becomes higher in definition, higher in performance, and larger in screen size, when a higher performance of the drain driver 130 is required, a power wiring layer in a semiconductor chip (IC) constituting the drain driver 130, In the clock wiring layer or the like, output delay due to the influence of load impedance becomes a problem.
Therefore, as in the present embodiment, the drive capability of the drain driver 130 is improved by reinforcing or replacing the metal wiring of the semiconductor chip (IC) with the wiring layer (COFB) of the film substrate 310 having a low impedance. Is possible.

Further, as shown in FIG. 22, it is also possible to connect a plurality of terminals (BUMP) with the same wiring, and further connect this wiring layer (COFB) to the input terminal of the wiring layer formed on the outer periphery of the film substrate 310. It is.
Alternatively, as shown in FIG. 23, terminals (BUMP) that cannot be placed on the outer periphery of the semiconductor chip (IC) are provided on the inner side, and the wiring layer (COFB) of the film substrate 310 is provided on the terminals (BUMP) provided on the inner side. By connecting, a voltage can be supplied to the terminal (BUMP) provided on the inside.
In each of the above embodiments, the embodiment in which the present invention is applied to the vertical electric field type liquid crystal display panel has been described. However, the present invention is not limited to this, and the present invention can also be applied to a horizontal electric field type liquid crystal display panel. is there.
In each of the above embodiments, the dot inversion method is applied as a driving method. However, the present invention is not limited to this, and the present invention is not limited to this. The pixel electrode (ITO1) is used for each line or each frame. The present invention can also be applied to a common inversion method for inverting the drive voltage applied to the common electrode (ITO2).
Furthermore, the present invention can also be applied to a simple matrix liquid crystal display device.
As mentioned above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

10 Liquid crystal display panel (TFT-LCD)
20 Output terminal area (a)
21 Output terminal area (b)
DESCRIPTION OF SYMBOLS 22 Input terminal area | region 23 Input circuit / wiring area | region 100 Interface part 110 Display control apparatus 120 Power supply circuit 121,122 Voltage generation circuit 123 Common electrode voltage generation circuit 124 Gate electrode voltage generation circuit 130 Drain driver 131,132,134,135,141 142 signal line 133 display data bus line 140 gate driver 150 aluminum wiring 151 gradation voltage generation circuit 152 clock control circuit 153 shift register circuit 154 input latch circuit 155 latch circuit (1)
156 Latch circuit (2)
157 Decoder circuit 158 Buffer circuit 251 High voltage decoder circuit 252 Low voltage decoder circuit 254 Shift clock generation circuit 261 Display data selection circuit 262 Data latch unit 263 Level shift circuit 264 Amplifier circuit 265 Output selection circuit 271 High voltage amplifier circuit 272 Low voltage amplifier circuit 301 TFT controller substrate 302 Drain driver substrate 303 Gate driver substrate 310 Film substrate D, Y Drain signal line (video signal line or vertical signal line)
G Gate signal line (scanning signal line or horizontal signal line)
ITO1 pixel electrode ITO2 common electrode CN common signal line TFT thin film transistor CLC liquid crystal capacitor CSTG holding capacitor CADD additional capacitor PM PMOS transistor NM NMOS transistor LS level shift circuit TRP transistor array NAND NAND circuit AND AND circuit NOR NOR circuit INV inverter OP operational amplifier IC semiconductor chip BUMP terminal BUMP1 output terminal BUMP2 input terminal COFA, COFB Wiring layer

Claims (3)

A film substrate on which a first wiring layer and a second wiring layer are formed;
A semiconductor chip mounted on the film substrate by a chip-on-film method,
The first wiring layer is connected to an input terminal formed on the outer periphery of the film substrate,
The second wiring layer is connected between a plurality of terminals of the semiconductor chip,
The first wiring layer and the second wiring layer are connected, and a power supply or a clock of the semiconductor chip is transmitted through the first wiring layer and the second wiring layer,
The driver, wherein the second wiring layer is formed between the semiconductor chip and the film substrate. The semiconductor chip has a longitudinal direction and a lateral direction,
The driver according to claim 1, wherein the second wiring layer is formed in the longitudinal direction. The semiconductor chip is provided with two output circuits arranged in the longitudinal direction,
The driver according to claim 1, wherein the second wiring layer is disposed between the two output circuits.

Images