JP2006126835A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device that eliminates the need to make larger a space where a plurality of signal lines are arranged when the signal lines are arranged on one substrate of a liquid crystal display element and can prevent signal lines from oxidizing or electrically corroding even if a protection film has a defect. <P>SOLUTION: The liquid crystal display device is provided which is equipped with a couple of substrates, the liquid crystal display element having liquid crystal sandwiched between the couple of substrates, a plurality of driving circuits, a display controller, and a power circuit. The liquid crystal display element has, on one substrate between the couple of substrates, the plurality of signal lines for supplying a source voltage from the power circuit and signals from the display controller to the plurality of driving circuits, adjacent signal lines being arranged at intervals such that electric field intensity between mutually adjacent signal lines which is determined by voltages on the signal lines is small enough not to cause electric corrosion. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a liquid crystal display device, and more particularly to a technique effective in arranging signal lines on a liquid crystal display panel.

STN (S uper T wisted N ematic ) method or TFT (T hin F ilm T ransistor ) mode liquid crystal display module, are widely used as a display device such as a notebook personal computer.
These liquid crystal display devices include a liquid crystal display panel, a drive circuit (drain driver and gate driver) for driving the liquid crystal display panel, a display control device (or timing controller), and a power supply circuit.
Such a liquid crystal display device is described in, for example, Patent Document 1 below.

As prior art documents related to the invention of the present application, there are the following.
Japanese Patent Laid-Open No. 10-268838

In the liquid crystal display module described above, a power supply voltage and a signal (pulse voltage) are respectively applied from the drain driver and the gate driver, thereby selectively driving the pixels in the liquid crystal display panel and displaying an image.
At that time, generally, a flexible cable is used to connect the timing control board and the drain board, and the drain board and the gate board, and the power supply voltage and the signal output from the timing control board are respectively connected to the drain board, The pixel is supplied to the gate substrate to drive the pixels in the liquid crystal display panel.
However, when using a so-called flexible cable-less system that does not use a flexible cable as a system for supplying the power supply voltage and drive voltage output from the timing control board to the drain driver and gate driver, respectively, the timing control It is necessary to provide a signal line for transmitting a power supply voltage and a driving voltage output from the substrate on one glass substrate of the liquid crystal display panel.

In the case described above, since the power supply voltage or the signal voltage value supplied to each signal line is different, an electric field proportional to the potential difference is generated between the signal lines.
When this electric field strength is strong, a problem arises in that the metal material constituting the signal line reacts with oxygen in the air and oxidizes and galvanizes.
In order to solve such problems, conventionally, (1) the signal lines are spaced to some extent, or (2) the signal lines are covered with a protective film so that they are not exposed to air. It was.
However, the above-mentioned method (1) has a drawback that the space for wiring the signal lines becomes large and cannot cope with the narrow frame of the liquid crystal display panel, and the above-mentioned method (2) has a drawback. The film has a low density, and if a defect occurs, the signal lines are partially exposed to the atmosphere. Therefore, if the potential difference between the signal lines is large and the interval between them is small, a strong electric field is required. There is a drawback that electric corrosion occurs in the place where it is exposed to the atmosphere.

The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to arrange a plurality of signal lines on one substrate of a liquid crystal display element in a liquid crystal display device. An object of the present invention is to provide a technique capable of preventing oxidation and electrolytic corrosion of a signal line without increasing the space for arranging the signal line and even when a defect occurs in the protective film.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
That is, the present invention is a liquid crystal display device including a liquid crystal display element having a pair of substrates and a liquid crystal sandwiched between the pair of substrates, a plurality of drive circuits, a display control device, and a power supply circuit. The liquid crystal display element has a plurality of signals for supplying a power supply voltage from the power supply circuit and a signal from the display control device to the plurality of driving circuits on one of the pair of substrates. And at least a part of the plurality of signal lines has a non-uniform wiring interval between adjacent signal lines, and is between the adjacent signal lines determined from the voltage on each signal line. It is characterized by being variable according to the potential difference.
In a preferred embodiment of the present invention, at least a part of the plurality of signal lines has a larger wiring interval between the adjacent signal lines as the potential difference between the adjacent signal lines is larger. It is characterized by being wide.

  The present invention is a liquid crystal display device including a liquid crystal display element having a pair of substrates and a liquid crystal sandwiched between the pair of substrates, a plurality of drive circuits, a display control device, and a power supply circuit. The liquid crystal display element has a plurality of signals for supplying a power supply voltage from the power supply circuit and a signal from the display control device to the plurality of driving circuits on one of the pair of substrates. An electric field between adjacent signal lines, wherein a part of the plurality of signal lines has a wiring interval determined from a voltage on each signal line. It is characterized by being arranged at intervals at which the intensity is an electric field intensity at which no electrolytic corrosion occurs.

  The present invention is a liquid crystal display device including a liquid crystal display element having a pair of substrates and a liquid crystal sandwiched between the pair of substrates, a plurality of drive circuits, a display control device, and a power supply circuit. The liquid crystal display element has a plurality of signals for supplying a power supply voltage from the power supply circuit and a signal from the display control device to the plurality of driving circuits on one of the pair of substrates. An electric field between adjacent signal lines, wherein a part of the plurality of signal lines has a wiring interval determined from a voltage on each signal line. The electric field strength is an electric field strength at which the electric corrosion does not occur.

In a preferred embodiment of the present invention, the part of the signal lines includes a signal line that supplies a liquid crystal driving reference voltage when driving the liquid crystal, and supplies the liquid crystal driving reference voltage. Is disposed at a position closest to the liquid crystal side, and the remaining signal lines among the some signal lines are signals for which the signal line having the highest voltage value on the signal line supplies the liquid crystal driving reference voltage. The potential difference between the adjacent signal lines determined from the voltage on each signal line is minimized with respect to the signal line having the highest voltage value on the signal line, which is arranged at the farthest position from the line. It is arranged so that it may be arranged.
In a preferred embodiment of the present invention, the part of the signal lines includes a signal line that is supplied from a display control device and that supplies a pulse voltage signal whose voltage level changes over time, The voltage on the signal line for supplying the pulse voltage signal is defined by the time average voltage value of the pulse voltage.

  According to the above means, when the power supply voltage and a signal line for supplying a signal are arranged on one substrate of the liquid crystal display element to each drive circuit (drain driver or gate driver) from the display control device, The distance between the signal lines is determined so that the electric field strength between adjacent signal lines determined by the voltage on each signal line is an electric field intensity at which no electric corrosion occurs, that is, the voltage on each signal line. When the potential difference between adjacent signal lines is large, the interval between the signal lines is increased, and when the potential difference between adjacent signal lines determined by the voltage on each signal line is small Since the interval between the signal lines is reduced, it is possible to prevent the signal lines from being oxidized and eroded even if a defect occurs in the protective film without increasing the space for arranging the signal lines.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the liquid crystal display device of the present invention, when the signal line for supplying the power supply voltage and the signal is arranged on one substrate of the liquid crystal display element, the protective film is formed without increasing the space for arranging the signal line. Even if a defect occurs, it is possible to prevent the signal line from being oxidized and electrolytic corrosion.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
In all the drawings for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof is omitted.
[Embodiment 1]
[Basic configuration of TFT liquid crystal display module to which the present invention is applied]
FIG. 4 is a block diagram showing a schematic configuration of a TFT liquid crystal display module to which the present invention is applied.
In the liquid crystal display module (LCM) of the present embodiment, a drain driver 130 is disposed on one side of the long side of the liquid crystal display panel (TFT-LCD) 10, and on one side of the short side of the liquid crystal display panel 10, A gate driver 140 is disposed.
The liquid crystal display panel 10 includes a TFT substrate on which pixel electrodes, thin film transistors, and the like are formed and a filter substrate on which counter electrodes, color filters, and the like are formed with a predetermined gap therebetween, and a peripheral portion between the two substrates. Both substrates are bonded together by a sealing material provided in the vicinity of a frame, and liquid crystal is sealed and sealed inside the sealing material between the substrates from a liquid crystal sealing port provided in a part of the sealing material. A polarizing plate is attached to the outside of the substrate.

FIG. 5 is a diagram showing an equivalent circuit of an example of the liquid crystal display panel 10 shown in FIG.
As shown in the figure, the liquid crystal display panel 10 has a plurality of pixels formed in a matrix.
Each pixel includes two adjacent signal lines (drain signal line (D) or gate signal line (G)) and two adjacent signal lines (gate signal line (G) or drain signal line (D)). It is arranged in the intersection area.
Each pixel has a thin film transistor (TFT1, TFT2), the source electrode of the thin film transistor (TFT1, TFT2) of each pixel is connected to the pixel electrode (ITO1), and the pixel electrode (ITO1) and the common electrode (or counter electrode) Since the liquid crystal layer is provided between (ITO2) and the pixel electrode (ITO1) and the common electrode (ITO2), the liquid crystal capacitance (CLC) is equivalently connected.
Further, an additional capacitor (CADD) is connected between the pixel electrode (ITO1) and the previous gate signal line (G).

FIG. 6 is a diagram showing an equivalent circuit of another example of the liquid crystal display panel 10 shown in FIG.
In the example shown in FIG. 5, an additional capacitor (CADD) is formed between the previous gate signal line (G) and the source electrode. In the equivalent circuit of the example shown in FIG. 6, the common electrode (ITO2) is connected to the common electrode (ITO2). The difference is that a storage capacitor (CSTG) is formed between the common signal line (CL) to which the supplied Vcom voltage is applied and the pixel electrode (ITO1).
In FIGS. 5 and 6, AR is a display area.
Although the present invention can be applied to both, in the former method, the gate signal line (G) pulse in the former stage jumps into the pixel electrode via the additional capacitor (CADD), whereas in the latter method, the jump in Therefore, better display is possible.
5 and 6 show an equivalent circuit of a vertical electric field type liquid crystal display panel. Further, FIGS. 5 and 6 are circuit diagrams, which are drawn corresponding to an actual geometric arrangement. ing.

In the liquid crystal display panel 10 shown in FIGS. 5 and 6, the drain electrodes of the thin film transistors (TFT1, TFT2) of the pixels arranged in the column direction are respectively connected to the drain signal lines (D), and the drain signal lines (D ) Is connected to a drain driver 130 for applying a gradation voltage to the liquid crystal of each pixel in the column direction.
In addition, the gate electrodes of the thin film transistors (TFT1, TFT2) in each pixel arranged in the row direction are connected to the gate signal line (G), respectively, and each gate signal line (G) has one horizontal scanning time in the row direction. It is connected to a gate driver 140 that supplies a scanning drive voltage (positive bias voltage or negative bias voltage) to the gate electrode of the thin film transistor (TFT1, TFT2) of each pixel.

The interface unit 100 shown in FIG. 4 includes a timing controller (display control device of the present invention) 110 and a power supply circuit 120.
The timing controller 110 is composed of one semiconductor integrated circuit (LSI), and receives a clock signal (CK), a display timing signal (DTMG), a horizontal synchronization signal (HSYNC), and a vertical synchronization signal (from the computer main body side). The drain driver 130 and the gate driver 140 are controlled and driven based on each display control signal of VSYNC) and display data (R, G, B).
When the display timing signal is input, the timing controller 110 determines that this is the display start position, and outputs a start pulse (display data capture start signal) to the first drain driver 130 via the signal line 135. Further, the received simple one-line display data is output to the drain driver 130 via the display data bus line 133.
At that time, the timing controller 110 outputs a display data latch clock signal (CL 2), which is a display control signal for latching display data, to the data latch circuit of the drain driver 130 via the signal line 131.
The display data from the main body computer is, for example, 6 bits or 8 bits, and is in units of one pixel, ie, each unit of red (R), green (G), and blue (B) data as a set. Forwarded to

The timing controller 110 determines that the display data for one horizontal line has ended when the input of the display timing signal is completed or a predetermined fixed time has passed after the display timing signal is input. The output timing control clock signal (CL1), which is a display control signal for outputting the gradation voltage based on the display data stored in the latch circuit, to the drain signal line (D) of the liquid crystal display panel 10, is the signal line 132. To the drain driver 130.
In addition, when the first display timing signal is input after the vertical synchronization signal is input, the timing controller 110 determines that this is the first display line and starts the frame to the gate driver 140 via the signal line 142. An instruction signal (FLM) is output.
Furthermore, the timing controller 110 is connected via the signal line 142 so as to sequentially apply a positive bias voltage to each gate signal line (G) of the liquid crystal display panel 10 every horizontal scanning time based on the horizontal synchronization signal. Then, a shift clock signal (CL3) of one horizontal scanning time period is output to the gate driver 140.
As a result, a plurality of thin film transistors (TFT1, TFT2) connected to each gate signal line (G) of the liquid crystal display panel 10 are turned on for one horizontal scanning time, and a gradation voltage is written to the pixels of one display line. .
With the above operation, an image is displayed on the liquid crystal display panel 10.

The power supply circuit 120 illustrated in FIG. 4 includes a positive voltage generation circuit 121, a negative voltage generation circuit 122, a common electrode (counter electrode) voltage generation circuit 123, and a gate electrode voltage generation circuit 124.
The positive voltage generation circuit 121 and the negative voltage generation circuit 122 are each configured by a series resistance voltage dividing circuit, and the positive voltage generation circuit 121 is, for example, a positive five-value gradation reference voltage (V "0 to V" 4). The negative voltage generation circuit 122 outputs, for example, a negative five-value gradation reference voltage (V "5 to V" 9).
The positive polarity reference voltage (for example, V ″ 0 to V ″ 4) and the negative polarity reference voltage (for example, V ″ 5 to V ″ 9) are supplied to each drain driver 130.
Each drain driver 130 is also supplied with an AC signal (AC timing signal; M) from the timing controller 110 via a signal line 134.
The common electrode voltage generation circuit 123 is a drive voltage to be applied to the common electrode (ITO2), and the gate electrode voltage generation circuit 124 is a drive voltage to be applied to the gate electrodes of the thin film transistors (TFT1 and TFT2) (positive bias voltage and negative bias voltage). ) Is generated.

[Configuration of Liquid Crystal Display Module of Embodiment 1 of the Present Invention]
FIG. 1 is a diagram showing a state in which a drain driver 130 and a gate driver 140 are arranged around a liquid crystal display panel 10 in the liquid crystal display module according to Embodiment 1 of the present invention.
In FIG. 1, 31 is a drain side TCP (Tape Carrier Package) mounted between one glass substrate (TFT substrate side glass substrate) of the liquid crystal display panel 10 and the drain substrate 30, and 41 is a liquid crystal display. This is a gate-side TCP mounted between one glass substrate of the panel 10 and the gate substrate 40.
A semiconductor chip (ICd) constituting the drain driver 130 is mounted on the drain side TCP (31), and a semiconductor chip (ICg) constituting the gate driver 140 is mounted on the gate side TCP (41).
A timing controller 110 and a power supply circuit 120 are mounted on the timing control board 20.

[Configuration of conventional LCD module]
FIG. 8 is a diagram showing a state in which the drain driver 130 and the gate driver 140 are arranged around the liquid crystal display panel 10 in the conventional liquid crystal display module.
As shown in FIG. 8, in the conventional liquid crystal display module, the power supply voltage and signal output from the timing control board 20 to the drain board 30 are sent to the drain board 30 via the flexible cable 60.
The power supply voltage and signal output from the timing control board 20 to the gate board 40 are sent to the gate board 40 via the flexible cable 60 → the drain board 30 → the flexible cable 61 → the gate board 40.

[Features of the liquid crystal display module of the embodiment of the present invention]
FIG. 2 is an enlarged view showing a dotted circle in FIG.
In FIG. 2, SUB1 is a glass substrate on the TFT substrate side, and SUB2 is a glass substrate on the filter substrate side.
In the present embodiment, the power supply voltage and signal sent from the timing control substrate 20 to the gate substrate 40 are the signal line 50 on the drain substrate 30 → the first drain side TCP (31) → the glass substrate (SUB1). → First gate side TCP (41) → Gate substrate 40 is transferred in this order.
Here, there are five types of power supply voltages sent from the timing control board 20 to the gate board 40: Vcom, VGH, VGL, Vcc and GND, and the signals are clock (CL3), FLM (frame start instruction signal), And OE (output enable signal).
These signal lines 50 are made of Al (aluminum), Cr (chromium), molybdenum (Mo), or the like, and are usually covered with a protective film or the like so as not to come into contact with the atmosphere.
In FIG. 2, nine signal lines are shown, but one is a dummy signal line.
Next, the wiring interval between the signal lines, which is a feature of this embodiment, will be described with reference to FIG.
In FIG. 3, the power supply voltages (Vcom, VGH, VGL, Vcc, GND) will be mainly described.
Table 1 shows the voltage values of these power supply voltages.

Vcom is a voltage applied to the common electrode (ITO2), VGH is a voltage for turning on the thin film transistors (TFT1, TFT2), VGL is a voltage for turning off the thin film transistors (TFT1, TFT2), and Vcc is a gate driver. The power supply voltage GND (or Vss) for the logic circuit inside the semiconductor chip 140 is a ground voltage.
As shown in FIG. 3, the voltage Vcom is a voltage applied to the common electrode (ITO 2) and needs to be supplied to the inside of the liquid crystal panel 10. Therefore, the signal line 51 for supplying Vcom is one of the liquid crystal panels 10. It is arranged on the innermost side (area closest to the effective display area AR).
As shown in Table 1, the other signal lines (52 to 55) are arranged so that the potential difference between the adjacent signal lines is minimized.
In this embodiment, as shown in FIG. 3, a signal line 51 supplying Vcom → a signal line 52 supplying VGL → a signal line 53 supplying GND → a signal line 54 supplying Vcc → a signal supplying VGH The line 55 is in this order.

In this embodiment, the interval between the signal lines having the largest potential difference between the adjacent signal lines (in this embodiment, the interval between the signal line 54 that supplies Vcc and the signal line 55 that supplies VGH). ) Is determined so that the electric field intensity does not occur.
In this embodiment, as shown in Table 1, the distance between the signal line 54 supplying Vcc and the signal line 55 supplying VGH is 1.0 mm.
Therefore, the electric field strength is 16.7 (= 16.7 / 1.0) (V / mm).
Then, the wiring interval between the remaining signal lines is determined so as to be substantially equal to the electric field strength described above.
Therefore, in this embodiment, as shown in Table 1, the wiring interval between the signal line 54 that supplies Vcc and the signal line 53 that supplies GND is 0.2 mm, and the signal line 53 that supplies GND and VGL The wiring interval between the signal line 52 and the signal line 52 supplying Vcom is 0.24 mm, and the wiring interval between the signal line 52 supplying the VGL and the signal line 52 supplying Vcom is 0.6 mm.

Thus, by determining the wiring interval of the signal lines (51 to 55), no electric corrosion occurs, and it is possible to arrange the wiring in the smallest space compared to other arrangements.
In the above description, the case where the electric field strength at which no electric corrosion occurs is 16.7 (V / mm) has been described. However, the electric field strength at which no electric corrosion occurs depends on the signal line material and the protective film. Since it differs for each liquid crystal display panel depending on the capacity and the like, it is necessary to set an optimum electric field strength as an electric field strength that does not cause electrolytic corrosion for each liquid crystal display panel.
In the above description, the wiring intervals of the signal lines for supplying the power supply voltages (Vcom, VGH, VGL, Vcc, GND) have been described. However, the signal (clock (CL3), FLM (frame start instruction signal), OE ( The wiring interval with the signal line supplying the output enable signal)) can be determined in the same manner.
However, since these signals are voltages whose voltage values change with time (so-called pulse voltage), the voltage values in this case need to be defined by taking a time average.

[Embodiment 2]
[Configuration of Liquid Crystal Display Module of Embodiment of the Present Invention]
FIG. 7 is a diagram showing a state in which the drain driver 130 and the gate driver 140 are arranged around the liquid crystal display panel 10 in the liquid crystal display module according to the second embodiment of the present invention.
In the liquid crystal display module of the present embodiment, the timing controller 110, the semiconductor chip ICd constituting the drain driver 130, and the semiconductor chip ICg constituting the gate driver 140 are mounted on the glass substrate (SUB1) on the TFT substrate side of the liquid crystal display panel 10. To be implemented.
The signal supplied from the timing control 110 to the semiconductor chip ICg constituting the gate driver 140 and the power supply voltage supplied from the power supply circuit 120 to the semiconductor chip ICg constituting the gate driver 140 are the TFTs of the liquid crystal display panel 10. It is supplied to each semiconductor chip ICg constituting the gate driver 140 via a signal line formed on the glass substrate (SUB1) on the substrate side.
Here, the power supply circuit 120 is installed outside the liquid crystal display panel 10.

The signal supplied from the timing control 110 to the semiconductor chip ICd constituting the drain driver 130 and the gradation reference voltage supplied from the power supply circuit 120 to the semiconductor chip ICd constituting the drain driver 130 are the liquid crystal display panel 10. Is supplied to the semiconductor chip ICd constituting each drain driver 130 via a signal line formed on the glass substrate (SUB1) on the TFT substrate side.
However, the power supply voltage for the logic circuit inside the semiconductor chip constituting the drain driver 130 is supplied to each drain driver 130 via the power supply circuit 120 → the flexible printed board 150.
Also in the present embodiment, a space for arranging signal lines is obtained by setting the wiring intervals of the signal lines formed on the glass substrate (SUB1) on the TFT substrate side of the liquid crystal display panel 10 to the wiring intervals as described above. It is possible to prevent signal line oxidation and galvanic corrosion even if a defect occurs in the protective film without increasing the thickness.

In the present embodiment, the power supply voltage for the logic circuit in the semiconductor chip constituting the drain driver 130 is supplied via the signal line formed on the glass substrate (SUB1) on the TFT substrate side of the liquid crystal display panel 10. You may make it supply to each drain driver 130. FIG.
Also in this case, by using the wiring interval as described above, it is possible to prevent the signal line from being oxidized and eroded even if a defect occurs in the protective film without increasing the space for arranging the signal line. Become.
In each of the above-described embodiments, the case where the present invention is applied to a vertical electric field type liquid crystal display panel has been described. However, the present invention is not limited to this, and can be applied to a horizontal electric field type liquid crystal display panel. .
In each of the above embodiments, the present invention is applied to a TFT liquid crystal display device. However, the present invention is not limited to this, and the present invention is applied to an STN simple matrix liquid crystal display device. It goes without saying that is also applicable.
As mentioned above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

In the liquid crystal display module of Embodiment 1 of this invention, it is a figure which shows the state which has arrange | positioned the drain driver and the gate driver around the liquid crystal display panel. It is a figure which expands and shows the part of the dotted-line circle in FIG. It is a figure for demonstrating the wiring space | interval of a signal line in Embodiment 1 of this invention. It is a block diagram which shows schematic structure of the liquid crystal display module of the TFT system to which this invention is applied. FIG. 5 is a diagram showing an equivalent circuit of an example of the liquid crystal display panel shown in FIG. 4. It is a figure which shows the equivalent circuit of the other example of the liquid crystal display panel shown in FIG. It is a figure which shows the state which has arrange | positioned the drain driver and the gate driver around the liquid crystal display panel in the liquid crystal display module of Embodiment 2 of this invention. It is a figure which shows the state which has arrange | positioned the drain driver and the gate driver around the liquid crystal display panel in the conventional liquid crystal display module.

Explanation of symbols

10 Liquid crystal display panel 20 Timing control board 30 Drain board 31, 41 TCP
40 Gate substrate 50, 51 to 55, 131, 132, 134, 135, 141, 142 Signal line 60, 61 Flexible cable 100 Interface unit 110 Timing controller 120 Power supply circuit 121 Positive voltage generation circuit 122 Negative voltage generation circuit 123 Common electrode ( Counter electrode) Voltage generation circuit 124 Gate electrode voltage generation circuit 130 Drain driver 133 Display data bus line 140 Gate driver 150 Flexible printed circuit board AR display area ITO1 Pixel electrode ITO2 Common electrode D Drain signal line G Gate signal line TFT1, TFT2 Thin film transistor CLC liquid crystal capacitor CADD additional capacitor CSTG holding capacitor CL common signal line ICd, ICg semiconductor chip SUB1, SUB2 Glass substrate.

Claims (6)

A liquid crystal display element having a pair of substrates and a liquid crystal sandwiched between the pair of substrates;
A plurality of drive circuits;
A display control device;
A liquid crystal display device comprising a power supply circuit,
The liquid crystal display element has a plurality of signal lines that supply a power supply voltage from the power supply circuit and a signal from the display control device to the plurality of driving circuits on one of the pair of substrates. And
At least some of the plurality of signal lines have a non-uniform wiring interval between adjacent signal lines, and are variable according to a potential difference between adjacent signal lines determined from a voltage on each signal line. A liquid crystal display device.   The wiring interval between the adjacent signal lines is increased as the potential difference between the adjacent signal lines is larger in at least a part of the plurality of signal lines. 2. A liquid crystal display device according to 1. A liquid crystal display element having a pair of substrates and a liquid crystal sandwiched between the pair of substrates;
A plurality of drive circuits;
A display control device;
A liquid crystal display device comprising a power supply circuit,
The liquid crystal display element has a plurality of signal lines that supply a power supply voltage from the power supply circuit and a signal from the display control device to the plurality of driving circuits on one of the pair of substrates. And
Some signal lines of the plurality of signal lines are electrically eroded by the electric field strength between the adjacent signal lines, the wiring interval between the adjacent signal lines being determined from the voltage on each signal line. A liquid crystal display device, characterized in that the liquid crystal display devices are arranged at an interval at which the electric field intensity does not occur. A liquid crystal display element having a pair of substrates and a liquid crystal sandwiched between the pair of substrates;
A plurality of drive circuits;
A display control device;
A liquid crystal display device comprising a power supply circuit,
The liquid crystal display element has a plurality of signal lines that supply a power supply voltage from the power supply circuit and a signal from the display control device to the plurality of driving circuits on one of the pair of substrates. And
Some signal lines of the plurality of signal lines have substantially the same electric field strength between adjacent signal lines in which a wiring interval between adjacent signal lines is determined from a voltage on each signal line. Are arranged at intervals,
The liquid crystal display device, wherein the electric field intensity is an electric field intensity at which no electrolytic corrosion occurs. The part of the signal lines includes a signal line for supplying a reference voltage for driving liquid crystal when driving the liquid crystal,
The signal line for supplying the liquid crystal driving reference voltage is disposed at a position closest to the liquid crystal side,
The remaining signal lines among the signal lines are arranged such that the signal line having the highest voltage value on the signal line is located farthest from the signal line that supplies the liquid crystal driving reference voltage. 4. The signal line having the highest voltage value on the line is arranged so that the potential difference between the adjacent signal lines determined from the voltage on each signal line is minimized. Or the liquid crystal display device of Claim 4. The part of the signal lines includes a signal line that is supplied from the display control device and supplies a pulse voltage signal whose voltage level changes with time.
6. The liquid crystal display according to claim 1, wherein a voltage on a signal line for supplying the pulse voltage signal is defined by a time average voltage value of the pulse voltage. apparatus.

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