JP5026550B2 - Liquid crystal display - Google Patents

Description

  The present invention relates to a liquid crystal display device, and more particularly to a technique that is effective when applied to a drive circuit of a liquid crystal display device having two liquid crystal display panels used in a mobile phone or the like.

A TFT (Thin Film Transistor) type liquid crystal display module having a small liquid crystal display panel with a sub-pixel number of about 100 × 150 × 3 in color display, or an EL display device having an organic EL element, such as a mobile phone Widely used as a display unit for portable devices.
Further, in recent years, a foldable mobile phone including a main display unit and a sub display unit is also used.
As a liquid crystal display module for a mobile phone including such a main display unit and a sub display unit, a first liquid crystal display panel corresponding to the main display unit and a second liquid crystal display module corresponding to the sub display unit are provided. An integrated liquid crystal display module including a liquid crystal display panel is known. (See Patent Document 1 below).
The integrated liquid crystal display module described in Patent Document 1 described above connects the first liquid crystal display panel and the second liquid crystal display panel with connection wirings on a flexible circuit board, and one liquid crystal drive. The circuit drives the first and second liquid crystal display panels.
As a result, it is possible to reduce mounting parts, reduce costs, and save space.

JP 2004-61892 A

In the liquid crystal display module described in Patent Document 1, the number of display lines of the main display unit is m, and the number of display lines of the sub display unit is n. Since it is driven as a single screen, it is not possible to employ an optimum driving method for each of the main and sub display units, which hinders reduction in power consumption.
The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to realize an optimum driving method in a small-sized liquid crystal display device having two liquid crystal display panels. The object is to provide a technique capable of reducing power consumption.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
That is, the present invention includes a first liquid crystal display panel, a second liquid crystal display panel, a drive circuit provided in the first liquid crystal display panel, and the drive circuit provided in the first liquid crystal display panel. In a liquid crystal display device having an output terminal to which a signal output from the terminal is supplied, and a connection wiring for connecting the output terminal and the second liquid crystal display panel, the first liquid crystal display panel existing in the same frame It is possible to change the alternating drive method during the display period and the alternating drive method during the display period of the second liquid crystal display panel.
Further, according to the present invention, the AC switching of the first common voltage is stopped during the non-display period of the first liquid crystal display panel, and the second common voltage is stopped during the non-display period of the second liquid crystal display panel. It is characterized by stopping the exchange.
In the present invention, the drive circuit includes a booster circuit unit, and the booster circuit unit can change an operation mode by an external signal.
In the present invention, the drive circuit includes a gradation voltage generation unit, and the drive circuit is configured to output the floor during a non-display period of the first liquid crystal display panel or the second liquid crystal display panel. An unnecessary amplifier circuit is stopped in the regulated voltage generation unit.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the liquid crystal display device of the present invention, low power consumption can be achieved.

It is a block diagram which shows schematic structure of the liquid crystal display module of Example 1 of this invention. It is a block diagram which shows schematic structure of the modification of the liquid crystal display module of Example 1 of this invention. It is a figure for demonstrating the alternating current drive method of the conventional liquid crystal display module. It is a figure for demonstrating an example of the alternating drive method of the liquid crystal display module of Example 1 of this invention. It is a figure for demonstrating the instruction signal used in the liquid crystal display module of Example 1 of this invention. In the liquid crystal display module of Example 1 of this invention, when a drive circuit is divided | segmented into two, it is a figure for demonstrating the signal transferred to a 2nd drive circuit from a 1st drive circuit. In the liquid crystal display module of Example 1 of this invention, when a drive circuit is divided | segmented into two, it is a figure for demonstrating the signal transferred to a 2nd drive circuit from a 1st drive circuit. It is a figure for demonstrating an example of the alternating drive method of the liquid crystal display module of Example 2 of this invention. It is a figure for demonstrating the other example of the alternating drive method of the liquid crystal display module of Example 2 of this invention. It is a figure for demonstrating the other example of the alternating drive method of the liquid crystal display module of Example 2 of this invention. It is a block diagram which shows schematic structure of an example of the source driver (SD) of the liquid crystal display module of Example 1 of this invention. It is a figure which shows an example of a structure of the gradation voltage generation circuit and selector in the liquid crystal display module of Example 3 of this invention. It is a figure which shows the other example of a structure of the gradation voltage generation circuit and selector in the liquid crystal display module of Example 3 of this invention. It is a figure for demonstrating the booster circuit of the liquid crystal display module of Example 4 of this invention. It is a figure for demonstrating the booster circuit of the liquid crystal display module of Example 4 of this invention. It is a figure for demonstrating the booster circuit of the liquid crystal display module of Example 4 of this invention. FIG. 15 is a circuit diagram showing a more specific configuration of the booster circuit shown in FIG. 14.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
In all the drawings for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof is omitted. Also, the following examples are not intended to limit the interpretation of the scope of the claims of the present invention.
[Example 1]
FIG. 1 is a block diagram showing a schematic configuration of a liquid crystal display module according to Embodiment 1 of the present invention.
The liquid crystal display module of the present embodiment is an integrated liquid crystal display module including a first liquid crystal display panel and a second liquid crystal display panel.
In FIG. 1, PNL1 is a first liquid crystal display panel serving as a main display when the foldable mobile phone is used in an open state, and PNL2 is used with the foldable mobile phone closed. It is the 2nd liquid crystal display panel used as the sub display part when doing.
The first liquid crystal display panel (PNL1) and the second liquid crystal display panel (PNL2) each include a plurality of scanning lines (or gate lines) (GL) and video lines (or drain lines) (SL). Each is provided in parallel.
A pixel portion is provided corresponding to a portion where the scanning line (GL) and the video line (SL) intersect. The plurality of pixel portions are arranged in a matrix, and each pixel portion is provided with a pixel electrode 12 and a thin film transistor 10.
The first and second liquid crystal display panels (PNL1, PNL2) include glass substrates (SUB1, SUB2) provided with pixel electrodes 12, thin film transistors 10 and the like, and glass substrates (not shown) on which color filters and the like are formed. Are laminated with a predetermined gap therebetween, and both substrates are bonded together by a sealing material provided in a frame shape in the vicinity of the peripheral edge between the two substrates, and both are attached from a liquid crystal sealing port provided in a part of the sealing material. The liquid crystal is sealed and sealed inside the sealing material between the substrates, and a polarizing plate is attached to the outside of both substrates.
Since the present invention is not related to the internal structure of the liquid crystal display panel, a detailed description of the internal structure of the liquid crystal display panel is omitted. Furthermore, the present invention can be applied to a liquid crystal display panel having any structure.

In the present embodiment, the first drive circuit (DRV1) is mounted on the glass substrate (SUB1) of the first liquid crystal display panel.
The first drive circuit (DRV1) includes a controller (CNTL), a source driver (SD) for driving the video lines (SL) of the first and second liquid crystal display panels (PNL1, PNL2), first and second The gate driver (GD) for driving the scanning lines (GL) of the liquid crystal display panels (PNL1, PNL2) and the common electrode (also referred to as counter electrode or common electrode) 15 of the first liquid crystal display panel (PNL1) A first common voltage (Vcom1) and a power supply circuit (PC) for supplying the second common voltage (Vcom2) to the common electrode 15 of the second liquid crystal display panel (PNL2) are included.
Display data and a display control signal are input to the controller (CNTL) from a central processing unit (hereinafter referred to as MPU) on the main body side.
Note that FIG. 1 illustrates a case where the first drive circuit (DRV1) is configured by one semiconductor chip.

FIG. 2 is a block diagram showing a schematic configuration of a modification of the liquid crystal display module of the present embodiment.
In the liquid crystal display module shown in FIG. 2, the drive circuit is divided into two parts, a first drive circuit (DRV1) and a second drive circuit (DRV2).
In FIG. 2, the first drive circuit (DRV1) has a controller (CNTL) and a source driver (SD) that drives the video lines (SL) of the first and second liquid crystal display panels (PNL1, PNL2). The second drive circuit (DRV2) includes a gate driver (GD) that drives the scanning lines (GL) of the first and second liquid crystal display panels (PNL1, PNL2), and a first liquid crystal display panel (PNL1). The power supply circuit (PC) supplies the first common voltage (Vcom1) to the common electrode 15 and the second common voltage (Vcom2) to the common electrode 15 of the second liquid crystal display panel (PNL2).
Further, each of the first drive circuit (DRV1) and the second drive circuit (DRV2) is configured by one semiconductor chip.

As shown in FIG. 1, terminals (not shown) are formed on the first liquid crystal display panel (PNL1) and the second liquid crystal display panel (PNL2), respectively, and these terminals are formed on the flexible wiring board (FPC). By being connected, the second liquid crystal display panel (PNL2) is connected to the first liquid crystal display panel (PNL1) via the flexible wiring board (FPC).
A flexible wiring board (FPC) is provided with connection wiring for video lines, connection wiring for scanning lines, connection wiring for control signals, and connection wiring for common electrodes.
That is, the video line (SL) of the second liquid crystal display panel (PNL2) is connected to the video wiring of the flexible wiring board (FPC) and the video line (SL) of the first liquid crystal display panel (PNL1). To the first drive circuit (DRV1).
The scanning lines (GL) of the second liquid crystal display panel (PNL2) are connected to the scanning lines of the flexible wiring board (FPC) and the glass substrate (SUB1) of the first liquid crystal display panel (PNL1). It is connected to the first drive circuit (DRV1) via the upper wiring.
Further, the common electrode 15 of the second liquid crystal display panel (PNL2) is connected to the common electrode connection wiring of the flexible wiring board (FPC) and the glass substrate (SUB1) of the first liquid crystal display panel (PNL1). It is connected to the first drive circuit (DRV1) via the wiring.

When driving the first liquid crystal display panel (PNL1) and the second liquid crystal display panel (PNL2) sharing the video lines as shown in FIGS. 1 and 2, conventionally, as shown in FIG. The liquid crystal display panel (PNL1) and the second liquid crystal display panel (PNL2) are driven as a single screen of a pseudo (m + n) line. Therefore, the first liquid crystal display panel (PNL1) And the alternating drive method of the second liquid crystal display panel (PNL2) could not be changed.
However, in order to reduce power consumption, it is desirable to be able to select an AC drive method that is optimal for each liquid crystal display panel.
In FIG. 3, m is the number of display lines of the first liquid crystal display panel (PNL1), n is the number of display lines of the second liquid crystal display panel (PNL2), F1 is the first frame, F2 is the second frame, PE1 is a display period of the first liquid crystal display panel (PNL1), PE2 is a display period of the second liquid crystal display panel (PNL2), and WE1 and WE2 are wait periods.
FIG. 3 shows a case where the first liquid crystal display panel (PNL1) and the second liquid crystal display panel (PNL2) both adopt the one-line common inversion method as an alternating drive method.

Therefore, in this embodiment, the AC drive method can be freely set in each of the display period of the first liquid crystal display panel (PNL1) and the display period of the second liquid crystal display panel (PNL2) existing in the same frame. It can be set.
For example, as shown in FIG. 4, the first liquid crystal display panel (PNL1) is driven by the one-line common inversion method, and the second liquid crystal display panel (PNL2) is driven by the one-frame common inversion method.
A driving circuit for driving the first and second liquid crystal display panels (PNL1, PNL2) drives a power supply circuit (PC) for generating a common potential (Vcom) to be applied to the common electrode 15 and a scanning line (GL). A gate driver (GD), a source driver (SD) that outputs gradation voltages, a controller (CNTL), and the like.
Here, the controller (CNTL) is connected to the MPU, the drive conditions (AC drive method) of the first and second liquid crystal display panels (PNL1, PNL2) are set by the MPU, and the drive conditions Is written and held in the register (RST in FIGS. 6 and 7) from the MPU into the controller (CNTL), and the first liquid crystal display panel (PNL1) and the second liquid crystal display panel ( The AC drive method is changed for each PNL 2).

When the drive circuit has a single semiconductor chip configuration shown in FIG. 1, these drive circuits are all included in the first drive circuit (DRV1).
In order to drive the first liquid crystal display panel (PNL1) and the second liquid crystal display panel (PNL2) by changing the alternating drive method, the display period of the first liquid crystal display panel (PNL1), and the second It is necessary to set the display period of the second liquid crystal display panel (PNL2).
For this reason, the number of display lines of each liquid crystal display panel and each wait period are sent from the MPU to the controller (CNTL) and set in registers built in the controller (CNTL).
Also, in the AC drive system of each liquid crystal display panel, an instruction signal is sent from the MPU to the controller (CNTL) and set in a register built in the controller (CNTL).
By this setting, the power supply circuit (PC) and the source driver (SD) are controlled to be the same during the display period of the first liquid crystal display panel (PNL1) and the display period of the second liquid crystal display panel (PNL2). It is possible to perform driving in which the alternating drive method is freely set in each of the display period of the first liquid crystal display panel (PNL1) and the display period of the second liquid crystal display panel (PNL2) existing in the frame.
FIG. 5 shows an example of the instruction signal. The instruction signal shown in FIG. 5 indicates 16-bit serial data.
In FIG. 5, 16-bit signals arranged in the horizontal direction are transferred from the outside to the first drive circuit (DRV1) as instruction signals and held in the registers.
In the instruction signal shown in FIG. 5, 3 bits from D15 to D13 are an index code (ID), and the contents of the instruction signal are distinguished.
The number of display lines of each liquid crystal display panel and each wait period are set by 13 bits from D12 to D0.

When the drive circuit is divided into two semiconductor chips as shown in FIG. 2, the common voltage (Vcom) applied to the common electrode 15 is applied to the second drive circuit (DRV2) not including the controller (CNTL). Since the power supply circuit (PC) to be generated is built in, the display period of the first liquid crystal display panel (PNL1) and the display period of the second liquid crystal display panel (PNL2) are set in the second drive circuit (DRV2). It needs to be recognized.
Therefore, as shown in FIG. 6, the instruction signal (INST) sent from the MPU to the controller (CNTL) in the second drive circuit (DRV1) is transferred to the register (RET) in the second drive circuit (DRV2). To do.
Accordingly, the display period of the first liquid crystal display panel (PNL1) and the display period of the second liquid crystal display panel (PNL2) are also set in the second drive circuit (DRV2), and the second drive circuit (DRV2). , The clock signal (CL1) from the controller (CNTL) in the first drive circuit (DRV1) is counted by the counter (CNT), so that the display period of the first liquid crystal display panel (PNL1) and the second The display period of the liquid crystal display panel (PNL2) is recognized.
In the power supply circuit (PC) in the second drive circuit (DRV2), the first common voltage (Vcom1) applied to the common electrode 15 of the first liquid crystal display panel (PNL1) and the second liquid crystal display The AC signal of the second common voltage (Vcom2) applied to the common electrode 15 of the panel (PNL2) is output from the controller (CNTL) in the first drive circuit (DRV1). In the case of the two semiconductor chip configuration, the display period of the first liquid crystal display panel (PNL1) and the display period of the second liquid crystal display panel (PNL2) existing in the same frame are respectively performed. Therefore, it is possible to drive the AC drive system freely.

When the drive circuit is divided into two as in the two semiconductor chips shown in FIG. 2, the display period of the first liquid crystal display panel (PNL1) and the display period of the second liquid crystal display panel (PNL2) are As another method of recognizing, there is a method of transferring a screen recognition signal (DR in FIG. 7) from the controller (CNTL) in the first drive circuit (DRV1) to the second drive circuit (DRV2).
As shown in FIG. 7, a signal line for transferring a screen recognition signal (DR) is provided between the first drive circuit (DRV1) and the second drive circuit (DRV2), and the screen recognition signal (DR) is at a high level (hereinafter referred to as “high”). , H level), the display period of the first liquid crystal display panel (PNL1), and when the screen recognition signal (DR) is low level (hereinafter referred to as L level), the second liquid crystal display panel (PNL2). By setting the display period, the second drive circuit (DRV2) can recognize the display period of the first liquid crystal display panel (PNL1) and the display period of the second liquid crystal display panel (PNL2).
In the power supply circuit (PC) of the second drive circuit (DRV2), the first voltage applied to the common electrode 15 of the first liquid crystal display panel (PNL1) during the display period of the first liquid crystal display panel (PNL1). Only the common voltage (Vcom1) is converted into an alternating current in synchronization with the alternating signal (M) output from the controller (CNTL) in the first drive circuit (DRV1), and the second liquid crystal display panel (PNL2) During the display period, only the second common voltage (Vcom2) applied to the common electrode 15 of the second liquid crystal display panel (PNL2) is converted into an alternating current in synchronization with the alternating signal (M). Even in the case of the two-chip configuration, the alternating drive method is automatically used for the display period of the first liquid crystal display panel (PNL1) and the display period of the second liquid crystal display panel (PNL2) existing in the same frame. Accordingly, in this embodiment, the driving method (AC driving method) of the two liquid crystal display panels of the first and second liquid crystal display panels (PNL1, PNL2) is freely set. Therefore, when the first and second liquid crystal display panels (PNL1, PNL2) are turned on at the same time, it is possible to reduce power consumption.

[Example 2]
In the liquid crystal display module of the present invention, in order to prevent the liquid crystal from being deteriorated by applying a direct current to the liquid crystal, it is necessary to perform an alternating drive that periodically inverts the polarity of the voltage applied to the liquid crystal.
When the common inversion method is adopted as this alternating drive method, the common voltage (Vcom) applied to the common electrode 15 also needs to be alternating, that is, periodically inverted between the positive potential side and the low potential side. .
Further, when the liquid crystal display panel (PNL1, PNL2) has two liquid crystal display panels (PNL1, PNL2) as in the above-described first embodiment, since the necessary voltage value differs for each liquid crystal display panel, the first common voltage (Vcom1) and Two common voltages of the second common voltage (Vcom2) are required.
However, in the display period of the first liquid crystal display panel (PNL1), the second common voltage (Vcom2) applied to the common electrode 15 and the second liquid crystal display panel are applied to the second liquid crystal display panel (PNL2). In the display period of (PNL2), it is not necessary to make the first common voltage (Vcom1) applied to the common electrode 15 of the first liquid crystal display panel (PNL1) AC.
For this reason, the first liquid crystal display panel (PNL1) is converted to AC by changing the first common voltage (Vcom1) to AC and the second common voltage (Vcom2) only during the display period of each liquid crystal display panel. As compared with the case where both the second liquid crystal display panel (PNL2) are driven by common inversion, it is possible to reduce the power consumption accompanying the extra charge / discharge of the liquid crystal display panel, so that the power consumption can be reduced. It becomes possible.
Further, a non-display period for each liquid crystal display panel (a display period of the second liquid crystal display panel (PNL2) in the first liquid crystal display panel (PNL1), and a first period in the second liquid crystal display panel (PNL2)). The common voltage applied to the common electrode 15 of the liquid crystal display panel in the non-display period is not amplified in the liquid crystal display panel (PNL1) display period) regardless of the alternating drive method. The common electrode of the first liquid crystal display panel (PNL1) and the second liquid crystal display panel (PNL2) can be obtained by using only one amplifier that outputs a common voltage by holding the voltage only by the holding capacitor without using the output. The common voltage applied to 15 can be converted into an alternating current.

FIG. 8A shows a common voltage when the common voltage applied to the common electrode 15 of the first liquid crystal display panel (PNL1) and the second liquid crystal display panel (PNL2) is changed to an alternating current in this embodiment. The voltage waveform of is shown.
FIG. 8A shows a case where the common voltage applied to the common electrode 15 of the first liquid crystal display panel (PNL1) and the second liquid crystal display panel (PNL2) is inverted for each line.
In FIG. 8A, F1 is the first frame, F2 is the second frame, PE1 is the display period of the first liquid crystal display panel (PNL1), and PE2 is the display period of the second liquid crystal display panel (PNL2). , P1-L is a one-line inversion period of the common voltage (Vcom1) of the first liquid crystal display panel (PNL1), and P2-L is a one-line inversion period of the common voltage (Vcom2) of the second liquid crystal display panel (PNL2). , KA is a period during which the common voltage is supplied from the amplifier, and KC is a period during which the common voltage is held by the storage capacitor.
FIGS. 8B and 8C show a circuit configuration for realizing the driving method shown in FIG. 8A, and FIG. 8B shows the display of the first liquid crystal display panel (PNL1). FIG. 8C shows the circuit operation during the display period of the second liquid crystal display panel (PNL2).

As shown in FIGS. 8B and 8C, the first amplifier circuit (AMP1) includes a first common voltage (VcomH1) on the high potential side and a second common voltage (VcomH2) on the high potential side. ) Is selectively input via the switching element (S1).
In the second amplifier circuit (AMP2), the first common voltage (VcomL1) on the low potential side and the second common voltage (VcomL2) on the low potential side are selectively transmitted via the switching element (S2). Is input.
The output of the first amplifier circuit (AMP1) is output to the terminal (V1) or the terminal (V3) via the switching element (S3). The terminal (V1) is connected to the first storage capacitor (C1), and the terminal (V3) is connected to the third storage capacitor (C3).
The output of the second amplifier circuit (AMP2) is output to the terminal (V2) or the terminal (V4) via the switching element (S4). The terminal (V2) is connected to the second storage capacitor (C2), and the terminal (V4) is connected to the fourth storage capacitor (C4).
The voltage of the terminal (V1) or the terminal (V2) is output to the terminal (VC1) through the switching element (S5), and the voltage output from the terminal (VC1) is the first liquid crystal display panel (PNL1). To the common electrode 15.
The voltage of the terminal (V3) or the terminal (V4) is output to the terminal (VC2) through the switching element (S6), and the voltage output from the terminal (VC2) is the second liquid crystal display panel (PNL2). To the common electrode 15.

Hereinafter, the circuit operation in the display period of the first liquid crystal display panel (PNL1) will be described with reference to FIG.
During this period, the switching element (S1) selects the first common voltage (VcomH1) on the high potential side, and the first amplifier circuit (AMP1) has the first common voltage (VcomH1) on the high potential side. ) Is entered.
The switching element (S2) selects the first common voltage (VcomL1) on the low potential side, and the first common voltage (VcomL1) on the low potential side is input to the second amplifier circuit (AMP2). .
The switching element (S3) selects the terminal (V1) side, and the output of the first amplifier circuit (AMP1) is output to the terminal (V1).
Similarly, the switching element (S4) selects the terminal (V2) side, and the output of the second amplifier circuit (AMP2) is output to the terminal (V2).
Since the switching element (S5) selects the voltage of the terminal (V1) or the terminal (V2) in synchronization with the alternating signal (M), the first potential on the high potential side is selected from the terminal (VC1). The common voltage (VcomH1) and the first common voltage on the low potential side (VcomL1) are alternately output for each line and applied to the common electrode 15 of the first liquid crystal display panel (PNL1).
At this time, the switching element (S6) is stopped, and the voltage held in the holding capacitor (C3) or the holding capacitor (C4) is output from the terminal (VC2), and the second liquid crystal display panel ( PNL2) is applied to the common electrode 15.
FIG. 8B shows a case where the voltage held in the holding capacitor (C4) is output from the terminal (VC2).

Hereinafter, the circuit operation in the display period of the second liquid crystal display panel (PNL2) will be described with reference to FIG.
During this period, the switching element (S1) selects the second common voltage (VcomH2) on the high potential side, and the second common voltage (VcomH2) on the high potential side is supplied to the first amplifier circuit (AMP1). ) Is entered.
The switching element (S2) selects the second common voltage (VcomL2) on the low potential side, and the second common voltage (VcomL2) on the low potential side is input to the second amplifier circuit (AMP2). .
The switching element (S3) selects the terminal (V3) side, and the output of the first amplifier circuit (AMP1) is output to the terminal (V3).
Similarly, the switching element (S4) selects the terminal (V4) side, and the output of the second amplifier circuit (AMP2) is output to the terminal (V4).
Since the switching element (S6) selects the voltage of the terminal (V2) or the terminal (V4) in synchronization with the alternating signal (M), the second potential on the high potential side is selected from the terminal (VC2). The common voltage (VcomH2) and the second common voltage on the low potential side (VcomL2) are alternately output for each line and applied to the common electrode 15 of the second liquid crystal display panel (PNL2).
At this time, the switching element (S5) is stopped, and the voltage held in the holding capacitor (C1) or the holding capacitor (C2) is output from the terminal (VC1), and the first liquid crystal display panel ( Applied to the common electrode 15 of PNL1).
Note that FIG. 8C illustrates a case where the voltage held in the holding capacitor (C2) is output from the terminal (VC1).

In FIG. 9A, in this embodiment, a one-line common inversion method for inverting the common voltage applied to the common electrode 15 of the first liquid crystal display panel (PNL1) for each line, a second liquid crystal display panel The voltage waveform of the common electrode in the case of adopting the one-frame common inversion method in which the common voltage applied to the common electrode 15 of (PNL2) is inverted every frame is shown in FIG. 9B and FIG. 9A. FIG. 9C shows the circuit operation during the display period of the first liquid crystal display panel (PNL1) in the driving method shown, and FIG. 9C shows the circuit operation during the display period of the second liquid crystal display panel (PNL2).
Similarly, FIG. 10A employs a one-line common inversion method in which a common voltage applied to the common electrode 15 of the first liquid crystal display panel (PNL1) is inverted for each line, thereby providing a second liquid crystal display. The voltage waveform of the common electrode when the panel (PNL2) is set to non-display is shown in FIG. 10B, and the circuit of the display period of the first liquid crystal display panel (PNL1) in the driving method shown in FIG. FIG. 10C shows the operation, and the circuit operation in the display period of the second liquid crystal display panel (PNL2) is shown.
9 and 10, P2-F is a one-frame inversion period of the common voltage (Vcom2) of the second liquid crystal display panel (PNL2). The circuit operations shown in FIGS. 9 and 10 are the same as those in FIG.
In this embodiment, the power consumption associated with extra charge and discharge of the liquid crystal display panel can be reduced, so that the power consumption can be reduced, and the first common voltage (VcomH1) on the high potential side and the high potential can be reduced. The amplifier circuit that outputs the second common voltage on the side (VcomH2), the first common voltage on the low potential side (VcomL1), and the second common voltage on the low potential side (VcomL2) may be one. As a result, it is possible to reduce the number of amplifier circuits and reduce power consumption.

[Example 3]
FIG. 11 is a block diagram illustrating a schematic configuration of an example of a source driver (SD) of the liquid crystal display module according to the first embodiment.
The display data 42 is taken into the memory writing circuit 43 and then written at a predetermined address in the frame memory 44.
Next, the display data stored in the frame memory 44 is read by the memory reading circuit 45 in accordance with the driving timing of the liquid crystal display panel, and is temporarily held in the data latch circuit 46 as display data for one row.
On the other hand, the gradation voltage generation circuit 47 is a circuit that generates a plurality of gradation voltages 48 necessary for gradation display, and generates, for example, 64 gradation voltages 48.
Next, the selector (also referred to as a decoder) 49 selects one gradation voltage from among the 64 gradation voltages 48 according to the display data held in the data latch circuit 46, and the video line (SL). ).

In a liquid crystal display module having two liquid crystal display panels (PNL1, PNL2) sharing a video line as shown in FIGS. 1 and 2, when only one of the liquid crystal display panels is displayed, a display operation is performed. In order to drive the liquid crystal display panel, a gradation voltage is applied to the video line.
Here, because the parasitic capacitance between the source and drain of the thin film transistor 10 also applies a voltage to the liquid crystal display panel set to non-display, the driving of the liquid crystal display panel set to non-display is completely stopped. I can't.
For this reason, it is necessary to perform black or white display for all the pixels of the liquid crystal display panel with the non-display setting.
Here, when displaying only black or white, the gradation voltage output from the source driver (SD) to the video line needs only the upper and lower binary values, so as shown in FIGS. When the gradation voltage output from the gradation voltage generation circuit 47 is supplied to the selector 49 via the amplifier circuit (or buffer circuit) (BA), the gradation voltage of V1 and the level of V64 are supplied. Other than the tone amplifier circuit (the amplifier circuit surrounded by B in FIGS. 12 and 13) can be stopped.
Further, as shown in FIG. 12, when the ladder resistor (R) is used, the ladder resistor (R) can be separated by the switching element (SWR).
As described above, the amplifier circuit (amplifying the gradation voltage output from the gradation voltage generation circuit 47 in the non-display period of the first liquid crystal display panel (PNL1) or the second liquid crystal display panel (PNL2)) ( By separating the BA) or the ladder resistance (R), it is possible to reduce the power consumption when the display operation is performed only on one liquid crystal display panel.
In order to perform the above-described operation, in the state where the display periods of the first and second liquid crystal display panels (PNL1, PNL2) are set, the liquid crystal display panel set to non-display is set to MPU using an instruction signal. Set from.
Accordingly, the amplifier circuit (BA) that amplifies the gradation voltage output from the gradation voltage generation circuit 47 or the ladder resistor (R) is turned off during the non-display period of the liquid crystal display panel set to non-display. Control to release.
Thus, in the non-display period, the amplifier circuit (BA) that amplifies the gradation voltage output from the gradation voltage generation circuit 47 or the ladder resistor (R) automatically stops, so that one liquid crystal When performing display operation only on the display panel, it is possible to reduce power consumption.

[Example 4]
When driving two liquid crystal display panels (PNL1, PNL2) sharing a video line as shown in FIGS. 1 and 2, power consumption differs depending on the driving method of the liquid crystal display panel.
The booster circuit has different boosting capability depending on the boosting clock frequency, the driving MOS size of the booster circuit, and the like, and the self-power consumption varies depending on the capability.
Therefore, in this embodiment, drive setting of the booster circuit for each liquid crystal display panel is performed, and the drive of the booster circuit is switched during the display period of each liquid crystal display panel.
FIGS. 14A to 14C are diagrams for explaining the booster circuit according to the present embodiment. Note that the booster circuit shown in FIGS. 14A to 14C is a booster circuit that boosts the input voltage of Vin twice.
The feature of the booster circuit of this embodiment is that two MOS transistors TM1 and TM2 are connected in parallel as switching elements (SW1 to SW4).
Here, when the normal mode shown in FIG. 14B is used as a reference, in the low power mode shown in FIG. 14A, one MOS transistor (TM1) constituting the switching element of the booster circuit is stopped. As a result, power consumption can be reduced.
In the high power mode shown in FIG. 14C, it is possible to cope with a large load current by driving two booster circuits shown in FIG. 14B in a complementary manner.
In FIG. 14C, the gate width of one MOS transistor constituting the switching elements (SW11 to SW14) is equal to that of the two MOS transistors (TM1, TM2) constituting the switching elements (SW1 to SW4). Equal to the sum of gate widths.
For this reason, for example, when the first liquid crystal display panel (PNL1) is driven by the one-line common inversion method and the second liquid crystal display panel (PNL2) is driven by the one-frame common inversion method, the current consumption is large. During the display period of the first liquid crystal display panel (PNL1), the booster circuit is driven in the high power mode, and normal during the display period of the second liquid crystal display panel (PNL2) that performs frame inversion with relatively low power consumption. Driving can be performed depending on the mode.

Thus, the first liquid crystal display panel in one frame is set by setting the booster circuit suitable for the power consumption in the respective display periods of the first and second liquid crystal display panels (PNL1, PNL2). In the display period of (PNL1) and the display period of the second liquid crystal display panel (PNL2), the optimum booster circuit operation is performed, and the power consumption of the liquid crystal display module can be reduced.
As another example, when only one of the first liquid crystal display panel (PNL1) or the second liquid crystal display panel (PNL2) performs a display operation, the non-display setting liquid crystal display panel In the display period, the power consumption can be similarly reduced by setting the booster circuit in the low power mode and delaying the cycle of the booster clock.
FIG. 15 shows a more specific configuration of the booster circuit shown in FIG.
In order to obtain the circuit shown in FIG. 14B, the switching element (SW2) and the switching element (SW4) in FIG. 15 are turned on. As a result, the voltage of the input power source Vin is charged in the booster capacitor (C11).
Next, the switching element (SW2) and the switching element (SW4) shown in FIG. 15 are turned off, the switching element (SW3) is turned on, and the input power supply Vin is applied to the boosting capacitor (C11). SW1) is turned on to charge the storage capacitor (Cout). In this case, it goes without saying that each switching element (SW1) is composed of two MOS transistors connected in parallel.
In this way, a voltage twice as large as the input power source Vin is held in the holding capacitor (Cout).

As described above, according to the liquid crystal display modules of the above-described embodiments, optimum driving for the first liquid crystal display panel (PNL1) and the second liquid crystal display panel (PNL2) is performed by the individual alternating drive method. The method can be adopted, and the power consumption can be reduced.
Further, when displaying only one of the first and second liquid crystal display panels (PNL1, PNL2), the unnecessary amplifier is stopped during the display period of the liquid crystal display panel set to non-display. It is possible to reduce power consumption and reduce power consumption.
In addition, when the display is unnecessary, the common voltage (Vcom) is turned off from alternating current, so that the power required for charging and discharging the liquid crystal display panel can be reduced. Can be generated by a single amplifier circuit, so that power consumption can be reduced.
Further, the driving of the booster circuit can be optimized in the display period of each liquid crystal display panel according to the driving method of the first liquid crystal display panel (PNL1) and the second liquid crystal display panel (PNL2). Therefore, it is possible to reduce power consumption.
As mentioned above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

DESCRIPTION OF SYMBOLS 10 Thin-film transistor 12 Pixel electrode 15 Common electrode 43 Memory write circuit 44 Frame memory 45 Memory read-out circuit 46 Data latch circuit 47 Gradation voltage generation circuit 48 Gradation voltage 49 Selector (decoder)
PNL1, PNL2 LCD panel FPC Flexible wiring board SL Video line (or drain line)
GL scan line (or gate line)
SUB1, SUB2 Glass substrate DRV1, DRV2 Drive circuit CNTL Controller SD Source driver GD Gate driver PC Power supply circuit MPU Central processing unit (Microprocessing Unit)
RST, RET register CNT counter AMP1, AMP2, BA amplifier circuit S1-S6, SWR, SW1-SW4, SW11-SW14 switching element V1-V4, VC1, VC2 terminal C1-C4, C11, Cout capacitive element TM1, TM2 MOS transistor

Claims (2)

A first liquid crystal display panel;
A second liquid crystal display panel;
A drive circuit provided in the first liquid crystal display panel;
An output terminal provided in the first liquid crystal display panel and supplied with a signal output from the drive circuit;
A connection wiring for connecting the output terminal and the second liquid crystal display panel;
The drive circuit has a booster circuit unit,
The booster circuit unit includes a first booster circuit and a second booster circuit,
The first booster circuit includes a switching element in which a plurality of transistor elements are connected in parallel,
The booster circuit unit includes a first mode in which the first booster circuit and the second booster circuit are complementarily operated by an external signal input from outside the liquid crystal display device, and the first booster circuit. And a third mode in which the first booster circuit is operated by using one transistor element of the plurality of transistor elements as a switching element of the first booster circuit. A liquid crystal display device which can be changed to   2. The liquid crystal according to claim 1, wherein the video line of the second liquid crystal display panel is connected to the drive circuit via the connection wiring and the video line of the first liquid crystal display panel. Display device.

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