JP5022651B2 - Display device - Google Patents

Description

  The present invention relates to a display device, and more particularly to a technique that is effective when applied to a display device that transfers digital signals between drive circuits.

2. Description of the Related Art A TFT (Thin Film Transistor) type liquid crystal display module using a thin film transistor as an active element is widely used as a display device such as a notebook personal computer. These liquid crystal display devices include a liquid crystal display panel and a drive circuit that drives the liquid crystal display panel.
In such a liquid crystal display module, for example, as described in Patent Document 1 below, a digital signal (for example, display data or a clock) is supplied only to the head drive circuit of the cascade-connected drive circuits. A method of transferring digital signals sequentially through the drive circuit (hereinafter referred to as a digital signal sequential transfer method) is known as the other drive circuit.
In the liquid crystal display device described in Patent Document 1 below, a semiconductor integrated circuit device (IC) that constitutes a drive circuit is directly mounted on a substrate (for example, a glass substrate) that constitutes a liquid crystal display panel. The power supply voltage of each gate driver is supplied from the power supply circuit via the power supply wiring on the substrate of the liquid crystal display panel.

As prior art documents related to the invention of the present application, there are the following.
JP-A-6-13724

In the liquid crystal display device described in Patent Document 1, when power is supplied from only one side to the power supply wiring on the substrate of the liquid crystal display panel, the larger the size of the liquid crystal display panel, the more the liquid crystal display panel has. The resistance of the power supply wiring on the substrate increases, and for example, the power supply voltage such as the gate-on voltage (Vgh) supplied to each gate driver becomes uneven due to a voltage drop due to the wiring resistance of the power supply wiring.
When the supplied power supply voltage becomes uneven in each gate driver, the on-resistance of the thin film transistor (TFT) changes, the video voltage written in each pixel electrode (ITO1) becomes uneven, and display unevenness occurs.
For this reason, in a liquid crystal display panel having a panel size of 12.1 inches or more, a circuit board is used to supply power from both sides to the power supply wiring on the substrate of the liquid crystal display panel, and supply power voltage supplied to each gate driver. I try to stabilize it.
On the other hand, there are some demands for cost reduction in the liquid crystal display module, but the circuit board is expensive, so the liquid crystal display module adopting the digital signal sequential transfer method as described above is much lower cost. There was a problem that it was difficult to make it easier.
The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to provide a technique capable of reducing the cost of the display device as compared with the prior art. .
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
(1) a display panel (for example, a liquid crystal display panel) having a plurality of scanning lines and n (n ≧ 2) scanning line driving circuits for sequentially applying a selected scanning voltage to the plurality of scanning lines; A display device comprising: a display control circuit for controlling and driving a scanning line driving circuit; and a power supply circuit for outputting a driving voltage to each of the scanning line driving circuits, wherein the periphery of the first side of the substrate constituting the display panel The power supply circuit is connected to one end of the power supply wiring layer, and each of the scanning line driving circuits is provided at a peripheral portion of the first side of the substrate constituting the display panel. The n scanning line drive circuits are mounted in the order of decreasing distance from each of the scan line drive circuits to one end of the power supply wiring layer. When the second scanning line driving circuit is used, When the (2 ≦ k ≦ n) th scanning line driving circuit sequentially applies a selection scanning voltage to the scanning lines, the driving voltage output from the power supply circuit to the kth scanning line driving circuit is The absolute value of the driving voltage is larger than the driving voltage output from the power supply circuit to the (k-1) th scanning line driving circuit, and the kth scanning line driving circuit has the (k-1) th scanning line. In the driving circuit, the selective scanning voltage is sequentially applied to the scanning lines after a predetermined delay time from the application of the selective scanning voltage to the last scanning line.

(2) In (1), the display control circuit counts the number of shift clocks, a signal generation circuit that outputs a shift clock to each of the scanning line driving circuits, and sequentially applies a selected scanning voltage to the scanning lines. A discrimination circuit for discriminating which scan line drive circuit is applied, and the display control circuit sequentially selects the scan lines based on a discrimination result in the discrimination circuit. The scanning line driving circuit to which the scanning voltage is applied detects a time point when the (k-1) th scanning line driving circuit shifts to the kth scanning line driving circuit, and outputs the detected time from the power supply circuit to each scanning line driving circuit. The voltage value of the driving voltage to be changed is changed.
(3) In (2), the signal generation circuit of the display control circuit outputs a frame start signal to each of the scanning line driving circuits, and the shift clock and the frame start output from the display control circuit The signal is input to the first scan drive circuit, and the shift clock input to the jth (1 ≦ j ≦ n−1) th scan drive circuit propagates through the jth scan drive circuit. The shift clock output from the jth scan drive circuit and output from the jth scan drive circuit is the jth scan drive at the periphery of the first side of the substrate constituting the display panel. Is input to the (j + 1) th scan drive circuit via a first wiring layer provided between the circuit and the (j + 1) th scan drive circuit, and each of the scan drive circuits is operated by a frame start signal. Before and before A shift register whose shift operation is controlled by a shift clock, and a shift pulse at the last stage of the shift register of the j-th scan driving circuit is generated at the periphery of the first side of the substrate constituting the display panel A frame start signal is input to the (j + 1) th scan drive circuit via a second wiring layer provided between the jth scan drive circuit and the (j + 1) th scan drive circuit. One wiring layer has a first delay line for delaying the shift clock for the predetermined delay time or longer, and the second wiring layer is a second delay line for delaying the shift pulse for the predetermined delay time or longer. Have
Alternatively, each scanning drive circuit includes a delay circuit that delays a shift clock output to the first wiring layer and a shift pulse output to the second wiring layer for the predetermined delay time or longer.

(4) In (2), the display control circuit outputs a frame start signal to each of the scanning line drive circuits, and the frame start signal output from the display control circuit is a first scan drive. Each of the scan driving circuits has a shift register whose operation is started by a frame start signal and whose shift operation is controlled by the shift clock, and is jth (1 ≦ j ≦ n−1) th. The shift pulse at the final stage of the shift register of the scan drive circuit is generated between the jth scan drive circuit and the (j + 1) th scan drive circuit at the periphery of the first side of the substrate constituting the display panel. The shift clock that is input as a frame start signal to the (j + 1) th scan driving circuit via the second wiring layer provided therebetween, and output from the display control circuit, passes through the signal wiring. The display control circuit, which is input to each of the scanning drive circuits, applies a selected scanning voltage to the scanning lines sequentially. The scanning line driving circuit drives the kth scanning line from the (k−1) th scanning line driving circuit. When the time point of transition to the circuit is detected, the shift clock is delayed for the predetermined delay time or longer.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the display device of the present invention, the cost can be reduced as compared with the conventional case.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
In all the drawings for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof is omitted.
[Liquid crystal display module of digital signal sequential transfer system which is the premise of the present invention]
First, a digital signal sequential transfer type liquid crystal display module which is a premise of the present invention will be described.
FIG. 7 is a block diagram showing a basic configuration of a conventional liquid crystal display module adopting a digital signal sequential transfer system.
The liquid crystal display panel 100 includes a TFT substrate on which a pixel electrode (PIX), a thin film transistor (TFT), and the like are formed and a filter substrate on which a counter electrode, a color filter, and the like are formed with a predetermined gap therebetween, The two substrates are bonded together by a seal material provided in the vicinity of the peripheral edge between the two substrates, and the liquid crystal is sealed and sealed inside the seal material between the two substrates from the liquid crystal sealing port provided in a part of the seal material. In addition, a polarizing plate is attached to the outside of both substrates.

Each subpixel has a pixel electrode (PIX) and a thin film transistor (TFT), and intersects a plurality of scanning lines (or gate lines) (G) and video lines (or drain lines, source lines) (D). It is provided corresponding to the part to do.
Further, since the liquid crystal layer is sandwiched between the pixel electrode (PIX) and the counter electrode (CT), the liquid crystal capacitance (C _LC ) is interposed between the pixel electrode (PIX) and the counter electrode (CT). Is formed. In the example shown in FIG. 7, in order to hold the potential of the pixel electrode (PIX), a holding capacitor (C _ST ) is provided for each subpixel between the pixel electrode (PIX) and the counter electrode (CT). Forming.
Further, in FIG. 7, only one pixel electrode (PIX) is illustrated, but a plurality of pixel electrodes (PIX), thin film transistors (TFTs), and storage capacitors (C _ST ) are provided in a matrix.
The thin film transistor (TFT) of each subpixel has a source connected to the pixel electrode (PIX), a drain connected to the video line (D), a gate connected to the scanning line (G), and a display voltage (gray scale) applied to the pixel electrode (PIX). Function as a switch for supplying voltage.
In the conventional liquid crystal display module shown in FIG. 7, the drain driver 130 and the gate driver 140 are provided on the periphery of two sides of a substrate (for example, a glass substrate) (SUB 1) constituting the TFT substrate of the liquid crystal display panel 100. Each is implemented.
The power supply circuit 120 and the display control circuit (or timing controller) 110 are mounted on a circuit board 150 disposed in the peripheral portion of the liquid crystal display panel 100, respectively.

The display control circuit 110 is composed of one semiconductor integrated circuit (LSI), and each display control signal and display data of a clock signal, a display timing signal, a horizontal synchronization signal, and a vertical synchronization signal transmitted from the computer body side. The drain driver 130 and the gate driver 140 are controlled and driven based on the data (R, G, B).
A digital signal (display data, clock number, etc.) 132 sent from the display control circuit 110 and a gradation reference voltage 133 supplied from the power supply circuit 120 are a flexible printed circuit board (hereinafter simply referred to as an FPC board) (FPCD). ) Through the internal signal line in each drain driver 130 and the transmission line (wiring layer on the glass substrate) between each drain driver 130, and each drain driver 130. Is input. The power supply voltage of each drain driver 130 is supplied from the power supply circuit 120 via the power supply line 131 on the FPC board (FPCS).
Similarly, a digital signal (frame start signal, shift clock, etc.) 141 sent from the display control circuit 110 is input to the top gate driver 140 via the FPC board (FPCD), and the internal signal in each gate driver 140 is internalized. The signal line and the transmission line (wiring layer on the glass substrate) between each gate driver 140 are propagated and input to each gate driver 140.
Further, a power supply voltage such as a gate-on voltage (Vgh) of each gate driver 140 is supplied from the power supply circuit 120 via the power supply wiring 142 on the substrate of the liquid crystal display panel 100.

[Example]
The basic configuration of the liquid crystal display module of the embodiment of the present invention is the same as the conventional liquid crystal display module shown in FIG.
FIG. 1 is a diagram showing a basic configuration of the liquid crystal display module of the present embodiment.
As shown in FIG. 1, in this embodiment, the display control circuit 110 includes a signal generation circuit 10, a counter circuit 11, and a decoder circuit 12.
The signal generation circuit 10 generates a frame start signal (FLM) and a shift clock (CL3) and outputs them to each gate driver 140.
The counter circuit 11 counts the number of shift clocks, and the decoder circuit 12 decodes the count number in the counter circuit 11.
Each gate driver (scanning line driving circuit of the present invention) 140 shown in FIG. 1 applies a selective scanning voltage (that is, a gate-on voltage (Vgh)) sequentially to the scanning line (G), and applies each display line. A scan operation is performed to turn on a thin film transistor (TFT).
Since this scanning operation is performed based on the shift clock (CL3), the number of scanning lines (G) on which each gate driver 140 performs the scanning operation, that is, the scanning lines (G) to which the sequential scanning voltage is sequentially applied. If the number is the same, it is possible to determine which gate driver 140 in the GDV1 to GDV3 in FIG. 1 is executing the scanning operation by counting the shift clock (CL3).

In the example shown in FIG. 7, in order to stabilize the power supply voltage supplied to each gate driver 140, an FPC board (FPCG) is provided, and both ends of the power supply wiring 142 on the substrate of the liquid crystal display panel 100 are connected to the power supply circuit 120. Power is supplied from both sides of the power supply wiring 142 on the substrate of the liquid crystal display panel 100. In contrast, in this embodiment, power is supplied to the power supply wiring 142 on the substrate of the liquid crystal display panel 100 only from one side.
However, when power is supplied from only one side to the power supply wiring 142 on the substrate of the liquid crystal display panel 100, a power supply such as a gate on voltage (Vgh) supplied to each gate driver 140 due to a voltage drop due to the wiring resistance of the power supply wiring 142 The voltage is uneven.
Therefore, in the present embodiment, the decoder circuit 12 decodes the count number in the counter circuit 11 so that the gate driver 140 that executes the scanning operation is changed from the gate driver 140 of the GDV1 in FIG. 1 to the gate of the GDV2 in FIG. 1 is detected, and the gate driver 140 of the GDV1 to GDV3 of FIG. 1 is detected from the power supply circuit 120 in accordance with the detection of the transition point from the gate driver 140 of the GDV2 of FIG. 1 to the gate driver 140 of the GDV3 of FIG. The voltage value of the drive voltage (gate-on voltage, power supply voltage, etc.) to be output is changed.

For example, as shown in FIG. 2, when the gate driver 140 of the GDV1 in FIG. 1 is performing a scan operation, the gate-on voltage of Vgh1 is output from the power supply circuit 120 to the gate driver 140 of the GDV1, 1, when the gate driver 140 of the GDV2 executes the scanning operation, the gate-on voltage of Vgh2 (| Vgh2 |> | Vgh1 |) is output from the power supply circuit 120 to the gate driver 140 of the GDV2, and the GDV3 of FIG. When the gate driver 140 performs a scan operation, the power supply circuit 120 outputs a gate-on voltage of Vgh3 (| Vgh3 |> | Vgh2 |> | Vgh1 |) to the gate driver 140 of the GDV3.
That is, in this embodiment, when power is supplied to the power supply wiring 142 on the substrate of the liquid crystal display panel 100 from only one side, the gate-on voltage (Vgh) dropped due to the wiring resistance of the power supply wiring 142 is almost equal in each gate driver 140. The voltage value of the drive voltage output to each gate driver 140 is selected so as to have the same voltage value.
As a result, in this embodiment, it is possible to prevent display unevenness caused by uneven driving voltages supplied to the gate drivers 140.
Therefore, in this embodiment, power supply from both sides is unnecessary, and as shown in FIG. 7, an FPC board (FPCG) is unnecessary, and the size of the circuit board 150 can be made smaller than the case shown in FIG. Therefore, the cost can be reduced.

However, for example, as shown in FIG. 3, when the gate-on voltage output from the power supply circuit 120 to the gate driver 140 is changed from Vgh1 to Vbh2, the gate-on voltage changes from Vbh1 to Vbh2 due to the distributed impedance of the power supply wiring 142. The gate-on voltage of Vbh2 is reached after a delay time of Tc from the time point (T1).
Therefore, when the gate driver 140 performing the scan operation shifts from the gate driver 140 of the GDV1 of FIG. 1 to the gate driver 140 of the GDV2 of FIG. 1, for example, the scan operation is the gate driver of the GDV1 of FIG. When the operation is continuously performed from 140 to the gate driver 140 of the GDV2 of FIG. 2, the gate-on voltage at the time of the first scan operation of the gate driver 140 of the GDV2 of FIG. 2 is a voltage during the transition to the gate-on voltage of Vgh2. It becomes.
Thus, the video voltage written by the first scan operation of the gate driver 140 of the GDV2 in FIG. 2 is different from the video voltage written by the second transition scan operation of the gate driver 140 of the GDV2 in FIG. Therefore, display unevenness occurs in one display line in which the video voltage is written by the first scan operation of the gate driver 140 of the GDV2 in FIG.

Therefore, in this embodiment, for example, as shown in FIG. 4, when the gate driver 140 performing the scanning operation shifts from the GDV1 gate driver 140 in FIG. 1 to the GDV2 gate driver 140 in FIG. The gate driver 140 of GDV2 executes the scan operation after a predetermined delay time (Tb) has elapsed since the last scan operation of the gate driver 140 of GDV1. Here, the delay time of Tb is longer than the delay time of Tc (Tc <Tb).
In FIG. 4, Ta is a time during which a thin film transistor (TFT) is turned on for each display line, and GDR1-255 is a GDR1-255 scanning operation from the last in the gate driver 140 of GDV1. 256 is the last scan operation in the gate driver 140 of the GDV1, GDR2-1 is the first scan operation in the gate driver 140 of the GDV2, and GDR2-2 is the second scan operation in the gate driver 140 of the GDV2. Represents a scan operation.
As a result, when the gate driver 140 performing the scan operation shifts from the gate driver 140 of the GDV1 of FIG. 1 to the gate driver 140 of the GDV2 of FIG. 1, for example, 1 of the gate driver 140 of the GDV2 of FIG. Since the second scan operation is performed after the gate-on voltage has shifted to the gate-on voltage of Vgh2, it is possible to prevent the display unevenness of one display line described above.

In order to execute the scan operation after the predetermined delay time (Tb) elapses, for example, the method shown in FIGS. 5-1 and 5-2 is executed.
FIG. 5A is a block diagram illustrating a schematic configuration of the gate driver 140 of the present embodiment.
In general, the gate driver 140 includes a shift register 40 as shown in FIG. The shift register 40 is enabled when a frame start signal (FLM) is input, and sequentially performs shift operations by transferring shift pulses based on the shift clock (CL3). The last-stage shift pulse is input to the next-stage gate driver 140 as a frame start signal (FLM).
A shift clock (CL3) and a frame start signal (FLM) are input to the first gate driver 140 (GDV1 gate driver in FIG. 1), but the shift clock (CL3) and the frame start signal described above are input. (FLM) (that is, the last-stage shift pulse of the shift register 40 of the first gate driver 140) is input to the second gate driver 140 (GDV2 gate driver in FIG. 1).

In this case, the shift clock (CL3) is the glass substrate (SUB1) constituting the liquid crystal display panel 100 between the internal wiring of the first gate driver 140 and the first gate driver 140 and the second gate driver 140. The signal is input to the second gate driver 140 via the upper first wiring layer.
The last-stage shift pulse of the shift register 40 of the first gate driver 140 is generated on the glass substrate (SUB1) constituting the liquid crystal display panel 100 between the first gate driver 140 and the second gate driver 140. Is input to the second gate driver 140 through the second wiring layer.
In the present embodiment, the gate driver 140 has a delay circuit 41, and the delay circuit 41 delays the input shift clock (CL3-in) by a predetermined delay time (Tb), for example, to shift the next stage. Output as a clock (CL3-in).
Similarly, the delay circuit 41 delays the last stage shift pulse of the shift register 40 by, for example, a predetermined delay time (Tb) and outputs it as the next frame start signal (FLM-in). Thereby, it is possible to prevent the display unevenness of one display line described above.

In the method shown in FIG. 5A, the shift pulse (CL3) and the frame start signal (FLM) are delayed by the common delay circuit 41. For example, the delay processing of the shift clock is performed by the display control circuit 110. You may go.
The method shown in FIG. 5B is the shift clock (CL3) between the first gate driver 140 and the second gate driver 140, and the last stage shift of the shift register 40 of the first gate driver 140. For example, the pulse is transmitted through a delay line 43 that is delayed by a predetermined delay time (Tb).
For example, the delay line 43 is configured by appropriately adjusting the lengths of the first and second wiring layers on the glass substrate (SUB1) between the first gate driver 140 and the second gate driver 140. Is possible.
The method shown in FIG. 5B can also prevent the display unevenness of one display line described above.

In order to execute the scanning operation after the above-described predetermined delay time (Tb) has elapsed, for example, the following method may be used.
FIG. 6A is a diagram illustrating a basic configuration of a modified example of the present embodiment.
As shown in FIG. 6A, in the modification of the present embodiment, the signal generation circuit 10 of the display control circuit 110 includes an output control signal (bar) in addition to the frame start signal (FLM) and the shift clock (CL3). OE) is also generated and output to each gate driver 140. Here, the frame start signal (FLM) is input to the first gate driver 140 (GDV1 gate driver in FIG. 6A), but the shift clock (CL3) is output controlled via the signal wiring 143. The signal (bar OE) is input to each gate driver 140 via the signal wiring 144.
FIG. 6B is a timing chart of the basic circuit shown in FIG. In FIG. 6B, FLM2 indicates a frame start signal input to the second gate driver 140 (GDV2 gate driver in FIG. 6A). This FLM2 is transmitted from the first gate driver 140. Is output.
GDR1-255 is the last scan operation in the gate driver 140 of the GDV1, GDR1-256 is the last scan operation in the gate driver 140 of the GDV1, and GDR2-1 is the gate of the GDV2. GDR2-2 represents the first scan operation in the driver 140, and GDR2-2 represents the second scan operation in the gate driver 140 of GDV2.

As shown in FIG. 6B, when the gate driver 140 performing the scanning operation shifts from the gate driver 140 of GDV1 of FIG. 1 to the gate driver 140 of GDV2 of FIG. After the shift clock (CL3) for the last scan operation of the gate driver 140 of GDV1 is output, the delay time of Td (Td> Tc) larger than the delay time of Tb is delayed, and then the gate driver 140 of GDV2 The shift clock (CL3) for the first scan operation is output.
Further, the output control signal (bar OE) is output from the time when the last scan operation of the gate driver 140 of the GDV1 is completed until the time when the shift clock (CL3) for the first scan operation of the gate driver 140 of the GDV2 is output. It becomes effective, and the operation of each gate driver 140 is temporarily stopped.
Accordingly, the first scan operation of the gate driver 140 of the GDV2 in FIG. 6A is executed after the gate-on voltage has shifted to the gate-on voltage of Vgh2, so that the display unevenness of one display line described above is performed. Can be prevented.
In the above description, the embodiment in which the present invention is applied to a liquid crystal display device has been described. However, the present invention is not limited to this, and the present invention can also be applied to an organic EL display device or the like. .
Although the invention made by the present inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. Of course.

It is a figure which shows the basic composition of the liquid crystal display module which employ | adopts the digital signal sequential transfer system of the Example of this invention. In the liquid crystal display module of the Example of this invention, it is a conceptual diagram for demonstrating the drive voltage output to each gate driver from a power supply circuit. FIG. 4 is a conceptual diagram for explaining a transition state of a drive voltage output to each gate driver when a drive voltage output from the power supply circuit to each gate driver changes in the liquid crystal display module according to the embodiment of the present invention. . FIG. 5 is a conceptual diagram for explaining a scan operation between adjacent gate drivers in the liquid crystal display module according to the embodiment of the present invention. It is a conceptual diagram for demonstrating one method for implement | achieving the scanning operation | movement shown in FIG. It is a conceptual diagram for demonstrating the other method for implement | achieving the scanning operation | movement shown in FIG. It is a figure which shows the basic composition of the modification of the liquid crystal display module which employ | adopts the digital signal sequential transfer system of the Example of this invention. It is a figure which shows the timing chart in the method shown to FIGS. It is a block diagram which shows the basic composition of the conventional liquid crystal display module which employ | adopts a digital signal sequential transfer system.

Explanation of symbols

40 shift register 41 delay circuit 43 delay line 100 liquid crystal display panel 110 display control circuit (timing controller)
120 Power supply circuit 130 Drain driver 131 Power supply line 132 Digital signal (display data, clock number, etc.)
133 gradation reference voltage 140 gate driver 141 digital signal (frame start signal (FLM), shift clock (CL3), etc.)
142 power supply wiring 143, 144 signal wiring 150 circuit board FPCD, FPCS, FPCD flexible printed wiring board SUB1 substrate PIX pixel electrode TFT thin film transistor G scanning line (or gate line)
D Video line (or drain line, source line)
C _LC liquid crystal capacitor C _ST holding capacitor CT Counter electrode

Claims (6)

A display panel having a plurality of scanning lines and n (n ≧ 2) scanning line driving circuits for sequentially applying a selection scanning voltage to the plurality of scanning lines;
A display control circuit for controlling and driving each of the scanning line driving circuits;
A display device comprising a power supply circuit that outputs a driving voltage to each of the scanning line driving circuits,
A power wiring layer provided in a peripheral portion of the first side of the substrate constituting the display panel;
The power supply circuit is connected to one end of the power supply wiring layer,
Each of the scanning line driving circuits is mounted on the peripheral portion of the first side of the substrate constituting the display panel, and a driving voltage is applied from the power wiring layer.
When the n scanning line driving circuits are first to nth scanning line driving circuits in order of decreasing distance from each scanning line driving circuit to one end of the power supply wiring layer, k (2 ≦ k ≦ When the n) th scanning line driving circuit sequentially applies the selected scanning voltage to the scanning lines, the driving voltage output from the power supply circuit to the kth scanning line driving circuit is from the power supply circuit to the ( k-1) The absolute value of the driving voltage is larger than the driving voltage output to the first scanning line driving circuit,
The kth scanning line driving circuit sequentially applies the scanning line to the scanning line after a predetermined delay time from the end of the application of the selected scanning voltage to the last scanning line in the (k−1) th scanning line driving circuit. A display device characterized by applying a selective scanning voltage. The display control circuit includes a signal generation circuit that outputs a shift clock to each scanning line driving circuit;
A discriminating circuit that counts the number of shift clocks and discriminates which scanning line driving circuit the scanning line driving circuit that sequentially applies the selected scanning voltage to the scanning lines;
The display control circuit includes: a scanning line driving circuit that sequentially applies a selected scanning voltage to the scanning lines based on a determination result in the determination circuit; the (k−1) th scanning line driving circuit to the kth scanning line; 2. The display device according to claim 1, wherein a point in time of transition to the drive circuit is detected, and a voltage value of a drive voltage output from the power supply circuit to each of the scanning line drive circuits is changed. The signal generation circuit of the display control circuit outputs a frame start signal to each of the scanning line driving circuits;
The shift clock and the frame start signal output from the display control circuit are input to a first scan driving circuit,
The shift clock input to the jth (1 ≦ j ≦ n−1) th scan drive circuit propagates through the jth scan drive circuit and is output from the jth scan drive circuit,
The shift clock output from the j-th scan drive circuit includes a j-th scan drive circuit and a (j + 1) -th scan drive circuit in the periphery of the first side of the substrate constituting the display panel. Are input to the (j + 1) th scan driving circuit via a first wiring layer provided between
Each of the scan driving circuits has a shift register that starts operation by a frame start signal and whose shift operation is controlled by the shift clock,
The shift pulse at the final stage of the shift register of the jth scan driving circuit is the jth scan driving circuit and the (j + 1) th scan in the periphery of the first side of the substrate constituting the display panel. A frame start signal is input to the (j + 1) th scan driving circuit via the second wiring layer provided between the driving circuit and the driving circuit.
The first wiring layer has a first delay line that delays the shift clock for the predetermined delay time or longer.
The display device according to claim 2, wherein the second wiring layer includes a second delay line that delays the shift pulse for the predetermined delay time or longer. The display control circuit outputs a frame start signal to each of the scanning line driving circuits;
The shift clock and the frame start signal output from the display control circuit are input to a first scan driving circuit,
The shift clock input to the jth (1 ≦ j ≦ n−1) th scan drive circuit propagates through the jth scan drive circuit and is output from the jth scan drive circuit,
The shift clock output from the j-th scan drive circuit includes a j-th scan drive circuit and a (j + 1) -th scan drive circuit in the periphery of the first side of the substrate constituting the display panel. Are input to the (j + 1) th scan driving circuit via a first wiring layer provided between
Each of the scan driving circuits has a shift register that starts an operation by a frame start signal and controls a shift operation by the scan shift clock,
The shift pulse at the final stage of the shift register of the jth scan driving circuit is the jth scan driving circuit and the (j + 1) th scan in the periphery of the first side of the substrate constituting the display panel. A frame start signal is input to the (j + 1) th scan driving circuit via the second wiring layer provided between the driving circuit and the driving circuit.
3. The scan driving circuit includes a delay circuit that delays a shift clock output to the first wiring layer and a shift pulse output to the second wiring layer for the predetermined delay time or longer. The display device described in 1. The display control circuit outputs a frame start signal to each of the scanning line driving circuits;
The frame start signal output from the display control circuit is input to a first scan driving circuit,
Each of the scan driving circuits has a shift register that starts operation by a frame start signal and whose shift operation is controlled by the shift clock,
The shift pulse at the last stage of the shift register of the jth (1 ≦ j ≦ n−1) th scan driving circuit is the jth scan drive at the periphery of the first side of the substrate constituting the display panel. A frame start signal is input to the (j + 1) th scan driving circuit via a second wiring layer provided between the circuit and the (j + 1) th scan driving circuit,
The shift clock output from the display control circuit is input to the scan driving circuits via a signal wiring,
The display control circuit detects when a scanning line driving circuit that sequentially applies a selected scanning voltage to the scanning lines shifts from the (k−1) th scanning line driving circuit to the kth scanning line driving circuit. The display device according to claim 2, wherein the shift clock is delayed more than the predetermined delay time. The display device according to claim 1, wherein the display panel is a liquid crystal display panel.

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