JP2012168277A - Driver of liquid-crystal display panel and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow the effect of feedthrough to be reduced without adjusting values of voltage according to each grayscale based on feed-through voltage.SOLUTION: A driver of a liquid-crystal display panel has plural gate wires and plural source wires arranged so as to cross each other and includes a gate driver for sequentially applying gate voltage to the gate wires and a common driver for supplying common voltage to a common electrode. The common driver puts the common electrode into a floating state at the time when application of gate voltage by the gate driver is finished.

Description

  The present invention relates to a liquid crystal display panel driving device and a liquid crystal display device that can reduce or eliminate the influence of feedthrough.

In a liquid crystal display panel using a TFT (Thin Film Transistor), a TFT is provided at an intersection of a gate wiring and a source wiring, and a gate-on voltage _VGH is applied to the gate wiring to make the source and drain of the TFT conductive. In that state, a data voltage corresponding to display is applied to the source wiring, and data is written to a pixel (specifically, a pixel capacitor and a storage capacitor) connected to the drain.

FIG. 7 is a schematic diagram showing a TFT together with a pixel capacitance (liquid crystal capacitance) C _lc , a storage capacitance C _s , parasitic capacitances C _gd and C _sd .

FIG. 8 is a waveform diagram for explaining the feedthrough voltage. As shown in FIG. 8, when the voltage applied to the gate wiring changes from the gate-on voltage V _GH to the gate-off voltage V _GL , the common electrode (common electrode) is caused by the gate-drain parasitic capacitance (C _gd ). ) (Reference voltage V _COM ) as a reference, the pixel voltage decreases by the feedthrough voltage ΔV (decrease in absolute value). Hereinafter, a phenomenon in which the voltage decreases by the amount of the feedthrough voltage ΔV is referred to as feedthrough. Feed-through reduces image quality, such as increased flicker. FIG. 8 shows a waveform that illustrates an example of a driving method in which the polarity is inverted every frame so that a certain pixel is not subjected to DC.

  As shown in FIG. 8, in order to prevent image quality degradation due to feedthrough, the value of the common voltage is generally shifted by ΔV with respect to the center voltage.

  However, simply shifting the value of the common voltage eliminates the problem that the DC voltage component is applied to the liquid crystal due to the change in ΔV when the data gradation is different and the alignment state of the liquid crystal is different. I can't.

FIG. 9 is an explanatory diagram showing an optimum common voltage corresponding to the gradation in the VA liquid crystal display device. As shown in FIG. 9, since the feedthrough voltage varies depending on the gradation, the common voltage is adjusted to the gradation like the optimum common voltage (optimum V _COM ) which is a desirable common voltage shown in FIG. It is desirable to change accordingly. In FIG. 9, the black feedthrough voltage (ΔV (Black)) which is the minimum gradation and the white feedthrough voltage (ΔV (White)) which is the maximum gradation are clearly shown.

  However, it is difficult to change the common voltage according to the data gradation. Therefore, a driving method has been proposed in which the value of the data voltage corresponding to each gradation is adjusted based on the feedthrough voltage (see, for example, Patent Documents 1 and 2). In the driving methods described in Patent Documents 1 and 2, the common voltage is shifted by ΔV from the center voltage, and the value of the data voltage corresponding to each gradation is adjusted based on the feedthrough voltage.

JP-A-5-203918 (paragraphs 0006, 0013, 0014) JP 2008-216363 A (paragraphs 0046-0052)

  By using the driving methods described in Patent Documents 1 and 2, a problem that cannot be solved only by shifting the center voltage of the common voltage, that is, ΔV changes when the data gradation is different. The problem that the DC voltage component is applied can be solved.

  However, in the driving methods described in Patent Documents 1 and 2, the feedthrough is taken into consideration by obtaining the feedthrough voltage corresponding to each gradation in advance and adjusting the data voltage corresponding to each gradation based on the feedthrough voltage. Determine the optimum data voltage value. Then, the liquid crystal display panel is driven using a data voltage corresponding to each determined gradation.

  However, if some of the liquid crystal display panels have characteristics far from those of standard liquid crystal display panels due to variations in elements and circuits, the liquid crystal display panel is driven with the optimum data voltage. However, this is not always the case, and there may be a problem that the image quality is deteriorated and a DC voltage component is applied.

  Therefore, the present invention provides a liquid crystal display panel driving device and a liquid crystal display device capable of reducing the influence of feedthrough without adjusting the voltage value corresponding to each gradation based on the feedthrough voltage. For the purpose.

  A driving device for a liquid crystal display panel according to the present invention is arranged so that a plurality of gate wirings and a plurality of source wirings intersect, a gate driver for sequentially applying a gate voltage to the gate wirings, and a common voltage to the common electrodes. A driving device for a liquid crystal display panel having a common driver, wherein the common driver causes the common electrode to be in a floating state when application of a gate voltage (for example, application of a gate-on voltage) by the gate driver is completed. To do.

  The common driver preferably sets the common electrode in a floating state before a first predetermined period (for example, a period t1 shown in FIG. 4) before the end of application of the gate voltage by the gate driver.

  When the second predetermined period (for example, the period of t0 shown in FIG. 4) elapses after the gate driver finishes applying the gate voltage to the gate wiring of the nth row (n: natural number), (n + 1) ) It may be configured to start application of the gate voltage to the gate wiring of the row.

  A gate voltage can be output when a gate enable signal (eg, gate enable OE) is in an on state, and the gate driver uses the gate enable signal to gate to the gate wiring of the (n + 1) th row. You may be comprised so that the time which starts application of a voltage may be determined.

  The common driver preferably releases the floating state of the common electrode before a third predetermined period (for example, a period t2 shown in FIG. 4) before the gate driver starts applying the gate voltage.

  A liquid crystal display device according to the present invention includes the above driving device and a liquid crystal display panel.

  According to the present invention, the influence of feedthrough can be reduced without adjusting the voltage value corresponding to each gradation based on the feedthrough voltage.

The block diagram which shows the structural example of the liquid crystal display device to which the drive device by this invention was applied. The circuit diagram which shows the structural example of a common driver. The timing diagram which shows an example of the state of the control signal and gate voltage which are output with respect to a gate driver from a timing control circuit. FIG. 6 is a waveform diagram showing an example of a common electrode potential and a pixel electrode potential. The circuit diagram which shows TFT and a pixel typically. FIG. 6 is a waveform diagram showing a gate potential, a pixel electrode potential, and a common potential. FIG. 3 is a schematic diagram illustrating a pixel capacitor, a storage capacitor, and a parasitic capacitor of a TFT. The wave form diagram for demonstrating a feedthrough voltage. Explanatory drawing which shows the optimal common voltage according to a gradation.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration example of a liquid crystal display device on which a driving device according to the present invention is mounted. In the liquid crystal display device shown in FIG. 1, the liquid crystal display panel 10 has a large number of pixels 12 formed in a matrix. In order to form a pixel, a large number of gate lines 13 are provided in the horizontal direction (row direction), and a large number of source lines 14 are provided in the column direction so as to intersect the gate lines 13. A TFT 15 is formed at the intersection between the gate line 13 and the source line 14. The drain electrode 16 of the TFT 15 is connected to the pixel electrode.

A counter substrate (not shown) is provided at a position facing the substrate on which the gate wiring 13, the source wiring 14, and the pixel 12 are formed, and the liquid crystal is sandwiched between the substrate on which the pixel 12 is formed and the counter substrate. Has been. A common electrode (common electrode) 20 is formed on the counter substrate. The common driver 50 supplies a common voltage _VCOM to the common electrode 20, and the common electrode 20 is set to a common potential. In addition, since the liquid crystal can be regarded as an element having a capacitance electrically, FIG. 1 shows a capacitor 17 in which one end is connected to the pixel electrode and the other end has a common voltage _VCOM. ing.

The gate driver 40 drives the gate lines 13 line-sequentially based on a signal output from the control unit (timing control circuit) 60. The pixel electrode in the pixel connected to the selected gate line 13, that is, the gate line 13 to which the gate-on voltage V _GH is applied is applied to the data voltage (voltage corresponding to the data signal) by the source driver 30 via the source line 14. ) V _D is applied.

  The source driver 30, the gate driver 40, the common driver 50, and the timing control circuit 60 shown in FIG. 1 are components of a liquid crystal display panel driving device. The common driver 50 may be built in a power supply circuit (not shown).

FIG. 2 is a circuit diagram illustrating a configuration example of the common driver 50. The common driver 50 includes a buffer circuit 51 for supplying the common voltage V _COM to the common electrode 20. The buffer circuit 51 has a control terminal, and when the VCOM control signal input to the control terminal is turned on (high level), the output is set to a high impedance state. In this example, the ON state of the VCOM control signal is assumed to be a state where the signal level is high. When VCOM control signal inputted to the control terminal is OFF (low level), and supplies the common voltage V _COM to the common electrode 20. In this example, it is assumed that the OFF state of the VCOM control signal is a state where the signal level is low.

  With the common driver 50 having the configuration illustrated in FIG. 2, the output of the common driver 50 becomes high impedance during the period in which the VCOM control signal is on. As a result, the common electrode 20 enters a floating state (a state separated from the determined potential).

  FIG. 3 is a timing chart showing an example of the control signal output from the timing control circuit 60 to the gate driver 40 and the state of the gate voltage.

  As shown in FIG. 3, in this embodiment, the control signal output from the timing control circuit 60 to the gate driver 40 includes a gate start pulse STV corresponding to a signal indicating the start of one frame, and each selection period. Includes a gate clock CKV that changes from a low level to a high level, and a gate enable OE that indicates a gate voltage output permission period. In the present embodiment, the liquid crystal display panel 10 is driven by a line sequential driving method, and the selection period corresponds to a period for driving one line.

  When the gate clock CKV and the gate enable OE become high level after the gate start pulse STV is input (specifically, after the gate driver 40 becomes high level), the gate driver 40 applies the gate-on voltage to the gate wiring of the first row. Is applied. That is, driving of the first row is started. Thereafter, when the gate enable OE becomes low level, a gate-off voltage is applied to the gate wiring of the first row. That is, the gate voltage is turned off (corresponding to the end of application of the gate voltage). Thereafter, every time the gate clock CKV and the gate enable OE become high level, driving of the next row is started. In FIG. 3, the hatched portion corresponds to a period in which the gate enable OE is off, that is, a period in which no gate wiring is driven.

Next, the operation of the drive device of this embodiment will be described. FIG. 4 is a waveform diagram showing an example of the potential of the common electrode 20 and the potential of the pixel electrode. In the present embodiment, a common DC system in which the common voltage V _COM output from the common driver 50 is constant throughout the frame is taken as an example.

  As shown in FIG. 4, when the gate voltage of the nth row is turned off, a feedthrough voltage is generated. That is, the potential of the pixel electrode (the potential of the drain electrode 16) decreases.

  In the present embodiment, the common electrode 20 is in a floating state between the time when the gate voltage of the nth row is turned off and the time when the gate voltage of the (n + 1) th row is turned on (period t0). There is a period.

Specifically, as shown in FIG. 4, the VCOM control signal is on before and after the gate voltage of the nth row (n: natural number) is turned off. Therefore, the common electrode 20 is in a floating state. More specifically, the common electrode 20 is in a floating state before t1 before the gate voltage is turned off. Thereafter, when the period of t0 has elapsed after the gate voltage is turned off, the gate enable OE for the gate wiring of the next row is turned on (in this example, high level). Incidentally, VCOM control signal immediately before the period t0 elapses is turned off, the potential of the common electrode 20 approaches the common voltage V _COM.

  In the present embodiment, the common electrode 20 is in a floating state when the gate voltage of the nth row is turned off. Then, the potential of the common electrode 20 follows the decrease in the potential of the drain electrode 16. As shown in FIG. 4, the degree of decrease in the potential of the common electrode 20 is substantially equal to the degree of decrease in the potential of the drain electrode 16. As a result, the voltage applied to the pixel (pixel voltage) is kept substantially constant (value indicated by “v” in FIG. 4) even when feedthrough occurs. Therefore, the deterioration of image quality due to feedthrough is prevented.

  In order to realize the state shown in FIG. 4, the timing control circuit 60 outputs the gate start pulse STV, the gate enable OE, and the gate clock CKV to the gate driver 40 at the timing shown in FIG. The VOM control signal is output to the common driver 50.

  As shown in FIG. 4, the timing control circuit 60 turns on the VCOM control signal by t1 before the gate enable OE is turned off. Further, when the period of [t0-t2] elapses after the VCOM control signal is turned on, the VCOM control signal is turned off. That is, there is a time difference between the period t2 between the end time of the period in which the common electrode 20 is in the floating state and the time when the gate voltage of the (n + 1) th row is turned on.

  As an example, the period of t1 is 2 μs. Moreover, the period of t0 is 3-5 microseconds as an example. Note that the period of t1 is set so that the pixel is sufficiently charged to a desired value before the period starts.

  In the present embodiment, as the potential of the drain electrode 16 decreases, the potential of the common electrode 20 also decreases. Therefore, regardless of the magnitude of the potential of the drain electrode 16, in other words, regardless of the level of gradation. It is possible to prevent image quality degradation caused by feedthrough. This is because the pixel voltage is kept constant regardless of the gradation level.

  Therefore, when the driving device of the present embodiment is used, it is not necessary to adjust the voltage value corresponding to each gradation in accordance with the feedthrough voltage at each gradation.

  Further, as shown in FIG. 4, in the present embodiment, the common electrode 20 is in a floating state before t1 before the gate voltage of the nth row is turned off. When the common electrode 20 enters a floating state after the gate voltage is turned off, the pixel voltage may change (for example, smaller than “v”). Since the floating state of the common electrode 20 is determined when the voltage is turned off, the pixel voltage is reliably maintained at a desired value.

  In the present embodiment, when the period t0 elapses from the time when the period t1 elapses, the gate enable OE for the (n + 1) th row gate wiring is turned on. A predetermined period is provided from when the gate enable OE for the nth row is turned off to when the gate enable OE for the (n + 1) th row is turned on. It is possible to prevent a situation in which the voltage deviates from a desired voltage.

In the present embodiment, since there is a time difference between the end time of the period in which the common electrode 20 is in the floating state and the time when the gate voltage of the (n + 1) th row is turned on, the (n + 1) th time is provided. ) When the row gate voltage is turned on, the potential of the common electrode 20 is surely determined to be V _COM .

  In this embodiment, a driver capable of outputting the gate enable OE is used, and the period of t0 is set using the gate enable OE (application of the gate voltage to the gate wiring 13 in the (n + 1) th row). Such control is merely an example, and the period of t0 can be set without using the gate enable OE.

  In addition, the drive device according to the present embodiment also has the effects described below.

  FIG. 5A is a circuit diagram schematically showing the TFT and pixel 12 in the n-th row and the (n + 1) -th TFT and pixel 12. FIG. 5B is an equivalent circuit diagram schematically showing the TFT and the pixel 12 in the n-th row. In FIG. 5, the symbol A indicates the position (hereinafter referred to as A point) that is closest to the installation position of the gate driver 40 in the n-th row, and the symbol B indicates the position that is farthest from the installation position of the gate driver 40 (hereinafter referred to as “point A”). , Referred to as point B).

  FIG. 6 is a waveform diagram showing a gate potential, a pixel electrode potential, and a common potential. The upper part of FIG. 6A shows the potential at point A when the gate voltage is on. The upper part of FIG. 6B shows the potential at point B when the gate voltage is in the on state. As shown in FIG. 5B, since the equivalent circuit has a configuration in which a pair of resistors R and a capacitor C are connected in cascade, the potential waveform at the point B is compared with the potential waveform at the point A. Change becomes gentle.

  As a result, the feedthrough voltage corresponding to point B (indicated by b in FIG. 6) is smaller than the feedthrough voltage corresponding to point A (indicated by a in FIG. 6).

  In the present embodiment, even when the gate voltage is turned off and feedthrough occurs, the potential of the common electrode 20 follows the decrease in the potential of the drain electrode 16, so that both the points A and B are common. The pixel voltage with respect to the potential is substantially equal to the pixel voltage immediately before the gate voltage is turned off.

  That is, when using the driving device of the present embodiment, it is possible to eliminate the influence of the difference in the feedthrough voltage caused by the signal delay in the lateral direction of the gate wiring 13. In other words, even if there is a signal delay in the lateral direction of the gate wiring 13, the image quality of each pixel can be prevented from being deteriorated.

As described above, in the present embodiment, it is not necessary to adjust the voltage value according to each gradation according to the feedthrough voltage at each gradation. The value of the data voltage can be set to the upper and lower targets with respect to the common voltage _VCOM . Therefore, data voltage setting in the driving device is facilitated.

  Further, even if the characteristics of the liquid crystal and the parasitic capacitance of the TFT change, it is not necessary to change the value of the data voltage at each gradation level. This is because even if the gate voltage is turned off and the feedthrough voltage is generated, the pixel voltage does not change because the potential of the common electrode 20 follows the decrease in the potential of the drain electrode 16.

  In the above embodiment, the common DC system is taken as an example, but the present invention can also be applied when using the common inversion system.

  In the above embodiment, the source driver 30, the gate driver 40, the common driver 50, and the timing control circuit 60 are described as separate blocks. However, the source driver 30, the gate driver 40, the common driver 50, and the timing are described. The control circuit 60 may be incorporated in one driver IC. Furthermore, the present invention may be applied to an IPS (In Plane Switching) system.

  The present invention can be applied to a liquid crystal display device using TFTs.

10 Liquid crystal panel 12 Pixel 13 Gate wiring 14 Source wiring 15 TFT
16 drain electrode 17 capacitor 20 common electrode 30 source driver 40 gate driver 50 common driver 51 buffer circuit 60 control unit (timing control circuit)

Claims (6)

Driving a liquid crystal display panel having a plurality of gate lines and a plurality of source lines crossing each other, a gate driver that sequentially applies a gate voltage to the gate lines, and a common driver that supplies a common voltage to the common electrode A device,
The drive device for a liquid crystal display panel, wherein the common driver sets the common electrode in a floating state when application of the gate voltage by the gate driver is finished. The drive device for a liquid crystal display panel according to claim 1, wherein the common driver sets the common electrode in a floating state before the first predetermined period before the application of the gate voltage by the gate driver ends. The gate driver applies the gate voltage to the gate wiring of the (n + 1) -th row when the second predetermined period has elapsed after finishing the application of the gate voltage to the gate wiring of the n-th row (n: natural number). The drive device for a liquid crystal display panel according to claim 1 or 2. A driving device capable of outputting a gate voltage when a gate enable signal is in an on state,
The liquid crystal display panel driving device according to claim 3, wherein the gate driver determines when to start applying the gate voltage to the gate wiring of the (n + 1) th row using the gate enable signal. 5. The common driver releases the floating state of the common electrode before a third predetermined period from the time when application of the gate voltage is started by the gate driver. 6. LCD panel drive device.   6. A liquid crystal display device comprising the driving device according to claim 1 and a liquid crystal display panel.

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