JPH08330474A - Package for semiconductor - Google Patents

Abstract

PURPOSE: To provide a semiconductor package such as PGA or BGA package, which allows the increase of the number of input and output signals accompanying the high integration of a semiconductor element and the increase of the dissipation from the semiconductor element, but also to improve the property of transmission of high frequency signal such as over GHz and reduce the dispersion. CONSTITUTION: This possesses a ceramic multilayer substrate 2 such as a nitride aluminum multilayer substrate, etc., which has a mount 2a for a semiconductor element and a terminal formation face 2b and which is provided with an inner wiring layer 5 electrically connected with the semiconductor element. A group of input/output terminals 3 electrically connected to the inner wiring layer 5 are arranged at the terminal formation face 2b of the ceramic multilayer substrate 2. A group of input/output terminals 3 have signal terminals 4a and 4c, a ground terminal 4b, and a power terminal 4d. Out of these, the signals 4a and 4c are arranged next to at least one ground terminal 4b or the power source terminal 4d.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package with improved high frequency transmission characteristics.

[0002]

2. Description of the Related Art Generally, a plastic package, a metal package, or a ceramic package is used for packaging a semiconductor element. Of these,
Ceramics packages are used for packaging CMOS gate arrays, ECL gate arrays, etc. used in the computing unit of computers, because they have excellent insulating properties, heat dissipation properties, moisture resistance, and the like.

By the way, in recent years, the number of input / output signals per semiconductor element tends to increase due to high integration of the element. Moreover, the amount of heat generated from the semiconductor element tends to increase. Therefore, it is strongly desired for semiconductor packages to cope with an increase in the number of input / output signals and to improve heat dissipation.

From the above, QFP (Quad Flat)
PGA (Pin) made of ceramics, which can easily handle multiple terminals compared to
Grid Array) packages and BGA (Ball Grid Array) packages are receiving attention. As described above, by using the PGA package, the BGA package, or the like made of ceramics, it is possible to deal with the increase in the number of terminals of the semiconductor element and the increase in the amount of heat generation. However, in recent semiconductor devices, there is a strong tendency to increase the operating frequency in order to increase the operating speed. Ceramic PG with conventional structure
Although the A package and the BGA package can handle high frequency signals up to the MHz range, it is feared that the following problems will occur when the high frequency signal exceeds GHz.

That is, in the PGA package and the BGA package having the conventional structure, the transmission characteristics vary depending on the arrangement position of the signal line in the package. This variation in transmission characteristics means that the transmission characteristics of the signal line are partially deteriorated. Due to this partial deterioration of the transmission characteristics, the PGA package, the BGA package, and the like having the conventional structure have a problem that a semiconductor element is likely to malfunction.

[0006] On the other hand, recent semiconductor devices have been in the direction of increasing the degree of freedom in design as seen in ASIC.
Therefore, it is difficult to determine the signal passing characteristics of each signal line on the package side in advance. Therefore, it is required to improve the high frequency transmission characteristics of the majority of signal lines.

[0007]

As described above, with the recent high integration and high speed operation of semiconductor elements, the required characteristics of the semiconductor package are to cope with the increase in the number of inputs and outputs and to increase the heat dissipation. Performance, improvement of transmission characteristics of high-frequency signals, prevention of variations, and prevention of malfunctions associated therewith are becoming severer year by year.

For example, in order to increase the number of input / output signals and improve heat dissipation, a PGA package or BG made of ceramics is used.
A package is valid. However, since there are variations in the transmission characteristics of high-frequency signals that exceed GHz, depending on the position of the signal line, etc., it is possible to prevent variations in the transmission characteristics of this high-frequency signal and to prevent malfunctions that accompany it. Is required to do.

The present invention has been made to solve such a problem, and it is an object of the present invention to provide a semiconductor package which can practically cope with high integration and high speed operation of semiconductor elements. The purpose is to meet the increase in the number of input / output signals that accompanies higher integration of semiconductor devices and the increase in the amount of heat generated from semiconductor devices, and then exceed GHz that accompanies the higher-speed operation of semiconductor devices. It is an object of the present invention to provide a semiconductor package that improves the transmission characteristics of such high-frequency signals and reduces the variation.

[0010]

According to another aspect of the present invention, there is provided a semiconductor package having a mounting surface for a semiconductor element and a terminal forming surface, which is electrically connected to the semiconductor element. A ceramics multilayer substrate having a wiring layer, and an input / output terminal group electrically connected to the internal wiring layer and provided on a terminal forming surface of the ceramics multilayer substrate and having a signal terminal, a ground terminal and a power supply terminal. However, the main signal terminal among the signal terminals is at least 1
It is characterized in that it is arranged adjacent to the one ground terminal or the power supply terminal.

Furthermore, the semiconductor package of the present invention is
A ceramic multilayer substrate having a mounting surface of a semiconductor element and a terminal forming surface, and a signal wiring layer, a ground wiring layer, and a power wiring layer provided inside the ceramic multilayer substrate. An internal wiring layer in which at least one of the ground wiring layer and the power supply wiring layer is formed in a planar shape in the ceramic multilayer substrate, and the ground wiring layer are electrically connected to each other, and a terminal formation surface of the ceramic multilayer substrate The ground terminal provided on the
A power supply terminal electrically connected to the power supply wiring layer and provided on the terminal forming surface of the ceramic multilayer substrate, and a power supply terminal electrically connected to the signal wiring layer and provided on the terminal forming surface of the ceramic multilayer substrate. A signal terminal is provided, and a main signal terminal among the signal terminals is arranged adjacent to at least one of the ground terminal and the power supply terminal.

Factors that affect the transmission characteristics of high frequency signals exceeding GHz include the wiring length of the signal wiring, the presence or absence of plated wiring, the electromagnetic coupling between the signal wiring and the ground wiring, and the reference potential wiring of the power supply wiring. Can be considered. Among these, the degree of electromagnetic coupling between the signal wiring and the reference potential wiring has a great influence on the transmission characteristics of the high frequency signal. Particularly, in the ceramic PGA package and BGA package, since the ceramic multilayer substrate having the internal wiring layer is used, the path of the return current flowing through the reference potential wiring has a great influence on the transmission characteristics of the high frequency signal. By suppressing this variation in the path length of the return current and minimizing the difference in the electromagnetic coupling between each signal wiring and the reference potential wiring, it is possible to improve the transmission characteristics of high frequency signals exceeding GHz. In addition, the variation can be reduced. The present invention was made based on such findings.

In the semiconductor package of the present invention,
The main signal terminal is arranged adjacent to at least one ground or power terminal. Specifically, 50% or more of the signal terminals are arranged adjacent to at least one ground terminal or power terminal. Therefore, the path length of the return current based on the main signal terminal can be reduced, and the variation can be significantly reduced.
Further, the electromagnetic coupling condition between the main signal terminal and the ground terminal or the power supply terminal can be made approximately constant.
As a result, it is possible to improve the high frequency transmission characteristics of the signal wiring and reduce the variation.
Therefore, semiconductor devices of various designs can be freely mounted on the semiconductor package of the present invention, and it becomes possible to prevent malfunction of the semiconductor devices mounted thereon.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Modes for carrying out the present invention will be described below.

FIG. 1 shows a semiconductor package of the present invention as a P package.
It is sectional drawing which shows the structure of one Embodiment applied to the package for GA. This PGA package is a surface mount type P
It is applicable to both GA and insertion mounting type PGA.

In the semiconductor package 1 shown in the figure, the upper surface 2a is used as a mounting surface for a semiconductor element such as a CMOS gate array or an ECL gate array, and the surface opposite to the element mounting surface, that is, the lower surface 2b is formed with terminals. It is mainly composed of an aluminum nitride multilayer substrate 2 formed as a surface and an input / output pin group 3 (input / output pin 4) joined to the terminal forming surface 2b of the aluminum nitride multilayer substrate 2.

The aluminum nitride multi-layer substrate 2 is a multi-layer wiring substrate formed by integrating five layers of aluminum nitride layers 2c, 2d, 2e, 2f and 2g. An internal wiring layer 5 having a predetermined wiring pattern, which will be described later in detail, is provided on each aluminum nitride layer. Such an aluminum nitride multilayer substrate 2 is produced by, for example, co-firing the substrate itself (each aluminum nitride layer) and a conductive material that will become an internal wiring layer and the like.

The above-mentioned input / output pin groups 3 are regularly arranged on the lower surface (terminal formation surface) 2b of the aluminum nitride multilayer substrate 2 in, for example, a grid pattern. I / O pin group 3
Are electrically connected to internal wiring layers 5 provided inside the aluminum nitride multilayer substrate 2, respectively.

Next, the structure of the internal wiring layer 5 provided inside the aluminum nitride multilayer substrate 2 and the relationship between the internal wiring layer 5 and the input / output pin group 3 will be described in detail. The relationship between the internal wiring layer 5 and the input / output pin group 3 described below relates to a part of the internal wiring layer 5 shown in FIG. 1, and all the input / output pin group 3 has the relationship shown in FIG. Is not satisfied.

A chip mounting portion 6 and a surface wiring layer 7 are formed on the first aluminum nitride layer 2c, which is the uppermost layer, by co-firing similarly to the internal wiring layer 5, for example. Further, the first signal wiring layer 8 having a predetermined wiring pattern for routing a part of the signal line is provided on the second aluminum nitride layer 2d.

One end of the first signal wiring layer 8 is electrically connected to the surface wiring layer 7 by a via hole 8a filled with a conductive material. The other end of the first signal wiring layer 8 is electrically connected to a similar via hole 8b extending to the lower surface 2b of the aluminum nitride multilayer substrate 2. The via hole 8b is electrically connected to the input / output pin 4a located on the outermost periphery of the input / output pin group 3. That is,
The input / output pin 4a becomes a signal pin (signal terminal).

A ground wiring layer 9 is provided on the third aluminum nitride layer 2e. This ground wiring layer 9
Are formed in a planar shape (solid shape) on the third aluminum nitride layer 2e. One end of the ground wiring layer 9 is electrically connected to the surface wiring layer 7 by a via hole (not shown). The other end of the ground wiring layer 9 is electrically connected to a via hole 9a extending to the lower surface 2b of the aluminum nitride multilayer substrate 2. The via hole 9a is
It is electrically connected to the input / output pin 4b arranged next to the input / output pin 4a serving as the signal pin. That is, the input / output pin 4b becomes a ground pin (ground terminal).

A second signal wiring layer 10 having a predetermined wiring pattern for routing other signal lines is provided on the fourth aluminum nitride layer 2f. One end of the second signal wiring layer 10 is electrically connected to the surface wiring layer 7 by a via hole (not shown). The other end of the second signal wiring layer 10 is electrically connected to a via hole 10a extending to the lower surface 2b of the aluminum nitride multilayer substrate 2. The via hole 10a is electrically connected to the input / output pin 4c arranged next to the input / output pin 4b serving as the ground pin. That is, the input / output pin 4c becomes a signal pin (signal terminal).

A power supply wiring layer 11 is provided on the fifth aluminum nitride layer 2g. This power wiring layer 10
Are formed in a planar shape (solid shape) on the fifth aluminum nitride layer 2g. One end of the power supply wiring layer 10 is electrically connected to the surface wiring layer 7 by a via hole (not shown). The other end of the power supply layer 11 has a via hole 11a extending to the lower surface 2b of the aluminum nitride multilayer substrate 2.
Is electrically connected to. The via hole 11a is electrically connected to the input / output pin 4d arranged next to the input / output pin 4c serving as the signal pin described above. That is, the input / output pin 4d becomes a power supply pin (power supply terminal).

The above-mentioned signal wiring layers 8, 10, the ground wiring layer 9, the power supply wiring layer 11, and the via holes electrically connected to them constitute the internal wiring layer 5 of the aluminum nitride multilayer substrate 2. .

The input / output pin group 3 shown in FIG. 1 is adjacent to the signal pins 4a and 4c and the ground pin 4b of the reference potential by appropriately selecting the formation position and the layout of the internal wiring layers 5. Alternatively, the power supply pins 4d are arranged so as to be positioned. Further, the signal wiring layers 8 and 10, the ground wiring layer 9 and the power supply wiring layer 11 are alternately arranged in the laminating direction of the aluminum nitride multilayer substrate 2 as described above. In other words, each signal pin 4
The signal wiring layers 8 and 10 connected to a and 4c are arranged adjacent to the ground wiring layer 9 and the power supply wiring layer 11, respectively.

The input / output pin 4a described with reference to FIG.
Reference numerals 4b, 4c, and 4d are parts of the input / output pin group 3, and an example of the entire array of the input / output pin group 3 is shown in FIG. As shown in FIG. 2, the input / output pin groups 3 are regularly arranged in a grid pattern. Signal pin S must have at least one ground pin G
Alternatively, they are arranged so as to be adjacent to the power supply pin P. That is, the ground pin G or the power supply pin P is arranged at least at one of the four adjacent positions on the array of all the signal pins S. At other adjacent positions, the ground pin G and the power supply pin P do not necessarily have to be arranged, and other signal pins S as shown in FIG.
May be arranged.

As described above, in the semiconductor package 1 of this embodiment, the input / output pin group 3 is arranged so that the ground pin G or the power supply pin P is located at the position adjacent to at least one of all the signal pins S. Are arranged. For this reason, all signal pins S must be one ground pin G.
Alternatively, it is adjacent to the power supply pin P. By applying such a pin arrangement, it is possible to reduce the path length of the return current and reduce variations in the path length of the return current.

FIG. 3 is an exploded perspective view of essential parts showing a part of the surface wiring layer 7 and the first signal wiring layer 8 and the ground wiring layer 9 in the semiconductor package 1 shown in FIG.
Here, when a signal current flows through the signal wiring layer 8, a return current flows through the adjacent ground wiring layer 9. The path length of this return current greatly affects the transmission characteristics of the high frequency signal. That is, if the path of the return current becomes long, the transmission characteristic of the high frequency signal deteriorates.

Here, the formation position of the ground pin 4b and the power supply pin 4d greatly affects the path of the return current. As shown in FIG. 3, a ground pin 4b exists at a position adjacent to the signal pin 4a. When a signal current flows in the signal wiring layer 8 connected to the signal pin 4a, a return current (indicated by an arrow in FIG. 3) flows based on the formation position of the ground pin 4b adjacent to the signal pin 4a. That is, the path length of the return current flowing through the ground wiring layer 9 can be shortened. This is the same when the signal pin 4a is adjacent to the power supply pin 4d.

As shown in FIG. 2, since all the signal pins S are always adjacent to one ground pin G or the power supply pin P, the path length of the return current based on all the signal wirings is shortened. be able to. In this way, the path length of the return current can be shortened and the variation in the path length of the return current can be reduced. Therefore, the high frequency transmission characteristics of all the signal wirings can be improved. Further, it is possible to suppress the variation in the high frequency transmission characteristics.

On the other hand, as shown in FIG. 4, when there is no ground pin or power supply pin adjacent to the signal pin 4a, the path length of the return current (indicated by the arrow in FIG. 4) becomes long. Further, the path length of the return current differs in each signal wiring due to the variation in the distance between the signal pin and the ground pin or the power supply pin. The present invention suppresses the deterioration of the high frequency transmission characteristics due to such variations in the path length of the return current. From the above description, it is clear that the positional relationship between the signal pin and the ground pin or the power supply pin has a great influence on the high frequency transmission characteristics.

In the semiconductor package 1 of this embodiment, the signal wiring layers 8 and 10 and the ground wiring layer 9 are further added.
And the power supply wiring layers 11 are alternately arranged. Therefore, the electromagnetic coupling conditions between the signal wiring layers 8 and 10 and the planar ground wiring layer 9 and the power supply wiring layer 11 can be made approximately constant. This greatly contributes to the impedance control of the signal wiring layers 8 and 10. That is, by stabilizing the impedance of each of the signal wiring layers 8 and 10 approximately, it is possible to stabilize the transmission characteristics of the high frequency signal. The planar ground wiring layer 9 and the power supply wiring layer 11 are also effective in shortening the path of the return current.

As described above, in the semiconductor package 1 of this embodiment, the path length of the return current based on all the signal wirings 8 and 10 is shortened and its variation is reduced. Furthermore, the impedance of each signal wiring layer 8 and 10 is controlled. By these, it becomes possible to improve the high frequency transmission characteristics of all the signal wirings. This means that semiconductor elements of various designs can be mounted freely.

That is, recent semiconductor devices are ASICs.
As you can see, the trend is toward increasing the degree of freedom in design. Therefore, it is difficult to determine the signal passing characteristics of each signal line on the package side in advance. In response to such a current situation, by improving the high-frequency transmission characteristics of all signal wirings, it becomes possible to operate satisfactorily regardless of what kind of semiconductor element is mounted without causing malfunctions or the like. .

FIG. 5 shows the transmission characteristics (S ₂₁ parameter) of the signal wirings (8, 10, 4a, 4c) in the internal wiring layer 5 in the semiconductor package 1 having the input / output pin group 3 shown in FIG. Is a result of actual measurement using a network analyzer (HP8510C (manufactured by Hewlett-Packard Co.)) having a bandwidth of 0.1 GHz to 10.1 GHz.
FIG. 5 shows the relationship between the used frequency and the transmission characteristic (transmission loss).

The specific measuring method is as follows. First, two adjacent signal wirings were arbitrarily selected, and the selected two signal wirings were short-circuited on the surface wiring layer 7 side. The signal is input from the signal pin S of one of the signal wirings, passed through another signal wiring layer in the surface wiring layer 7 short-circuited through the signal wiring layer, and output from the other signal pin S. At this time, the ground wiring layer 9 and the power supply wiring layer 11 were all short-circuited.

On the other hand, as a comparison with the present invention, a semiconductor package having a conventional structure was manufactured. That is, the power supply pin and the ground pin were collectively arranged near the center of the lower surface of the aluminum nitride multilayer substrate, and the signal pins were arranged around them. A package having the same structure as that of the semiconductor package of the above-described embodiment was manufactured except for the arrangement of the input / output pin groups. Using the semiconductor package of this comparative example, the transmission characteristics (S ₂₁ parameter) of the signal line were measured as in the embodiment. The signal wiring (signal pin) for measurement was selected such that all the other signal pins were arranged in adjacent positions around the signal wiring. This measurement result is shown in FIG. 6 as a relationship between the used frequency and the transmission characteristic (transmission loss).

As is apparent from FIG. 5, in the semiconductor package 1 according to the above-described embodiment, the transmission loss is small over the entire measured frequency range, and excellent transmission characteristics are obtained even for high frequency signals in the GHz range. . Further, when the transmission characteristics of other signal wirings were measured in the same manner, the same good result was obtained for all the signal wirings. From these, it was confirmed that the variation in the transmission characteristics of the high frequency signal was small.

On the other hand, as is apparent from FIG. 6, in the semiconductor package of the conventional structure, the transmission loss increased as the measurement frequency increased, and the transmission characteristics of high frequency signals were inferior. Even in the semiconductor package of the conventional structure, some of the signal wirings obtained the same results as in the embodiment of the present invention, but most of them showed the characteristics shown in FIG. 6 and were transmitted depending on the position of the signal wiring. It was confirmed that there was a large variation in characteristics. Further, in the semiconductor package 1 of the above-described embodiment, the aluminum nitride multilayer substrate 2 having excellent thermal conductivity is used as the multilayer wiring substrate. As a result, high heat dissipation as a package is realized. From this point as well, it is attempted to prevent malfunctions and to speed up the operation of semiconductor elements. Further, it is possible to reduce the size of the package and cope with an increase in the number of input / output pins.

The ceramic multilayer substrate in the semiconductor package of the present invention is not limited to the aluminum nitride multilayer substrate, and an aluminum oxide multilayer substrate, a silicon nitride multilayer substrate, or the like can be used. However, it is preferable to use the aluminum nitride multilayer substrate from the viewpoint of heat dissipation as described above. The semiconductor package 1 of the above-described embodiment is suitable for mounting a highly integrated or high-speed semiconductor element, specifically, a CPU element or the like.

The semiconductor package 1 of the above-described embodiment
Then, the input / output pin group 3 is arranged so that all the signal pins S are adjacent to one ground pin G or one power supply pin P. The present invention is not limited to this, and if the arrangement is such that at least 50% or more of the signal pins S are adjacent to at least one ground pin G or power supply pin P, the degree of freedom in designing when mounting a semiconductor element is increased. Can hold enough.

For example, in the case of a 16-bit CPU, good high frequency transmission characteristics are required for at least 16 signal lines. Similarly, for a 32-bit CPU, at least 32
In the case of a 64-bit CPU, good high-frequency transmission characteristics are required for at least 64 signal lines. Therefore, 50%
By arranging the signal pins S so as to be adjacent to at least one ground pin G or power supply pin P, it is possible to sufficiently deal with various CPUs as described above.

As described above, not all the signal pins S have to be adjacent to the ground pin G or the power supply pin P. When it is desired to increase the degree of freedom in the arrangement of input / output pins, it is preferable to arrange 50% to 80% of the signal pins S adjacent to one ground pin G or power supply pin P. Even in such a case, an effect similar to that of the above-described embodiment can be obtained, and the degree of freedom in the arrangement of the input / output pins can be increased.

The arrangement of the input / output pin group 3 in the semiconductor package of the present invention is, as shown in FIG.
Any arrangement may be used so that the ground pin G or the power supply pin P is located at least at one position adjacent to the. further,
For example, as shown in FIG. 7, on the array of all signal pins S
The ground pin G or the power supply pin P may be arranged at all four adjacent positions. In this case, it is possible to further improve the high frequency transmission characteristic and further reduce the variation.

The semiconductor package 1 of the above-described embodiment
For example, as shown in FIG. 8, the semiconductor element 21 is mounted and used as a package component (semiconductor component). That is, the semiconductor element 21 is bonded to the chip mounting portion 6 of the aluminum nitride multilayer substrate 2. The semiconductor element 21 is electrically connected to the surface wiring layer 7 via the bonding wire 22.

Further, the semiconductor element 21 is hermetically sealed by being covered with a sealing member 23 made of, for example, an aluminum nitride sintered body. Aluminum nitride sealing member 2
3, the end surface of the convex outer edge portion having a U-shaped cross section is brought into contact with the semiconductor element mounting surface of the aluminum nitride multilayer substrate 2 and is joined so that the semiconductor element 21 is housed in the concave portion. The aluminum nitride multilayer substrate 2 and the aluminum nitride sealing member 23 are bonded to each other by Pb-Sn solder or Au-Sn.
It is performed with solder, glass, or the like.

The above-described embodiment uses the semiconductor package of the present invention as a PGA in which input / output pins are used as input / output terminals.
However, the present invention can also be applied to a semiconductor package having other input / output terminals, for example, a BGA package having input / output bumps as input / output terminals.

FIG. 9 shows a semiconductor package B of the present invention.
It is sectional drawing which shows the structure of embodiment applied to the package for GA. The BGA package 31 shown in FIG. 9 has bump terminal groups 32 (bump terminals 33) arranged on the terminal formation surface 2 b of the aluminum nitride multilayer substrate 2. The bump terminal 33 is formed by bonding a solder ball to the terminal forming surface 2b. Other configurations are
It has the same configuration as the PGA package 1 shown in FIG.

The bump terminals 33a and 33c are signal terminals. The bump terminal 33b is a ground terminal and the bump terminal 33d is a ground terminal. Also in the BGA package 31 in which the bump terminals 33 are arranged in this way, the high frequency transmission characteristics of the signal wiring can be improved similarly to the PGA package 1 described above. Then, no matter what kind of semiconductor element is mounted, it is possible to operate satisfactorily without causing a malfunction or the like.

In each of the above-described embodiments, the example in which the semiconductor element is mounted on one main surface of the aluminum nitride multilayer substrate 2 has been described, but the present invention is not limited to this, and a semiconductor having a cavity is provided. It is also possible to apply the present invention to a packaging.

Incidentally, Japanese Utility Model Publication No. 7-27164 discloses a semiconductor device in which a lead as a signal line and a lead as a ground line or a power line are alternately arranged in a flat package. This relates to a package using a lead frame such as QFP, and uses PGA or BG using the ceramic multilayer substrate according to the present invention.
The structure is obviously different from the semiconductor package for A. Furthermore, the present invention solves the problem regarding the return current peculiar to the semiconductor package using the ceramic multilayer substrate, and from this point as well, the present invention and the semiconductor device described in the above publication are different. is there.

In addition to these, in the semiconductor package for PGA or BGA targeted by the present invention, since 30 to 40% of the input / output terminals are originally ground terminals or power supply terminals, especially the ground terminals or power supply terminals are The terminal arrangement as described above can be realized without increasing the number of terminals. On the other hand, Q
In the case of FP, it is necessary to increase the number of ground leads and power source leads, and the number of signal line leads is reduced accordingly. This is against the increase in the number of input / output signals of the semiconductor element.

Further, in the case of QFP, it is necessary to directly electrically connect the leads and the semiconductor element, and therefore the arrangement of the leads limits the electrode position on the semiconductor element side. On the other hand, in the present invention, since the signal wiring and the like can be freely arranged in the internal wiring layer, the electrode position on the semiconductor element side is not particularly limited. Therefore, various semiconductor elements can be freely mounted. This is also a big difference.

[0055]

As described above, according to the semiconductor package of the present invention, it is possible to obtain excellent transmission characteristics of high-frequency signals exceeding GHz and reduce variations in the transmission characteristics. Therefore, for example, it is possible to freely mount semiconductor devices of various designs that are operated at high speed while suppressing malfunctions. As a result, it becomes possible to provide a semiconductor package that can practically cope with high integration and high speed operation of semiconductor elements.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of an embodiment in which a semiconductor package of the present invention is applied to a PGA package.

FIG. 2 is a diagram showing an example of an arrangement of input / output pins of the PGA package shown in FIG.

FIG. 3 is an exploded perspective view showing a main part of the PGA package shown in FIG.

FIG. 4 is an exploded perspective view of a main part of a PGA package shown as a comparison with the present invention.

5 is a diagram showing an example of the relationship between the measured frequency of the signal wiring and the transmission loss in the PGA package shown in FIGS. 1 and 2. FIG.

FIG. 6 is a diagram showing an example of a relationship between a measured frequency of a signal wiring and a transmission loss in a conventional PGA package.

7 is a diagram showing another arrangement example of input / output pins of the PGA package shown in FIG.

8 is a diagram showing a configuration example of a package component configured by mounting a semiconductor element on the PGA package shown in FIG.

FIG. 9 is a cross-sectional view showing a configuration of an embodiment in which the semiconductor package of the present invention is applied to a BGA package.

[Explanation of symbols]

 1 ... Semiconductor package 2 ... Aluminum nitride multilayer substrate 2c, 2d, 2e, 2f, 2g ... Aluminum nitride layer 3 ... Input / output pin group 4 ... Input / output pin 4a, 4c ... Signal pin 4b. Ground pin 4d ... Power supply pin 5 ... Internal wiring layer 8 ... First signal wiring layer 9 ... Ground wiring layer 10 ... Second signal wiring layer 11 ... Power supply wiring layer 21 ... Semiconductor element 32 ... … Bump terminal group 33 …… Bump terminal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yashiro Godai 4-4, 2 Suehiro-cho, Tsurumi-ku, Yokohama-shi, Kanagawa Prefecture Toshiba Keihin Office

Claims (6)

[Claims] 1. A ceramic multilayer substrate having an internal wiring layer having a mounting surface of a semiconductor element and a terminal forming surface and electrically connected to the semiconductor element; and a ceramic multilayer board electrically connected to the internal wiring layer. A signal terminal provided on the terminal forming surface of the ceramic multilayer substrate,
An input / output terminal group having a ground terminal and a power supply terminal, wherein a main signal terminal of the signal terminals is arranged adjacent to at least one of the ground terminal or the power supply terminal. For the package. 2. The semiconductor package according to claim 1, wherein 50% or more of the signal terminals are arranged adjacent to at least one ground terminal or power supply terminal. . 3. The semiconductor package according to claim 1, wherein all of the signal terminals are arranged adjacent to at least one ground terminal or power supply terminal. 4. The semiconductor package according to claim 1, wherein the internal wiring layer has a signal wiring layer, a ground wiring layer and a power wiring layer, and the signal wiring layer, the ground wiring layer and the power wiring layer At least one of them is arranged alternately in the stacking direction of the ceramic multilayer substrate. 5. The semiconductor package according to claim 1, wherein the input / output terminal group has pin terminals or bump terminals. 6. A ceramic multilayer substrate having a semiconductor element mounting surface and a terminal forming surface, a signal wiring layer, a ground wiring layer and a power wiring layer provided inside the ceramic multilayer substrate, and the ground wiring. At least one of the layer and the power supply wiring layer is electrically connected to the internal wiring layer formed in a plane in the ceramic multilayer substrate and the ground wiring layer, and is provided on the terminal formation surface of the ceramic multilayer substrate. A power supply terminal electrically connected to the ground terminal and the power supply wiring layer and provided on the terminal formation surface of the ceramic multilayer substrate, and a power supply terminal electrically connected to the signal wiring layer and the terminal formation surface of the ceramic multilayer substrate And a signal terminal provided on the power supply terminal, the main signal terminal among the signal terminals being at least one of the ground terminal or the power supply terminal. Semiconductor package, characterized by being arranged adjacent to.