JPH06163739A - Semiconductor package - Google Patents

Abstract

PURPOSE:To provide a small semiconductor package that can realize correspondence to the increase in input/output signals and high heat radiation and prevent mulfunctions due to high-speed operation of a semiconductor chip. CONSTITUTION:A semiconductor package 1 is provided with a semiconductor chip 3 mounted therein, a multilayered aluminum nitride substrate 2 having wiring patterns (6, 7, 10, 11, 14, 15) connected electrically with the chip 3, and connecting terminals 4 that are electrically connected with the wiring patterns and are prepared on the opposite face to the chip mounting face of the substrate 2. At least one layer of the substrate 2 occupies a power source layer 13 or a ground layer 9 exclusively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package using an aluminum nitride substrate.

[0002]

2. Description of the Related Art Semiconductor chips are usually used by being packaged with a plastic material, a ceramic material or the like for the purpose of protection from the external environment and improvement of handleability. By the way, in recent years, with the progress of semiconductor manufacturing technology, high integration and high speed operation of semiconductor chips are rapidly advancing.

With the high integration of the semiconductor chip, the number of input / output signals per element tends to increase year by year, and the amount of heat generated from the semiconductor chip also tends to increase. For this reason, it is strongly desired for the semiconductor package to cope with the increase in the number of input / output signals and to improve the heat dissipation.

On the other hand, the operation speed of the semiconductor chip is increased,
That is, as the operating frequency (system clock frequency) increases, malfunctions due to timing errors, crosstalk, reflection / ringing, ground bounce (simultaneous switching noise), etc., are more likely to occur.
There is a strong demand for semiconductor packages to prevent such malfunctions. In addition, as semiconductor chips operate at higher speeds, it is becoming more important to suppress signal delay within the package.

[0005]

As described above, as semiconductor chips become highly integrated and operate at high speed, the required characteristics of the semiconductor package are to cope with an increase in the number of input / output signals, to improve heat dissipation, The prevention of malfunctions and the suppression of signal delays are becoming severer year by year. For example, suppression of signal delay is
This can be handled by making the package shape smaller and reducing the wiring length in the package. In addition, the demand for miniaturization of various electronic devices is increasing, and the need for miniaturization of the semiconductor package itself is increasing. However, simply miniaturizing the package may increase the number of input / output signals. Correspondence and heat dissipation are likely to be sacrificed.

Therefore, there is a strong demand for a semiconductor package which can be miniaturized and practically applicable to high integration and high speed operation of semiconductor chips. That is, the package can be downsized in response to an increase in the number of input / output signals due to the high integration of the semiconductor chip, and high heat dissipation that can cope with an increase in the amount of heat generated from the semiconductor chip is ensured. There is a demand for a semiconductor package that can be manufactured.

Recently, a semiconductor chip having an operating frequency of 2 GHz or more has also appeared, and when a semiconductor chip having such an operating frequency is mounted, it is possible to prevent malfunction due to ground bounce or the like. Getting important.

The present invention has been made to address such a problem, and makes it possible to reduce the size of the package, cope with an increase in the number of input / output signals, and achieve high heat dissipation, and at the same time, a semiconductor chip. It is an object of the present invention to provide a semiconductor package that prevents malfunction due to high speed operation.

[0009]

In a semiconductor package of the present invention, a semiconductor chip is mounted and an aluminum nitride multilayer substrate having a wiring pattern electrically connected to the semiconductor chip; And a connection terminal provided on the surface of the aluminum nitride multilayer substrate opposite to the surface on which the semiconductor chip is mounted, wherein at least one layer in the aluminum nitride multilayer substrate is a power supply layer or a ground layer. It is characterized in that it is a layer that monopolizes layers.

[0010]

In the semiconductor package of the present invention, since at least one layer in the multi-layer substrate is a layer exclusively occupied by the power supply layer or the ground layer, even when operating at a high system clock frequency such as 2 GHz or more. The malfunction can be effectively prevented. By reducing the self-inductance of the ground, it is possible to stably prevent malfunction due to ground bounce or the like.

Further, in the semiconductor package of the present invention, the aluminum nitride multi-layer substrate having excellent thermal conductivity is used, and the package structure is such that the connection terminals are provided on the side opposite to the semiconductor chip mounting surface of the aluminum nitride multi-layer substrate. Since it is provided on the surface, it is possible to reduce the size of the package while achieving the increase in the number of input / output signals and the high heat dissipation of the package. By reducing the size of the package, the wiring length in the package can be shortened, so that it is possible to suppress the signal delay, and thus it is possible to effectively cope with the high-speed operation of the semiconductor chip. It will be possible.

[0012]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 and FIG. 2 are views showing the structure of an embodiment of the semiconductor package of the present invention. In the semiconductor package 1 shown in these figures, a semiconductor chip 3 for a CMOS gate array, an ECL gate array or the like is mounted on the upper surface of an aluminum nitride multilayer substrate 2, and a connection terminal and a connection terminal are provided on the lower surface side of the aluminum nitride multilayer substrate 2. The input / output pin 4 is formed by joining. The semiconductor package 1 of this embodiment is particularly suitable when it has 100 or more input / output pins 4 and is used at a system clock frequency of 2 GHz or more.

The above-mentioned aluminum nitride multilayer substrate 2 is
7 layers of aluminum nitride (2a, 2b, 2c, 2d,
2e, 2f, 2g) is a multilayer wiring board formed by integrating multiple layers, and an internal wiring layer described later having a predetermined wiring pattern is provided on each aluminum nitride layer. Such an aluminum nitride multilayer substrate 2
Is produced by, for example, co-firing the substrate itself (each aluminum nitride layer) and a conductive material that will become an internal wiring layer and the like. The number of layers of the aluminum nitride multilayer substrate 2 is preferably 6 or more in order to form a power supply layer and a ground layer described later on the dedicated aluminum nitride layer.

The aluminum nitride multilayer substrate 2 will be described in detail. The chip mounting portion 5 and the surface wiring layer 6 are formed on the uppermost first aluminum nitride layer 2a by a thin film forming technique such as a sputtering method or a vapor deposition method. The surface wiring layer 6 has a connection pad that serves as an electrical connection portion with the semiconductor chip 3 and a surface wiring portion. The connection pad is provided at one end of the surface wiring portion, and the other end is connected to the via hole 7 filled with a conductive substance.

A ground layer 9 is provided on the second aluminum nitride layer 2b except for a via hole formation region 8 which is provided continuously with the via hole 7. Further, on the third aluminum nitride layer 2c, a first signal wiring layer 10 having a predetermined wiring pattern for routing a part of the input / output signal line is provided. One end of the first signal wiring layer 10 is connected to the via hole 7 and the other end thereof is connected to the via hole 11. The via hole 11 is formed with the third, fourth, fifth, sixth and seventh aluminum nitride layers 2c, 2d, 2e, 2f, 2g.
Through, to the lower surface of the aluminum nitride multilayer substrate 2. Further, the input / output signal line which is not routed in the first signal wiring layer 10 is further extended to the fifth aluminum nitride layer 2e by the via hole (7).

A power supply layer 13 is provided on the fourth aluminum nitride layer 2d except for a via hole forming region 12 which is provided continuously with the via holes 7 and 11. Further, a second signal wiring layer 14 having a predetermined wiring pattern for routing the remaining input / output signal lines is provided on the fifth aluminum nitride layer 2e. One end of the second signal wiring layer 14 is formed from the surface wiring portion (6) to the first, second, third and fourth aluminum nitride layers 2.
It is connected to a via hole (7) extended through a, 2b, 2c, and 2d, and the other end is connected to a via hole 15. The via hole 15 extends to the lower surface of the aluminum nitride multilayer substrate 2 via the fifth, sixth and seventh aluminum nitride layers 2e, 2f and 2g.

On the sixth aluminum nitride layer 2f, a via-hole forming region 16 is formed continuously with the via-holes 11 and 15 forming the input / output signal lines (including some power supply lines). The ground layer 17 is provided except for. Further, a ground layer 19 is provided on the seventh aluminum nitride layer 2g, except for a via hole formation region 18 which is similarly provided continuously with the via holes 11 and 15. A partial wiring layer 20 is also provided on the seventh aluminum nitride layer 2g.

On the lower surface side of the aluminum nitride multilayer substrate 2, there is a predetermined land 21 which is electrically connected to the via holes 11 and 15 which form the input / output signal lines (including some power supply lines). It is formed in a pattern. Then, the input / output pin 4 serving as a connection terminal is formed on these lands 21.
Are joined respectively. The land 21 is preferably arranged so that the formation pitch of the input / output pins 4 is 1.27 mm (50 mils) or less. In this embodiment, the formation pattern of the lands 21 is set so that the formation pitch of the input / output pins 4 is 1.27 mm. In this way, even if the density of the connection terminals is increased, the multilayer substrate is made of aluminum nitride, which has high thermal conductivity, so sufficient heat dissipation is ensured and miniaturization is possible, resulting in signal delay. Can be made smaller.

The semiconductor chip 3 includes the bonding wire 2
It is electrically connected to the connection pad of the surface wiring layer 6 via 2. The semiconductor chip 3 is covered with a sealing member made of ceramics having high thermal conductivity, for example, a sealing member 23 made of an aluminum nitride sintered body. That is, in the aluminum nitride sealing member 23, the end surface of the convex outer edge portion 23a having a U-shaped cross section is brought into contact with the semiconductor chip mounting surface of the aluminum nitride multilayer substrate 2, and the semiconductor chip 3 is housed in the concave portion 23b. Are joined as described. Aluminum nitride multilayer substrate 2 and aluminum nitride sealing member 2
The connection with 3 is made with Pb-Sn solder, Au-Sn solder, glass, or the like. However, when using a bonding material having low thermal conductivity such as glass, it is desirable that the bonding layer has a layer thickness of 100 μm or less, preferably 50 μm or less.

The aluminum nitride sealing member 23 described above
Also has the function of a heat dissipation member. The joint area of the aluminum nitride sealing member 23 directly affects the heat transfer state from the aluminum nitride multi-layer substrate 2 to the aluminum nitride sealing member 23. Therefore, the formation accuracy of the surface wiring layer 6 and the semiconductor package 1 can be improved. It is preferable to set the size as large as possible in consideration of the allowable size.

In the semiconductor package 1 of the above-mentioned embodiment, since the ground layer 9 and the power supply layer 13 are provided so as to exclusively use the aluminum nitride layers 2b and 2d in the aluminum nitride multilayer substrate 2, It is possible to reduce the self-inductance of the ground, which can prevent malfunction due to ground bounce or the like. Further, the power supply layer 13 also contributes to the prevention of malfunction by providing it on a dedicated layer. Therefore, even when operating at a system clock frequency of 2 GHz or higher, it is possible to stably secure the operating characteristics.

Further, since the aluminum nitride multilayer substrate 2 having excellent thermal conductivity is used as the multilayer wiring substrate and the input / output pins 4 are provided on the lower surface side of the aluminum nitride multilayer substrate 2, an input of 100 or more is obtained. It is possible to support the number of output signals and achieve high heat dissipation as a package. Then, after achieving these, it becomes possible to reduce the package shape. For example, the shape of the semiconductor package 1 of the above embodiment is 25.4 mm × 25.4 mm. In this way, since the package can be made smaller,
The wiring length in the package can be shortened, and thus the signal delay can be suppressed. As a result, it becomes possible to effectively cope with the high speed operation of the semiconductor chip.

Further, since the sealing member 23 for hermetically sealing the semiconductor chip 3 has high thermal conductivity, the heat from the semiconductor chip 3 can be dissipated also from this sealing member 23 side. Therefore, heat dissipation can be further improved.

As described above, the semiconductor package 1 of the above-described embodiment can be miniaturized and have a large number of pins, can satisfy the high heat dissipation property, can further suppress the signal delay, and malfunction due to the high operating frequency. It can be said that this can be prevented. Therefore, having 100 or more input / output pins 4,
It is also suitable when used at a system clock frequency of 2 GHz or higher.

Although the semiconductor chip 3 is mounted on one main surface of the aluminum nitride multilayer substrate 2 in the above embodiment, the present invention is not limited to this, and may have a cavity. It can also be applied to a semiconductor package. In addition, the above embodiment is an example in which the semiconductor package of the present invention is applied to PGA.
Similar effects can be obtained with A (land grid array).

[0027]

As described above, according to the semiconductor package of the present invention, the size of the package can be reduced, the number of input / output signals can be increased, and the heat dissipation can be improved. It is possible to prevent the malfunction due to the higher speed operation. Therefore, it is possible to provide a semiconductor package that can practically cope with high integration and high speed operation of semiconductor chips.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a configuration of a semiconductor package of an embodiment of the present invention.

FIG. 2 is an exploded perspective view showing a structure of an aluminum nitride multilayer substrate used in the semiconductor package shown in FIG.

[Explanation of symbols]

1 ... Semiconductor package 2 ... Aluminum nitride multilayer substrate 2a, 2b, 2c, 2d, 2e, 2f, 2g ... Aluminum nitride layer 3 ... Semiconductor chip 4 ... Input / output pin 6 ... Surface Wiring layer 9 ... Ground layer 10 ... First signal wiring layer 13 ... Power supply layer 14 ... Second signal wiring layer 21 ... Land 23 ... Aluminum nitride sealing member

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication location // H01L 21/3205 7514-4M H01L 21/88 S (72) Inventor Kotoshi Sato Yokohama, Kanagawa 8 Shinsita-cho, Isogo-ku, Yokohama Stock company Toshiba Yokohama office

Claims (5)

[Claims] 1. An aluminum nitride multilayer substrate having a semiconductor chip mounted thereon and a wiring pattern electrically connected to the semiconductor chip; and an aluminum nitride multilayer substrate electrically connected to the wiring pattern. And a connection terminal provided on a surface opposite to the mounting surface of the semiconductor chip, wherein at least one layer in the aluminum nitride multilayer substrate is
A semiconductor package characterized by being a layer exclusively used for a power supply layer or a ground layer. 2. The semiconductor package according to claim 1, wherein the semiconductor package has 100 or more connection terminals and is used at a system clock frequency of 2 GHz or more. 3. The semiconductor package according to claim 1, wherein the aluminum nitride multilayer substrate has six or more aluminum nitride layers. 4. The semiconductor package according to claim 1, wherein a high thermal conductive ceramics sealing member is bonded to the mounting surface side of the semiconductor chip of the aluminum nitride multilayer substrate so as to seal the semiconductor chip. A semiconductor package characterized in that 5. The semiconductor package according to claim 1, wherein the connection terminals are arranged so that a formation pitch is 1.27 mm or less.