JPH07221182A - Semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the malfunction in IO cells caused N M by the rounding in the rise of clock signals by cutting down the rounding in the rise of the clock signals. CONSTITUTION:A single phase clock wiring 4 connecting to a clock input terminal 1 and IO cells 5a is arranged in square shape in the peripheral region of a chip 100. At this time, the 10 cells 5a are arranged on one side opposite to one side of the signal phase clock wiring 4 with the clock input terminal 1 arranged thereon. Besides, the wiring resistance between the clock input terminal 1 and the IO cells 5a can be lowered by transmitting the clock signals from the clock input terminal 1 through the intermediary of another clock wiring 6 due to the IO cells 5a and the clock terminal 1 connected by the wiring 6. Through these procedures, the rounding in the rise of clock signals can be cut down thereby enabling the malfunction in the IO cells 5a to be eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which operates by a clock signal.

[0002]

2. Description of the Related Art Generally, a clock is used in a synchronous system in a one-phase clock system and a two-phase clock system. Hereinafter, a semiconductor device adopting both the one-phase clock system and the two-phase clock system will be used. A conventional semiconductor device will be described.

FIG. 4 is a diagram showing the structure of a conventional semiconductor device. In FIG. 4, reference numeral 13 denotes a two-phase clock wiring, which is arranged in a peripheral region in the chip 100 and is connected to a plurality of IO cells 15. The IO cell 15 is an input / output terminal between the chip 100 and the outside. Reference numeral 14 denotes a one-phase clock wiring, which is the same as the two-phase clock wiring 13 in the chip 1
00 are arranged in the peripheral area, and each of them has a plurality of I's.
It is connected to the O cell 15. Reference numeral 11 denotes a clock input terminal, which is connected to the one-phase clock wiring 14. Reference numeral 12 denotes a clock generator, which can generate a two-phase clock signal from the clock signal input from the clock input terminal 11. The clock generator 12 is connected to the clock input terminal 11 and the two-phase clock wiring 13, and can give different clock signals to the two-phase clock wiring 13.

The one-phase clock wiring 14 is arranged in a square shape, and the wiring resistance on each side of the one-phase clock wiring 14 is 1.0 rΩ (r is an arbitrary constant). Also,
The capacitance between the substrate and the wiring on each side is 1.0 c coulomb (c is an arbitrary constant). The IO cell 15a and the clock input terminal 11 are respectively located at the centers of the sides of the one-phase clock wiring 14 and are opposed to each other.

Next, the clock input terminal 11 and the IO cell 1
Wiring resistance and wiring capacitance in the one-phase clock wiring 14 between the wiring 5a and 5a will be described.

The wiring resistance of the one-phase clock wiring 14 between the clock input terminal 11 and the IO cell 15a is 0.
It can be considered that two resistors of 5r + 1.0r + 0.5r = 2.0r (ohm) are connected in parallel. Therefore, when the wiring resistance of the one-phase clock line 14 between the clock input terminal 11 and the IO cell 15a and R _2, from Ohm's law, the R ₂ = 1.0r (ohms). Further, when the capacity of one-phase clock line 14 between the clock input terminal 11 and the IO cell 15a and _{C 2, C 2 = 0.5c +} 1.0c + 0.5c + 0.5c + 1.0
It becomes c + 0.5c = 4.0c (coulomb). FIG. 5 is a lumped constant circuit model diagram of the wiring resistance and capacitance of the one-phase clock wiring 14 between the clock input terminal 11 and the IO cell 15a.

The operation of the semiconductor device configured as described above will be described with reference to FIGS.

FIG. 6 is a diagram showing the relationship between the rise time of the clock signal propagated through the one-phase clock wiring 14 in the IO cell 15a and the power supply voltage.

First, the clock signal input from the clock input terminal 11 propagates through the one-phase clock wiring 14 and reaches the IO cell 15a. At this time, a power supply voltage of 5V is applied to the clock input terminal 11 as a clock signal, and the rising time required for the output voltage of the IO cell 15a to reach 3.16V, which can be read as a high level, is τ ₂ . Then, τ ₂ = R ₂ ·
C ₂ = 1.0r · 4.0c = 4rc. The relationship between the rise time and the voltage is as shown in FIG.

[0010]

However, semiconductors
The wiring becomes longer due to the increase in the chip area of the device,
Narrow wiring width due to the miniaturization of processes accompanying high integration
If it becomes, the capacity C ₂Increase or wiring resistance R₂But
It will increase. On the other hand, clock input terminal 1
Clocks propagated from 1 to 1-phase clock wiring 14
Rise time τ of IO signal 15a in IO cell 15a₂Is
One-phase black between lock input terminal 11 and IO cell 15a
Wiring resistance R of the wiring 14₂And capacity C₂Is proportional to
It

Therefore, in the conventional semiconductor device, the clock wiring resistance R ₂ and the capacitance C ₂ of the one-phase clock wiring 14 are used.
As the voltage increases, the time required for the voltage of the IO cell to reach 3.16V becomes longer (hereinafter, the longer the time required for the voltage to reach 3.16V means that the rounding of the clock signal becomes larger). . Further, as the rounding of the clock signal becomes large, the semiconductor device tends to malfunction.

The semiconductor device of the present invention solves the above problem and is capable of reducing the rounding of the rising edge of the clock signal in the IO cell 15a and reducing the malfunction caused by the rounding of the clock signal.

[0013]

According to the present invention, in order to solve the above problems, a clock input terminal located on one side of a clock wiring arranged in the periphery of a semiconductor device and one side of a clock wiring facing the clock input terminal. And an input / output terminal located at, and a wiring connecting the clock input terminal and the input / output terminal.

[0014]

According to the present invention, the wiring having the input / output terminal at the position facing the clock input terminal is connected by the above-mentioned structure, so that the wiring resistance between the clock input terminal and the input / output terminal can be reduced. .

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the semiconductor device of the present invention will be described below with reference to FIG.

FIG. 1 is a diagram showing the configuration of an embodiment of the semiconductor device of the present invention. In FIG. 1, 3 and 4 are two-phase clock wirings, which are arranged in the periphery of the chip 100 and are connected to a plurality of IO cells 5. IO cell 5
Are input / output terminals between the chip 100 and the outside. A clock input terminal 1 is connected to the one-phase clock wiring 4 and has a flip-flop circuit inside. In addition,
The clock input terminal 1 is not connected to the two-phase clock wiring 3. Reference numeral 2 denotes a clock generator, which can generate a two-phase clock signal from the clock signal input from the clock input terminal 1 and can supply different clock signals to the two-phase clock wiring 3. Further, the clock input terminal 1 and the IO cell 5a are connected by the wiring 6.

In this embodiment, the one-phase clock wiring 4
Are arranged in a square and the wiring resistance on each side is 1.0
r ohm (r is an arbitrary constant). The capacitance between the substrate and the wiring on each side is 1.0 c coulomb (c is an arbitrary constant). The IO cell 5a and the clock input terminal 1 are located at the center of one side of the one-phase clock wiring 4 and at the opposite positions. In addition, the wiring resistance of the wiring 6 is also set to 1.0 rOhm, and the capacitance between the wiring 6 and the substrate is set to 1.0 c Coulomb.

Next, the clock input terminal 1 and the IO cell 5a
The wiring resistance and capacitance between the two will be described.

Regarding the wiring resistance between the clock input terminal 1 and the IO cell 5a, there are two resistances of 0.5r + 1.0r + 0.5r = 2.0r (ohm) and one resistance of 1.0r (ohm). It can be considered that a total of three resistors are connected in parallel. Therefore, when the wiring resistance between the clock input terminal 1 and the IO cells 5a and R _1, from Ohm's law, the R ₁ = 0.5r (ohms). If the capacitance between the clock input terminal 1 and the IO cell 5a is C ₁ , C ₁ = 0.5c + 1.0c + 0.5c + 0.5c + 1.0.
It becomes c + 0.5c + 1.0c = 5.0c (coulomb).
FIG. 2 shows an equivalent circuit in which the wiring resistance and capacitance between the clock input terminal 1 and the IO cell 5a are represented by lumped constants.

The operation of the semiconductor device configured as described above will be described with reference to FIGS.

FIG. 3 is a diagram showing the relationship between the rising time and the voltage of the clock signal input from the clock input terminal 1 in the IO cell 5a.

First, the clock signal input from the clock input terminal 1 propagates through the one-phase clock wiring 4 and the wiring 6 through each IO cell and reaches the IO cell 5a. At the same time, the clock signal is also supplied to the clock generator 2, and the two-phase clock signals generated by the clock generator 2 are supplied to the two-phase clock wiring 3.

In this embodiment, the clock signal propagated through the one-phase clock wiring 4 and the wiring 6 is used for explanation, and the explanation of the clock signal propagation operation of the two-phase clock wiring 3 is omitted. To do.

Then, when the clock signal input from the clock input terminal 1 is propagated to the IO cell 5a,
The relationship between the voltage and time in the IO cell 5a will be described.

It is assumed that a power supply voltage of 5V is applied to the clock input terminal 1 as a clock signal. Letting τ ₁ be the rise time required for the output voltage of the IO cell 5a to reach 3.16 V that can be read as a high level from 0 V, then τ ₁ = R ₁ · C ₁ . Further, as described above, since R ₁ = 1.0r and C ₁ = 5.0c, τ ₁ = 0.
5r · 5.0c = 2.5rc. Therefore, the relationship between the voltage and time in the IO cell 5a is shown in FIG.

As described above, according to the semiconductor device of this embodiment, the wiring resistance between the clock input terminal 1 and the IO cell 5a can be reduced, and the clock signal supplied to the IO cell 5a becomes 3.16V. The time required to reach can be reduced from the conventional 4 rc to 2.5 rc.

Although the IO cell is described as an input / output terminal in the above embodiment, there is no problem even if it is an input-only terminal.

Although only the one-phase clock wiring 4 has been described in the above embodiment, it is obvious that the same effect can be obtained even if the above-described configuration is adopted for the two-phase clock wiring 3.

In the above-mentioned embodiment, the one-phase clock wiring 4 is arranged in a square, but this is one embodiment, and it is not always arranged in a square.

[0030]

According to the present invention, since the clock input terminal is connected to the input / output terminal at the position facing the clock input terminal, the wiring resistance between the clock input terminal and the input / output terminal can be reduced. Therefore, the rise time of the clock signal at the input / output terminal can be shortened.

Therefore, it is possible to provide an excellent semiconductor device capable of reducing the malfunction of the data exchange at the input / output terminals, which is caused by the delay in the transmission of the clock signal.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a lumped constant circuit model diagram in a semiconductor device according to an embodiment of the present invention.

FIG. 3 is an IO cell 5a of a semiconductor device according to an embodiment of the present invention.
Showing the relationship between rise time and voltage in

FIG. 4 is a diagram showing a configuration of a conventional semiconductor device.

FIG. 5 is a lumped constant circuit model diagram in a conventional semiconductor device.

FIG. 6 is a diagram showing a relationship between a rise time and a voltage in an IO cell 15a of a conventional semiconductor device.

[Explanation of symbols]

 1 Clock Input Terminal 2 Clock Generator 3 2-Phase Clock Wiring 4 1-Phase Clock Wiring 5 IO Cell 6 Wiring 11 Clock Input Terminal 12 Clock Generator 13 2-Phase Clock Wiring 14 1-Phase Clock Wiring 15 IO Cell 100 Chip

Claims (1)

[Claims] 1. A clock wiring arranged in a peripheral region in a semiconductor device, a clock input terminal connected to the clock wiring, and the clock wiring facing one side of the clock wiring where the clock input terminal is arranged. A semiconductor device comprising: an input / output terminal arranged on one side; and a wiring connecting the input / output terminal and the clock input terminal.