JP2013201189A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2013201189A
JP2013201189A JP2012067425A JP2012067425A JP2013201189A JP 2013201189 A JP2013201189 A JP 2013201189A JP 2012067425 A JP2012067425 A JP 2012067425A JP 2012067425 A JP2012067425 A JP 2012067425A JP 2013201189 A JP2013201189 A JP 2013201189A
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layer
semiconductor
type
semiconductor layer
electrode
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JP5793101B2 (en
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Masakazu Kanechika
将一 兼近
Makoto Kuwabara
誠 桑原
Hiroyuki Ueda
博之 上田
Tsutomu Uesugi
勉 上杉
Hidemiki Tomita
英幹 富田
Hirofumi Aoki
宏文 青木
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Toyota Central R&D Labs Inc
株式会社豊田中央研究所
Toyota Motor Corp
トヨタ自動車株式会社
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Abstract

PROBLEM TO BE SOLVED: To provide a technique for discharging holes generated by avalanche breakdown.
A semiconductor device includes an aluminum gallium nitride buried layer, a gallium nitride electron transit layer, and an aluminum gallium nitride electron supply layer. The electron transit layer 6 has a p-type partial region 6A containing a p-type impurity in at least a part other than the existence range of the two-dimensional hole gas layer (2DHG) formed on the joint surface with the buried layer 5. ing.
[Selection] Figure 1

Description

  The technology disclosed in this specification relates to a semiconductor device including a heterojunction.

  A semiconductor device having a heterojunction composed of two semiconductor layers having different band gap widths is known. This type of semiconductor device uses a two-dimensional electron gas layer formed on a heterojunction surface as a channel, and is often referred to as HEMT (High Electron Mobility Transistor) or HFFT (Heterojunction Field Effect Transistor). .

  In this type of semiconductor device, when an excessive voltage is applied, avalanche breakdown occurs in a high electric field region near the gate portion. For example, when holes generated by avalanche breakdown remain in the vicinity of the gate portion, there is a problem that the element is conducted by electrons attracted to the holes and, in some cases, the semiconductor device is destroyed.

  Therefore, in this type of semiconductor device, a hole discharge electrode is provided in order to discharge holes generated by avalanche breakdown. Patent Document 1 discloses a technique that uses a two-dimensional hole gas layer to guide the generated holes to a hole discharge electrode.

JP 2008-135575 A (FIG. 1)

  Patent Document 1 discloses a technique for making a semiconductor layer on which a two-dimensional hole gas layer is formed p-type. When a p-type impurity is contained, the resistance of the hole transfer path from the high electric field region where avalanche breakdown occurs to the two-dimensional hole gas layer can be reduced. On the other hand, since the p-type impurity is also contained in the existence range of the two-dimensional hole gas layer, the resistance of the two-dimensional hole gas layer is increased by impurity scattering.

  Patent Document 1 also discloses a technique for forming an i-type semiconductor layer on which a two-dimensional hole gas layer is formed. In this case, since the existence range of the two-dimensional hole gas layer is i-type, impurity scattering is suppressed and the resistance of the two-dimensional hole gas layer does not increase. On the other hand, the hole movement path from the high electric field region where the avalanche breakdown occurs to the two-dimensional hole gas layer is increased in resistance.

  As described above, in the technique of Patent Document 1, regardless of whether the semiconductor layer on which the two-dimensional hole gas layer is formed is p-type or i-type, a high resistance is provided between the high electric field region and the hole discharge electrode. However, there is a problem in that holes are efficiently discharged. It is an object of the present specification to provide a technique for guiding holes generated by avalanche breakdown to a hole discharge electrode in a semiconductor device having a heterojunction.

  The semiconductor device disclosed in this specification includes a first semiconductor layer of a first type of semiconductor material, a second semiconductor layer of a second type of semiconductor material, a third semiconductor layer of a third type of semiconductor material, and a first electrode. And a second electrode, a gate portion, and a hole discharge electrode. The second semiconductor layer is provided in contact with the first semiconductor layer. The third semiconductor layer is provided in contact with the second semiconductor layer. The first electrode is provided on the third semiconductor layer. The second electrode is provided on the third semiconductor and is separated from the first electrode. The gate portion is provided on the third semiconductor layer and is disposed between the first electrode and the second electrode. The hole discharge electrode is in contact with the first semiconductor layer. The band gap width of the first type semiconductor material is wider than the band gap width of the second type semiconductor material, and the band gap width of the third type semiconductor material is the band gap width of the second type semiconductor material. Wider than. As a result, a two-dimensional hole gas layer is formed on the second semiconductor layer side of the joint surface between the first semiconductor layer and the second semiconductor layer, and the first of the joint surfaces between the second semiconductor layer and the third semiconductor layer. A two-dimensional electron gas layer is formed on the two semiconductor layer side. In the semiconductor device disclosed in this specification, the second semiconductor layer has a p-type partial region containing a p-type impurity. The p-type partial region is formed in at least a part other than the existence range of the two-dimensional hole gas layer.

  In the semiconductor device of the above aspect, since the p-type impurity is not included in the existence range of the two-dimensional electron gas layer, impurity scattering is suppressed and the resistance of the two-dimensional hole gas layer does not increase. Further, in the semiconductor device of the above aspect, the p-type partial region is formed in addition to the existence range of the two-dimensional electron gas layer, and the movement of holes from the high electric field region where avalanche breakdown occurs to the two-dimensional hole gas layer The resistance of the path is reduced. In the semiconductor device of the above aspect, holes generated by avalanche breakdown can be efficiently discharged to the hole discharge electrode.

The principal part sectional drawing of the semiconductor device of an Example is shown typically. An example of the concentration distribution in the depth direction of the p-type partial region is shown. Another example of the concentration distribution in the depth direction of the p-type partial region is shown. An example of the energy band figure of a buried layer, an electron transit layer, and an electron supply layer is shown. Another example of the energy band diagram of a buried layer, an electron transit layer, and an electron supply layer is shown. A manufacturing process of a semiconductor device of an example is shown (1). The manufacturing process of the semiconductor device of an Example is shown (2). The manufacturing process of the semiconductor device of an Example is shown (3). The manufacturing process of the semiconductor device of an Example is shown (4). The manufacturing process of the semiconductor device of an Example is shown (5). The manufacturing process of the semiconductor device of an Example is shown (6).

Some of the technical features disclosed in the present specification are summarized below. The items described below have technical usefulness independently.
(Mode 1) A semiconductor device disclosed in this specification includes a first semiconductor layer of a first type of semiconductor material, a second semiconductor layer of a second type of semiconductor material, and a third semiconductor layer of a third type of semiconductor material. And may be provided. The second semiconductor layer may be provided in contact with the first semiconductor layer. The third semiconductor layer may be provided in contact with the second semiconductor layer.
(Mode 2) The band gap of the first type semiconductor material may be wider than the band gap of the second type of semiconductor material. The band gap width of the third type semiconductor material may be wider than the band gap width of the second type semiconductor material. The magnitude relationship between the band gap width of the first type semiconductor material and the band gap width of the third type semiconductor material is not particularly limited. For this reason, the first type semiconductor material and the third type semiconductor material may be the same semiconductor material or different semiconductor materials.
(Mode 3) Any of the first type semiconductor material, the second type semiconductor material, and the third type semiconductor material may be a nitride semiconductor. In this case, the first type of semiconductor material is represented by the general formula In X1 Al Y1 Ga 1-X1 -Y1 N (0 ≦ X1 ≦ 1,0 ≦ Y1 ≦ 1,0 ≦ X1 + Y1 ≦ 1). The second type of semiconductor material, represented by the general formula In X2 Al Y2 Ga 1-X2 -Y2 N (0 ≦ X2 ≦ 1,0 ≦ Y2 ≦ 1,0 ≦ X2 + Y2 ≦ 1). The third type of semiconductor material is represented by the general formula In X3 Al Y3 Ga 1-X3 -Y3 N (0 ≦ X3 ≦ 1,0 ≦ Y3 ≦ 1,0 ≦ X3 + Y3 ≦ 1). Here, X1 is smaller than X2, and Y1 is larger than Y2. X3 is smaller than X2, and Y3 is larger than Y2. In one example, the first type of semiconductor material may be aluminum gallium nitride, the second type of semiconductor material may be gallium nitride, and the third type of semiconductor material may be aluminum gallium nitride.
(Mode 4) A semiconductor device disclosed in this specification may include a first electrode, a second electrode, a gate portion, and a hole discharge electrode. The first electrode may be provided on the third semiconductor layer. The second electrode is provided on the third semiconductor and may be separated from the first electrode. Here, both the first electrode and the second electrode may be ohmically connected to the two-dimensional electron gas layer formed on the second semiconductor layer side of the joint surface between the second semiconductor layer and the third semiconductor layer. Good. The gate portion is provided on the third semiconductor layer and is disposed between the first electrode and the second electrode. The gate portion may be a Schottky gate type or an insulated gate type. The hole discharge electrode may be in contact with the first semiconductor layer.
(Mode 5) The second semiconductor layer has a p-type partial region containing a p-type impurity in at least a part other than the existence range of the two-dimensional hole gas layer formed on the joint surface with the first semiconductor layer. You may do it.
(Mode 6) The p-type partial region may be arranged so as to include at least a part of the existence range of the gate portion when viewed in plan. Avalanche breakdown often occurs near the gate. For this reason, if a p-type partial region is provided corresponding to the gate portion, holes generated by avalanche breakdown can be efficiently discharged.
(Mode 7) The impurity concentration of the p-type partial region may decrease from the junction surface between the first semiconductor layer and the second semiconductor layer toward the junction surface between the second semiconductor layer and the third semiconductor layer. A two-dimensional electron gas layer is formed on the bonding surface between the second semiconductor layer and the third semiconductor layer. For this reason, by suppressing the impurity scattering in this two-dimensional electron gas layer, the on-resistance can be kept low.

  As shown in FIG. 1, the semiconductor device 1 is a lateral HFET, and includes a substrate 2, a buffer layer 3, a high resistance layer 4, a buried layer 5, an electron transit layer 6, an electron supply layer 7, a drain electrode 11, and a gate. A portion 14, a source electrode 15, and a hole discharge electrode 16 are provided. Here, the buried layer 5 corresponds to the first semiconductor layer described in the claims, the electron transit layer 6 corresponds to the second semiconductor layer described in the claims, and the electron supply layer 7 corresponds to the claims. The drain electrode 11 corresponds to the first electrode recited in the claims, and the source electrode 15 corresponds to the second electrode recited in the claims.

The material of the substrate 2 is a material capable of crystal growth of a nitride semiconductor, and sapphire or silicon is used as an example. The buffer layer 3 is provided on and in contact with the substrate 2. When the material of the substrate 2 is sapphire, the material of the buffer layer 3 is non-doped gallium nitride (GaN) or aluminum nitride (AlN). The high resistance layer 4 is provided on and in contact with the buffer layer 3, and gallium nitride is used as the material thereof. Further, the high resistance layer 4 is doped with carbon to increase the resistance. In one example, the carbon concentration contained in the high resistance layer 4 is about 1 × 10 18 to 2 × 10 19 cm −3 .

  The buried layer 5 is provided in contact with a part of the high resistance layer 4 and is made of non-doped aluminum gallium nitride (AlGaN). The composition ratio of aluminum in the buried layer 5 is adjusted to about 15 to 23%. The buried layer 5 has a thickness of about 50 to 100 nm. The buried layer 5 in this example is selectively provided in a part of the surface of the high resistance layer 4. However, instead of this example, the buried layer 5 covers the entire surface of the high resistance layer 4. May be provided. The electron transit layer 6 is provided in contact with a part on the high resistance layer 4 and a part on the buried layer 5, and the material thereof is non-doped gallium nitride. For this reason, the band gap of the buried layer 5 is wider than the band gap of the electron transit layer 6. Therefore, a two-dimensional hole gas layer (2DHG) is formed on the electron transit layer 6 side of the heterojunction surface between the buried layer 5 and the electron transit layer 6. The thickness of the portion of the electron transit layer 6 provided on the buried layer 5 is about 100 to 500 nm. The electron supply layer 7 is provided in contact with the electron transit layer 6, and non-doped aluminum gallium nitride is used as the material thereof. The composition ratio of aluminum in the electron supply layer 7 is adjusted to about 20 to 30%. For this reason, the band gap of the electron supply layer 7 is wider than the band gap of the electron transit layer 6. Therefore, a two-dimensional electron gas layer (2DEG) is formed on the electron transit layer 6 side of the heterojunction surface of the electron transit layer 6 and the electron supply layer 7. The thickness of the electron supply layer 7 is about 15 to 30 nm.

  The drain electrode 11 is provided in contact with part of the electron supply layer 7. The drain electrode 11 is a laminate in which titanium and aluminum are laminated in this order. Titanium is in contact with the electron supply layer 7. The drain electrode 11 is ohmically connected to a two-dimensional electron gas layer (2DEG) formed on the heterojunction surface between the electron transit layer 6 and the electron supply layer 7. The gate portion 14 is provided in contact with a part of the electron supply layer 7 and is disposed between the drain electrode 11 and the source electrode 15. The gate portion 14 is disposed in a range where the buried layer 5 exists when seen in a plan view. The gate unit 14 includes a gate electrode 12 and a gate insulating film 13. The gate electrode 12 faces the electron supply layer 7 through the gate insulating film 13. Aluminum is used as the material of the gate electrode 12, and silicon oxide is used as the material of the gate insulating film 13. The source electrode 15 is provided in contact with a part of the electron supply layer 7 and is disposed away from the drain electrode 11. The source electrode 15 is a laminated body in which titanium and aluminum are laminated in this order. Titanium is in contact with the electron supply layer 7. The source electrode 15 is ohmically connected to a two-dimensional electron gas layer (2DEG) formed on the heterojunction surface between the electron transit layer 6 and the electron supply layer 7. The hole discharge electrode 16 is provided in contact with a part of the buried layer 5. The hole discharge electrode 16 is a laminate of nickel and gold. Nickel is in contact with the buried layer 5. The hole discharge electrode 16 is ohmically connected to the buried layer 5. The hole discharge electrode 16 may be fixed to the ground voltage, or may be biased to the negative side in order to increase the hole discharge efficiency.

  As shown in FIG. 1, the electron transit layer 6 has a p-type partial region 6A containing a p-type impurity. Magnesium is used as the p-type impurity. The p-type partial region 6A is arranged in a range where the buried layer 5 exists when viewed in plan. Further, the p-type partial region 6A is not arranged in a range where the two-dimensional hole gas layer (2DHG) and the two-dimensional electron gas layer (2DEG) exist. Specifically, the p-type partial region 6A is separated from the junction surface between the buried layer 5 and the electron transit layer 6 by about 10 nm or more, and separated from the junction surface between the electron transit layer 6 and the electron supply layer 7 by about 10 nm or more. .

As shown in FIG. 2, the impurity concentration of the p-type partial region 6A has a distribution that decreases from the buried layer 5 side toward the electron supply layer 7 side when observed in the depth direction. The impurity concentration of the p-type partial region 6A is 1 × 10 19 cm −3 or more on the buried layer 5 side and 1 × 10 15 cm −3 or less on the electron supply layer 7 side. In this example, the impurity concentration of the p-type partial region 6A continuously decreases from the buried layer 5 side toward the electron supply layer 7 side. Instead of this example, as shown in FIG. 3, the impurity concentration of the p-type partial region 6A may decrease discontinuously (stepwise) from the buried layer 5 side toward the electron supply layer 7 side. .

  Next, the operation of the semiconductor device 1 will be described. The semiconductor device 1 is configured as a normally-on type. When a positive voltage is applied to the drain electrode 11, a ground voltage is applied to the source electrode 15, and a ground voltage is applied to the gate electrode 12, the drain electrode 11 is formed near the heterojunction surface of the electron transit layer 6 and the electron supply layer 7. Electrons travel from the source electrode 15 toward the drain electrode 11 through the two-dimensional electron gas layer (2DEG). As a result, the semiconductor device 1 is turned on. In the semiconductor device 1, since the p-type partial region 6A is not formed in the existence range of the two-dimensional electron gas layer (2DEG), the impurity scattering is suppressed, and the resistance of the current flowing through the two-dimensional electron gas layer (2DEG) Is small.

  When a negative voltage is applied to the gate electrode 12, a depletion layer is formed below the gate insulating film 13, the electrons of the two-dimensional electron gas layer (2DEG) are depleted, and the two-dimensional electron gas layer (2DEG) is passed through. Electronic travel stops. As a result, the semiconductor device 1 is turned off. In this off state, for example, the electric field concentrates on the surface portion of the semiconductor layer located at the drain side end of the gate portion 14 (see 1A in FIG. 1), and avalanche breakdown may occur in this high electric field region. Holes generated by avalanche breakdown are discharged to the hole discharge electrode 16 through a two-dimensional hole gas layer (2DHG) formed at the heterojunction surface of the buried layer 5 and the electron transit layer 6. In the semiconductor device 1, since the p-type partial region 6A is provided between the high electric field region and the two-dimensional hole gas layer (2DHG), holes from the high electric field region to the two-dimensional hole gas layer (2DHG) are provided. The movement path of the is reduced in resistance. Furthermore, in the semiconductor device 1, since the p-type partial region 6A is not formed in the existence range of the two-dimensional hole gas layer (2DHG), impurity scattering is suppressed, and the two-dimensional hole gas layer (2DHG) is formed. The resistance of the flowing current is small. For this reason, holes generated by avalanche breakdown are discharged from the hole discharge electrode 16 with high efficiency and are prevented from accumulating inside. As a result, the avalanche resistance of the semiconductor device 1 is greatly improved.

  The advantages of the p-type partial region 6A will be described in more detail with reference to FIGS. 4A and 4B. In order to reduce the resistance of the hole movement path from the high electric field region on the surface of the semiconductor layer to the two-dimensional hole gas layer (2DHG), for example, it is also possible to shorten the distance of the movement path. is there. That is, the thickness of the electron transit layer 6 between the buried layer 5 and the electron supply layer 7 may be reduced. As shown in FIG. 4A, when the thickness of the electron transit layer 6 between the buried layer 5 and the electron supply layer 7 is reduced, the potential of the two-dimensional electron gas layer (2DEG) with respect to electrons increases, and the two-dimensional electron gas layer The electron density of (2DEG) becomes small. For this reason, in the ON state, the resistance of the current flowing through the two-dimensional electron gas layer (2DEG) is increased.

  On the other hand, in order to increase the electron density of the two-dimensional electron gas layer (2DEG), the thickness of the electron transit layer 6 between the buried layer 5 and the electron supply layer 7 should be increased as shown in FIG. 4B. . However, when the thickness of the electron transit layer 6 is increased, the distance of the hole movement path from the high electric field region on the surface of the semiconductor layer to the two-dimensional hole gas layer (2DHG) is increased, and the holes are discharged. When the resistance increases. The semiconductor device 1 is characterized in that the electron transit layer 6 is made relatively thick and a p-type partial region 6A is provided. Thereby, in the semiconductor device 1, even when the electron transit layer 6 is thick, the resistance when holes are discharged can be kept small. That is, the semiconductor device 1 can suppress the resistance when holes are discharged while suppressing the on-resistance.

(Manufacturing method of the semiconductor device 1)
Hereinafter, a first manufacturing method of the semiconductor device 1 will be described with reference to the drawings. First, as shown in FIG. 5, a laminated substrate is prepared in which a substrate 2, a buffer layer 3, a high resistance layer 4, a buried layer 5, a non-doped layer 6a, and a p-type doped layer 6b are laminated. Note that the non-doped layer 6 a and the p-type doped layer 6 b finally become a partial region of the electron transit layer 6. The buffer layer 3 is crystal-grown on the substrate 2 using a metal organic chemical vapor deposition (MOCVD) method at a low temperature. The high resistance layer 4, the buried layer 5, the non-doped layer, and the p-type doped layer 6b are also crystal-grown using the MOCVD technique. As an example of the carbon source of the high resistance layer 4, acetylene is used. Alternatively, a methyl group of an organometallic gas can be used as a carbon source. Cyclopentadienyl magnesium is used as the magnesium source of the p-type doped layer 6b. In one example, the non-doped layer 6a has a thickness of about 10 to 20 nm, and the p-type doped layer 6b has a thickness of about 10 to 20 nm. Moreover, the magnesium concentration contained in the p-type doped layer 6b is about 1 × 10 19 to 3 × 10 19 cm −3 .

  Next, as shown in FIG. 6, a part of the p-type doped layer 6b, the non-doped layer 6a and the buried layer 5 is removed by using an etching technique, and a part of the surface of the high resistance layer 4 is exposed. .

  Next, as shown in FIG. 7, gallium nitride is crystal-grown on the high resistance layer 4 and the p-type doped layer 6b by using MOCVD technology, and then aluminum gallium nitride is crystal-grown. When crystal growing gallium nitride, magnesium contained in the p-type doped layer 6b diffuses into the regrown portion on the p-type doped layer 6b. As a result, as shown in FIG. 8, the electron transit layer 6 having the p-type partial region 6 </ b> A and the electron supply layer 7 are formed on the buried layer 5.

  Next, as shown in FIG. 9, the drain electrode 11, the gate portion 14, and the source electrode 15 are formed on the electron supply layer 7 by using a vapor deposition technique. Next, as shown in FIG. 10, a part of the electron supply layer 7 and a part of the electron transit layer 6 are removed using an etching technique, and a part of the surface of the buried layer 5 is exposed. Finally, a hole discharge electrode 16 is formed on the exposed buried layer 5 using a vapor deposition technique, and the semiconductor device 1 shown in FIG. 1 is completed.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. In addition, the technical elements described in the present specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in the present specification or the drawings can achieve a plurality of objects at the same time, and has technical utility by achieving one of the objects.

2: substrate 3: buffer layer 4: high resistance layer 5: buried layer 6: electron transit layer 6A: p-type partial region 7: electron supply layer 11: drain electrode 14: gate portion 15: source electrode 16: hole discharge electrode

Claims (4)

  1. A first semiconductor layer of a first type of semiconductor material;
    A second semiconductor layer of a second type of semiconductor material provided on and in contact with the first semiconductor layer;
    A third semiconductor layer of a third kind of semiconductor material provided on and in contact with the second semiconductor layer;
    A first electrode provided on the third semiconductor layer;
    A second electrode provided on the third semiconductor and separated from the first electrode;
    A gate portion provided on the third semiconductor layer and disposed between the first electrode and the second electrode;
    A hole discharge electrode in contact with the first semiconductor layer,
    The band gap of the first type semiconductor material is wider than the band gap of the second type semiconductor material,
    The band gap width of the third type semiconductor material is wider than the band gap width of the second type semiconductor material,
    The second semiconductor layer has a p-type partial region containing a p-type impurity in at least a part other than the existence range of the two-dimensional hole gas layer formed on the joint surface with the first semiconductor layer. A semiconductor device.
  2.   2. The semiconductor device according to claim 1, wherein the p-type partial region is disposed so as to include at least a part of an existing range of the gate portion when seen in a plan view.
  3.   2. The impurity concentration of the p-type partial region decreases from a junction surface between the first semiconductor layer and the second semiconductor layer toward a junction surface between the second semiconductor layer and the third semiconductor layer. 2. The semiconductor device according to 2.
  4. The first semiconductor layer is aluminum gallium nitride;
    The second semiconductor layer is gallium nitride;
    The semiconductor device according to claim 1, wherein the third semiconductor layer is aluminum gallium nitride.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015149360A (en) * 2014-02-05 2015-08-20 トヨタ自動車株式会社 compound semiconductor FET
JP2015149359A (en) * 2014-02-05 2015-08-20 トヨタ自動車株式会社 compound semiconductor FET
JP2016134613A (en) * 2015-01-22 2016-07-25 国立大学法人名古屋大学 Group iii nitride semiconductor element and manufacturing method of the same

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03171636A (en) * 1989-11-29 1991-07-25 Oki Electric Ind Co Ltd Field-effect transistor
JP2007103451A (en) * 2005-09-30 2007-04-19 Toshiba Corp Semiconductor device and its manufacturing method
JP2008016588A (en) * 2006-07-05 2008-01-24 Toshiba Corp GaN-BASED SEMICONDUCTOR ELEMENT
JP2008135575A (en) * 2006-11-28 2008-06-12 Furukawa Electric Co Ltd:The Semiconductor electronic device
JP2008258419A (en) * 2007-04-05 2008-10-23 Toshiba Corp Nitride semiconductor device
JP2009054685A (en) * 2007-08-24 2009-03-12 Sharp Corp Nitride semiconductor device and power converter including the same
JP2011238701A (en) * 2010-05-07 2011-11-24 Toyota Central R&D Labs Inc Hfet

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03171636A (en) * 1989-11-29 1991-07-25 Oki Electric Ind Co Ltd Field-effect transistor
JP2007103451A (en) * 2005-09-30 2007-04-19 Toshiba Corp Semiconductor device and its manufacturing method
JP2008016588A (en) * 2006-07-05 2008-01-24 Toshiba Corp GaN-BASED SEMICONDUCTOR ELEMENT
JP2008135575A (en) * 2006-11-28 2008-06-12 Furukawa Electric Co Ltd:The Semiconductor electronic device
JP2008258419A (en) * 2007-04-05 2008-10-23 Toshiba Corp Nitride semiconductor device
JP2009054685A (en) * 2007-08-24 2009-03-12 Sharp Corp Nitride semiconductor device and power converter including the same
JP2011238701A (en) * 2010-05-07 2011-11-24 Toyota Central R&D Labs Inc Hfet

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015149360A (en) * 2014-02-05 2015-08-20 トヨタ自動車株式会社 compound semiconductor FET
JP2015149359A (en) * 2014-02-05 2015-08-20 トヨタ自動車株式会社 compound semiconductor FET
JP2016134613A (en) * 2015-01-22 2016-07-25 国立大学法人名古屋大学 Group iii nitride semiconductor element and manufacturing method of the same

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