JPH03171636A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To prevent a modulation in a drain current from causing even if a drain voltage becomes high by a method wherein a field-effect transistor is provided with a quantum well formation layer for accumulating holes provided in a buffer layer and an electrode for hole lead-out use, which is electrically connected with the quantum well formation layer. CONSTITUTION:A field-effect transistor is provided with a buffer layer 12 and a channel layer 16, which are provided in order on a substrate 10, and is provided with a quantum well formation layer 1 for accumulating holes provided in the layer 12 and an electrode 16 for hole lead-out use, which is electrically connected with this layer 14. When such a high drain voltage that collision ionization is caused in a channel is applied, the holes injected in a buffer layer 14b are led to an InGaAs layer 12b and are discharged to an external circuit through an electrode 18, whose potential connected with the external circuit is held in 0V or a negative potential. As the hole mobility in the layer 12b is high, a reduction in the time of a hole conduction ranging from the channel to the electrode 18 can be made small. Accordingly, a reduction in an electron potential due to the hole conduction can sufficiently be lessened.

Description

[Detailed Description of the Invention] (Field of Industrial Application) This invention relates to field effect transistors. (Prior Art) As a conventionally proposed field effect transistor, for example, Document I: IEEE Electron Device
Letters (IEE Electron Device Letters) vol.1. EDL-6, No. 1
．． There is something that was not disclosed in January 1985. This conventional field effect transistor consists of undoped GaAs that is sequentially stacked on a semi-insulating 'aGaAs substrate using a crystal lengthening method such as molecular beam epitaxial growth (MBE).
As buffer layer, Si-doped n-GaAs channel layer,
A Si-doped n''-GaAs cap layer is provided, and an ohmic electrode is provided in each of the cap layers of the source region and drain region, and the cap layer of the channel region is recessed to the channel layer, thereby forming a gate electrode on the exposed channel layer. (Problems to be Solved by the Invention) In the conventional field effect transistor described above, when the train voltage increases and the electric field strength in the channel increases, an electron collision electric field M is generated in the channel. Of the electrons and holes generated by ionization, some of the electrons are guided to the train electrode and some of the holes are guided to the gate electrode, but the other part of the holes is injected into the buffer layer and the semi-insulating substrate. These injected holes are captured in the deep level of the buffer layer or half-w! fastener substrate, lowering the electron potential of the layer.As a result,
The width of the depletion layer between the channel and the buffer layer narrows, the drain current increases rapidly, a kink occurs, and the saturation characteristics of the train current deteriorate rapidly. An object of the present invention is to solve the above-mentioned conventional problems and to provide a field effect transistor in which the train current does not undergo modulation or the degree of modulation is small even when the train voltage increases. (Means for Solving the Problems) In order to further achieve this object, a field effect transistor of the present invention includes a buffer layer and a channel layer sequentially provided on a substrate. It is characterized by comprising a quantum well forming layer for accumulating the provided holes, and a hole extraction electrode electrically connected to the quantum well forming layer. (Function) According to such a structure, the quantum well type layer has a valence band (
A quantum well layer is created to store holes in the valence band. Therefore, holes injected into the buffer layer due to impact ionization are discharged to an external electric circuit or the like via the hole extraction electrode accumulated in the quantum well type barrier layer.

(Embodiment) Hereinafter, embodiment 1 of the present invention will be explained with reference to the drawings. It should be noted that the drawings are merely shown schematically to the extent that the invention can be understood, and therefore, the shapes, dimensions, and locations of the various structures are not limited to the 8% illustrated examples. FIG. 1 is a cross-sectional view schematically showing the structure of an embodiment of the present invention, showing the structure of one field effect transistor separated by an element isolation layer. As shown in the figure, the field effect transistor of this embodiment includes a buffer layer 12 and a channel layer 16 that are sequentially provided on a substrate 10, and quantum wells are formed in the buffer layer 12 for storing holes. layer 14
and a hole deriving electrode] 6 electrically connected to the quantum well type barrier layer 14. This example will be explained in more detail below. In this embodiment, undoped GaAs lower buffer layers 12a, ! Single well formation layer 14
and undoped GaAs upper buffer layer 12b! The quantum well forming layer 14 is sandwiched between buffer layers 12a and 12b. The quantum well forming layer 14 includes a p-GaAs layer 14a, which is sequentially provided from the lower buffer layer 12a side.
Two-dimensional holes are induced from the p-InGaAs layer 14b and the p-GaAs layer 14c to a certain InGaAs layer 14t), and therefore, a collision electric charge M is generated in the channel (the holes generated thereby are in the upper buffer layer 12t) and the GaAs layer 14c. The 5InGaAs layer 14b that passes through it accumulates. In order to increase the mobility of holes in the InGaAs layer 14b, the layer thickness of the InGaAs layer 14b is set to a critical thickness tM.
Must be less than or equal to AX. The film thickness t MAX is the maximum film thickness at which lattice strain relaxation due to the introduction of dislocations does not occur, and the film thickness t M
AX is the lattice constant of the GaAs layers 12a and 12C and In
It is determined by the magnitude of the mismatch in the lattice constant of the x Ga+-x As layer 14t) (X>O). For example, InGaAS
layer 141) in Ino. 2Gaa. ．． In the case of As layer,
t MAX is approximately 200λ. The film thickness t MAX is
Inx Ga+-. The larger the x of the As layer 14b, that is, the larger the difference in lattice constant between the InxG a + -x A S layer 14b and the GaAs layers 12a and 12C, the smaller the difference. I below critical film thickness t MAX
Since lattice strain due to lattice mismatch is applied to the nGaAs layer 14b, the hole unit in the valence band is split, and as a result, the effective mass of the hole becomes small. Therefore, the two-dimensional hole mobility induced in the strained InGaAs layer 14k) is the same as the hole mobility in the GaAs layers 12a and 12b and the strain-free InGaAs layer 14k).
This becomes higher than the two-dimensional hole mobility in the s-layer 14b. Roughly speaking, in this embodiment, an n-GaAs channel layer 16 and an n''-GaAs channel layer 16 are sequentially formed in the center of the upper buffer layer 12b.
An As contact layer 20 is provided. Also, the upper buffer layer 1
Hole deriving electrode (ohmic electrode) on one side of 2b
18 will be provided. The electrode 18 is electrically connected to the InGaAs layer 14b via the alloy layer 22 which is shaped by sintering. And the center g of the channel layer 16! A recess 24 having a depth extending from the contact layer 20 to the channel layer 16 is provided so as to expose the contact layer 3, and a gate electrode 26 is formed in the exposed channel layer 16.
Establish. Further, a source electrode (ohmic electrode) 28 and a drain electrode (ohmic electrode) 30 are provided on one side and the other side of the contact layer 20. electrodes 28 and 30
are electrically connected to the channel layer 16 through alloy layers 32 and 34 formed by sintering, respectively. In order to roughly separate one field effect transistor element of this embodiment, the lower buffer layer 1 is separated from the upper buffer layer 12b.
An element isolation layer 36 having a depth of 2a is provided.

In this embodiment configured as described above, when a high drain voltage is applied that generates an impact charge M18 in the channel, the holes injected into the buffer layer 14t) are
It is led to the InGaAs layer 14b, connected to an external circuit, and discharged to the external circuit through an electrode 18 whose potential is maintained at Ov or a negative potential. Furthermore, since the mobility of holes in the InGaAs layer 14b is high, holes are transferred from the channel to the electrode 1.
8, the resistance until the hole conducts is reduced, and therefore the drop in electron potential due to hole conduction can be sufficiently reduced. In this way, the holes are not discharged to the external circuit, and the decrease in electron potential due to hole conduction can be reduced, so it is possible to eliminate or reduce potential fluctuations due to hole injection into the buffer layer 14b, and as a result, the drain current can be reduced. It is possible to improve the saturation characteristics of the conventional method. Next, in order to deepen the understanding of this invention, the manufacturing process of this embodiment will be explained by way of an example with reference to FIGS. 2 and 1. Figures 2 (A) to CC') are cross-sectional views showing step by step the main manufacturing steps of this embodiment. First, as shown in FIG. 2(A), an undoped GaAs buffer layer 12 is sequentially formed on a semi-embossed GaAs substrate 10.
a, Be dove p-GaAs#14a, Be dove p-
InGaAS layer 14b, Be-doped p-GaAs layer 14
C2 undoped GaAs buffer layer 12b, Si doped n-G' a As channel layer 16 and Si doped n
+ ++ 20% GaAs contact layer, epitaxially grown by molecular beam elongation method (MBE method). Next, as shown in FIG. 2 CB), the contact layer 20, the channel layer 16, and the buffer layer 121) are partially etched away to form a mesa portion 38 in the center of the buffer layer 12b. The element isolation layer 36 is shaped by partially implanting oxygen ions from the buffer layer 12b to the buffer layer 14a.

Next, as shown in FIG. 2(C), a source electrode 28 and a drain electrode 30 are provided on the contact layer 20, and then sintering is performed to form alloy layers 32 and 34 under the electrodes 28 and 30, respectively. Buffer layer 12
A hole deriving electrode 8 is provided on b, and then sintering is performed to form an alloy layer 22 on the lower side of the electrode 8. Next, as shown in FIG. 1, the contact layer 20 and the channel layer 16 are partially removed by recess etching to form the recess 24, and a gate is placed in the center of the channel layer 16 exposed through the recess 24. Form electrodes and obtain the desired field effect transistor. The present invention is not limited to the embodiments described above, and therefore, the conductivity type, forming material, doping material, shape or method, arrangement position, size, shape, and other conditions of each component can be arbitrarily changed. You can change it as you like. For example, in the above-described embodiment, an InGaAs layer is inserted into the undoped GaAs buffer layer 12, and the InGaAs layer and the GaAs buffer layer 12 in the vicinity of this InGaAs layer are doped with an acceptor impurity.
As layer 14a, p-InGaAs layer 14b and p-Ga
A quantum well forming layer 14 is formed from the As layer 14c, and p
-Although two-dimensional holes are induced in the InGaAs layer 14t), the structure of the quantum well forming layer is not limited to this. In addition, for example, the quantum well forming layer may be
It is also possible to adopt a structure in which only the nGaAs layer is used and supported by an undoped GaAs upper buffer layer and an undoped GaAs lower buffer layer. Alternatively, the quantum well forming layer may be composed of a p-GaAs layer, an undoped InGaAs layer, and a p-GaAs layer, which are sequentially provided from the lower buffer layer side. In addition to the epitaxial growth method such as the MBE method, the formation of the channel layer and the contact layer may be performed using an ion implantation method. (Effects of the Invention) As is clear from the above explanation, according to the field effect transistor of the present invention, the quantum well forming layer has a valence band (
A quantum well layer is formed to store holes in the valence band). Therefore, holes that are generated and injected into the puffer layer due to impact ionization accumulate in the quantum well forming layer and are discharged to the external electric circuit etc. via the hole extraction electrode. As a result, fluctuations in the potential of the buffer layer due to hole injection can be eliminated or reduced, making it possible to provide a field effect transistor with better train current saturation characteristics than conventional ones.

[Brief explanation of the drawing]

FIG. 1 is a sectional view schematically showing the structure of an embodiment of the present invention, and FIGS. 2(A) to 2(C) are sectional views showing step-by-step the main manufacturing steps of the embodiment. 10...Substrate, 12...Buffer layer] 4
... Quantum well type layer 18 ... Electrode for leading out holes.

Claims (1)

[Claims] (1) In a field effect transistor comprising a buffer layer and a channel layer sequentially provided on a substrate, a quantum well forming layer provided in the buffer layer for storing holes, and an electrical connection between the quantum well forming layer and the quantum well forming layer. 1. A field effect transistor comprising: a hole deriving electrode connected to a hole deriving electrode;