JP2010219247A - Compound semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compound semiconductor device suppressing a drain leak current generated upon application of a large drain voltage, and also to provide a manufacturing method for the compound semiconductor device. <P>SOLUTION: The compound semiconductor device is provided with: a substrate 1; an electron traveling layer 3 formed above the substrate 1; electron supply layers 4 and 5 which are formed above the electron traveling layer 3 and contain an AlGaN; and a Shottky barrier layer 6 which is formed on the electron supply layers 4 and 5 and contains an InAlN. The lattice constant of crystals making up the Shottky barrier layer 6 is larger than the lattice constant of crystals making up the electron supply layers 4 and 5. The band gap of a material making up the Shottky barrier layer 6 is larger than the band gap of a material making up the electron supply layers 4 and 5. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a compound semiconductor device and a manufacturing method thereof.

  In recent years, development of electronic devices (compound semiconductor devices) in which a GaN layer and an AlGaN layer are sequentially formed on a substrate made of sapphire, SiC, GaN, Si, or the like and the GaN layer is used as an electron transit layer has been active. The band gap of GaN is 3.4 eV, which is larger than 1.4 eV of GaAs. For this reason, this compound semiconductor device is expected to operate at a high breakdown voltage.

  One of such compound semiconductor devices is a GaN-based high electron mobility transistor (HEMT). When the GaN-based HEMT is used as a switch for an inverter for power supply, both reduction of on-resistance and improvement of breakdown voltage are possible. In addition, power consumption during standby can be reduced as compared with Si-based transistors, and the operating frequency can be improved. For this reason, switching loss can be reduced and the power consumption of the inverter can be reduced. In addition, a transistor having equivalent performance can be downsized as compared with a Si-based transistor.

  There is also a GaN-based HEMT capable of a normally-off operation in which no current flows through the channel when no voltage is applied to the gate.

  FIG. 1 is a cross-sectional view showing the structure of a conventional GaN-based HEMT. On the SiC substrate 101, an AlN layer 102, an undoped i-GaN layer 103, an undoped i-AlGaN layer 104, an n-type n-AlGaN layer 105, an n-type n-GaN layer 106, an AlN layer 107, and an n-type The n-GaN layers 108 are sequentially formed. Further, an SiN layer 109 is formed on the n-GaN layer 108. Openings are formed in the SiN layer 109, the n-GaN layer 108, and the AlN layer 107, and a gate electrode 111g is formed therein. Further, two openings are formed in the SiN layer 109, the n-GaN layer 108, the AlN layer 107, and the n-GaN layer 106 so as to sandwich the gate electrode 111g, and the source electrode 111s is formed in one of them. A drain electrode 111d is formed in the other. The AlN layer 102 functions as a buffer layer. The gate electrode 111g is in Schottky contact with the n-GaN layer 106, and the source electrode 111s and the drain electrode 111d are in ohmic contact with the n-AlGaN layer 105.

  In the conventional GaN-based HEMT configured as described above, the threshold voltage Vth exceeds 0V as shown in FIG. That is, a normally-off operation is possible.

  However, even in such a conventional GaN-based HEMT, the threshold voltage Vth is close to 0V. In the GaN-based HEMT, when a large drain voltage is applied, the threshold voltage Vth may change in the negative direction. For this reason, even in a conventional GaN HEMT capable of normally-off operation, when a large drain voltage is applied, a drain leakage current may flow from the drain electrode to the source electrode. This is apparent from the fact that the drain current is positive even when the gate voltage is 0 V in FIG.

JP 2006-114653 A

  An object of the present invention is to provide a compound semiconductor device that can suppress drain leakage current when a large drain voltage is applied, and a method for manufacturing the compound semiconductor device.

  In one aspect of the compound semiconductor device, a substrate, an electron transit layer formed above the substrate, an electron supply layer formed above the electron transit layer, and containing AlGaN, and formed on the electron supply layer, And a Schottky barrier layer containing InAlN. The lattice constant of the crystal constituting the Schottky barrier layer is larger than the lattice constant of the crystal constituting the electron supply layer, and the band gap of the material constituting the Schottky barrier layer constitutes the electron supply layer. It is larger than the band gap of the material.

  In the method for manufacturing a compound semiconductor device, an electron transit layer is formed above a substrate, and an electron supply layer containing AlGaN is formed above the electron transit layer. Further, a Schottky barrier layer containing InAlN is formed on the electron supply layer. The lattice constant of the crystal constituting the Schottky barrier layer is larger than the lattice constant of the crystal constituting the electron supply layer, and the band gap of the material constituting the Schottky barrier layer constitutes the electron supply layer. It is larger than the band gap of the material.

  According to the above compound semiconductor device or the like, since the appropriate Schottky barrier layer is provided on the electron supply layer, the two-dimensional electron gas contributing to the drain leakage current can be eliminated. Therefore, drain leakage current when a large drain voltage is applied can be suppressed.

It is sectional drawing which shows the structure of the conventional GaN-type HEMT. It is a figure which shows the characteristic of the conventional GaN-type HEMT. 1 is a cross-sectional view showing a structure of a GaN-based HEMT (compound semiconductor device) according to a first embodiment. 1 is a layout diagram showing a structure of a GaN-based HEMT according to a first embodiment. It is a figure which shows the band structure of the conduction band in 1st Embodiment. It is a figure which shows the relationship between the lattice constant and energy band gap in 1st Embodiment. It is a figure which shows the characteristic of GaN-type HEMT which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of GaN-type HEMT which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the GaN-type HEMT which concerns on 1st Embodiment following FIG. 8A. FIG. 8B is a cross-sectional view illustrating the method for manufacturing the GaN-based HEMT according to the first embodiment following FIG. 8B. 8C is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 8C. FIG. 8D is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 8D. It is sectional drawing which shows the structure of GaN-type HEMT (compound semiconductor device) which concerns on 2nd Embodiment. It is a figure which shows the relationship between the lattice constant and energy band gap in 2nd Embodiment. It is a figure which shows the characteristic of GaN-type HEMT which concerns on 2nd Embodiment. It is sectional drawing which shows the structure of GaN-type HEMT (compound semiconductor device) which concerns on 3rd Embodiment. It is a figure which shows the characteristic of GaN-type HEMT which concerns on 3rd Embodiment.

  Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

(First embodiment)
First, the first embodiment will be described. FIG. 3 is a sectional view showing the structure of a GaN-based HEMT (compound semiconductor device) according to the first embodiment.

In the first embodiment, an AlN layer 2 having a thickness of about 0.001 μm to 1 μm (for example, 0.3 μm) is formed on a substrate 1 such as a SiC substrate. A non-doped i-GaN layer 3 having a thickness of about 1 μm to 10 μm (for example, 2.5 μm) is formed on the AlN layer 2, and an undoped i-GaN layer having a thickness of about 1 nm to 30 nm (for example, 2 nm) is formed thereon. An AlGaN layer 4 is formed, and an n-type n-AlGaN layer 5 having a thickness of about 3 nm to 30 nm (for example, 8 nm) is formed thereon. The compositions of the i-AlGaN layer 4 and the n-AlGaN layer 5 are expressed as Al _x1 Ga _1-x1 N, and the value of x1 is about 0.1 to 0.5 (for example, 0.2). The n-AlGaN layer 5 is doped with Si at about 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ (for example, 1 × 10 ¹⁸ cm ⁻³ ).

A p-type p-InAlN layer 6 having a thickness of about 2 nm to 10 nm (for example, 5 nm) is formed on the n-AlGaN layer 5. The composition of the p-InAlN layer 6 is represented by In _y1 Al _1-y1 N, and the value of y1 is about 0.10 to 0.20 (for example, 0.18). The p-InAlN layer 6 is doped with about 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ (for example, 1 × 10 ¹⁸ cm ⁻³ ) of Mg.

A non-doped i-AlN layer 7 having a thickness of about 0.5 nm to 5 nm (for example, 2 nm) is formed on the p-InAlN layer 6, and an n layer having a thickness of about 2 nm to 20 nm (for example, 6 nm) is formed thereon. A type n-GaN layer 8 is formed, and a SiN layer 9 having a thickness of about 10 nm to 100 nm (for example, 40 nm) is formed thereon. The n-GaN layer 8 is doped with Si at about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ (for example, 5 × 10 ¹⁸ cm ⁻³ ).

  In the SiN layer 9, the n-GaN layer 8, and the i-AlN layer 7, an opening 10g for a gate electrode is formed. Further, the SiN layer 9, the n-GaN layer 8, the i-AlN layer 7, and the p-InAlN layer 6 have an opening 10s for a source electrode and an opening for a drain electrode with an opening 10g interposed therebetween. 10d is formed. A gate electrode 11g is formed in the opening 10g, a source electrode 11s is formed in the opening 10s, and a drain electrode 11d is formed in the opening 10d. The gate electrode 11g is composed of, for example, a Ni film and an Au film formed thereon. The source electrode 11s and the drain electrode 11d are composed of, for example, a Ta film and an Al film formed thereon. The gate electrode 11g is in Schottky contact with the p-InAlN layer 6, and the source electrode 11s and the drain electrode 11d are in ohmic contact with the n-AlGaN layer 5.

  The layout viewed from the front side of the substrate 1 is, for example, as shown in FIG. That is, the planar shape of the gate electrode 11g, the source electrode 11s, and the drain electrode 11d is a comb shape, and the source electrodes 11s and the drain electrodes 11d are alternately arranged. A gate electrode 11g is disposed between them. By adopting such a multi-finger gate structure, the output can be improved. Note that the cross-sectional view shown in FIG. 3 is a cross-sectional view taken along line II in FIG. The active region 10 includes the AlN layer 2 and the i-GaN layer 3 and the like, and the periphery of the active region 10 is made an inactive region by ion implantation or mesa etching.

  The band structure of the conduction band in the first embodiment is as shown in FIG. FIG. 5A shows the band structure in the depth direction in the region between the gate electrode 11g and the source electrode 11s or the drain electrode 11d, and FIG. 5B shows the depth direction in the region including the gate electrode 11g. The band structure of is shown.

  As shown in FIG. 5, the energy band gap of the p-InAlN layer 6 is larger than the energy band gaps of the n-AlGaN layer 5 and the i-AlGaN layer 4 located therebelow. Further, the energy band gap of the i-GaN layer 3 is smaller than the energy band gaps of the n-AlGaN layer 5 and the i-AlGaN layer 4 located thereon.

  In addition, high concentration carriers are generated at the heterojunction interface between the i-GaN layer 3 and the i-AlGaN layer 4 due to piezoelectric polarization. That is, electrons are induced in the vicinity of the interface between the i-GaN layer 3 and the i-AlGaN layer 4 due to the piezoelectric effect caused by lattice mismatch. As a result, a two-dimensional electron gas layer (2DEG) appears, and this part functions as an electron transit layer (channel). Further, the i-AlGaN layer 4 and the n-AlGaN layer 5 function as an electron supply layer.

  However, in this embodiment, the p-InAlN layer 6 is heterojunction with the n-AlGaN layer 5, and the lattice constant of the p-InAlN layer 6 is larger than the lattice constant of the n-AlGaN layer 5 as shown in FIG. 6. large. For this reason, a negative piezoelectric charge acting as an acceptor is generated at the heterojunction interface between them, and the energy band of the heterojunction interface is raised as shown in FIG. 5B. As a result, 2DEG disappears from the i-GaN layer 3 below the gate electrode 11g. Therefore, no leakage current flows when no voltage is applied to the gate electrode 11g.

  On the other hand, in the region between the gate electrode 11g and the source electrode 11s or the drain electrode 11d, there is a lattice mismatch between the i-AlN layer 7 and the p-InAlN layer 6, and the lattice constant of the i-AlN layer 7 is As shown in FIG. 6, it is smaller than the lattice constant of the p-InAlN layer 6. Therefore, positive piezoelectric charges acting as donors are generated at the heterojunction interface between the i-AlN layer 7 and the p-InAlN layer 6, and the energy band at the heterojunction interface is lowered as shown in FIG. . As a result, sufficient 2DEG is present in the i-GaN layer 3.

  Therefore, according to the GaN-based HEMT according to the present embodiment, not only a normally-off operation is possible, but in a state where no voltage is applied to the gate electrode 11g (off state), a leakage current is not generated even when a large drain voltage is applied. A large current can be obtained when it does not flow and is on.

  That is, as shown in FIG. 7, the threshold voltage Vth becomes higher than the conventional one, and the drain current becomes 0 when the gate voltage is 0V. In addition, as the drain current increases, the range of the gate voltage at which the drain current greatly increases with respect to the gate voltage is increased.

Instead of the p-type p-InAlN layer 6 functioning as a Schottky barrier layer, a non-doped InAlN layer may be used. The Schottky barrier layer may further contain Ga or the like. In this case, the composition of the Schottky barrier layer is represented by, for example, an (In _x Al _1-x ) _y Ga _1-y N layer (0 <x ≦ 1, 0 <y <1). The i-AlN layer 7 may contain Ga or the like. Further, the i-AlGaN layer 4 and the n-AlGaN layer 5 functioning as an electron supply layer may contain other elements.

  Further, a monolithic microwave integrated circuit (MMIC) may be formed by mounting resistors and capacitors.

  Next, a method for manufacturing a GaN-based HEMT (compound semiconductor device) according to the first embodiment will be described. 8A to 8E are cross-sectional views showing a method of manufacturing a GaN-based HEMT (compound semiconductor device) according to the first embodiment in the order of steps.

In the first embodiment, first, as shown in FIG. 8A, an AlN layer 2 and an i-GaN layer 3 are formed in this order on a substrate 1. Next, an i-AlGaN layer 4, an n-AlGaN layer 5, a p-InAlN layer 6, an i-AlN layer 7, and an n-GaN layer 8 are formed in this order on the i-GaN layer 3. The i-AlGaN layer 4, the n-AlGaN layer 5, the p-InAlN layer 6, the i-AlN layer 7, and the n-GaN layer 8 are formed by a crystal growth method such as a metal organic chemical vapor deposition (MOVPE) method. Do. In this case, these layers can be formed continuously by selecting a source gas. As a raw material for aluminum (Al), a raw material for gallium (Ga), and a raw material for indium (In), for example, trimethylaluminum, trimethylgallium, and trimethylindium can be used, respectively. Further, as a raw material of nitrogen (N), it can be used, for example ammonia (NH _3). Moreover, as a raw material of silicon (Si) contained as an impurity in the n-AlGaN layer 5 and the n-GaN layer 8, for example, silane (SiH ₄ ) can be used. Magnesium contained as an impurity in the p-InAlN layer 6 (as a raw material of Mg, for example, cyclopentamagnesium (Cp2Mg) can be used.

  After the n-GaN layer 8 is formed, the SiN layer 9 is formed thereon by, for example, a plasma CVD (chemical vapor deposition) method.

  Next, a resist pattern is formed on the SiN layer 9 to open a region where the source electrode 11s and the drain electrode 11d are to be formed. Thereafter, by using the resist pattern as a mask, the SiN layer 9, the n-GaN layer 8, the i-AlN layer 7, and the p-InAlN layer 6 are etched, as shown in FIG. An opening 10 s for a source electrode and an opening 10 d for a drain electrode are formed in the n-GaN layer 8, the i-AlN layer 7, and the p-InAlN layer 6. As this etching, for example, dry etching using a chlorine-based gas is performed. In addition, regarding the depths of the openings 10 s and 10 d, a part of the p-InAlN layer 6 may be left, or a part of the n-AlGaN layer 5 may be removed. That is, the depths of the openings 10 s and 10 d do not need to match the total thickness of the SiN layer 9, the n-GaN layer 8, the i-AlN layer 7, and the p-InAlN layer 6.

  Subsequently, as shown in FIG. 8C, a source electrode 11s and a drain electrode 11d are formed in the openings 10s and 10d, respectively, by a lift-off method. In the formation of the source electrode 11s and the drain electrode 11d, after removing the resist pattern used when forming the openings 10s and 10d, a new resist pattern is formed that opens the region where the source electrode 11s and the drain electrode 11d are to be formed. Then, Ta and Al are vapor-deposited, and then the Ta and Al adhered on the resist pattern are removed together with the resist pattern. The thicknesses of the Ta film and Al film are, for example, about 30 nm and about 200 nm, respectively. And it heat-processes at 400 to 1000 degreeC, for example, 600 degreeC in nitrogen atmosphere, and establishes ohmic characteristics.

  After the formation of the source electrode 11s and the drain electrode 11d, a resist pattern is formed that opens a region where the opening 10g is to be formed. Next, etching using a resist pattern is performed to form an opening 10g in the SiN layer 9, the n-GaN layer 8, and the i-AlN layer 7, as shown in FIG. 8D. As this etching, for example, dry etching using a chlorine-based gas and wet etching using an acid are combined. This is to reliably remove the i-AlN layer 7 while avoiding the etching of the p-InAlN layer 6.

  Thereafter, as shown in FIG. 8E, a gate electrode 11g is formed in the opening 10g by a lift-off method. In the formation of the gate electrode 11g, after removing the resist pattern used when forming the opening 10g, a new resist pattern that opens the region where the gate electrode 11g is formed is formed, and Ni and Au are deposited. Thereafter, Ni and Au attached on the resist pattern are removed together with the resist pattern. The thicknesses of the Ni film and Au film are, for example, about 30 nm and about 400 nm, respectively.

  With such a manufacturing method, a GaN-based HEMT having the structure shown in FIG. 7 can be obtained.

  The gate length of the gate electrode 11g, that is, the length in the direction connecting the source electrode 11s and the drain electrode 11d is about 0.5 μm to 5 μm (for example, 2 μm). The unit gate width, that is, the length in the direction orthogonal to the gate length direction is about 200 μm to 1000 μm (for example, 400 μm).

(Second Embodiment)
Next, a second embodiment will be described. FIG. 9 is a cross-sectional view showing the structure of a GaN-based HEMT (compound semiconductor device) according to the second embodiment.

In the second embodiment, a non-doped i-InAlN layer 16 having a thickness of about 2 nm to 20 nm (for example, 5 nm) is provided in place of the p-InAlN layer 6 in the first embodiment. The composition of the i-InAlN layer 16 is represented by In _y2 Al ₁ -y2 N, and the value of y2 decreases as it approaches the lower surface from the upper surface, is 0.23 on the upper surface, and is 0.15 on the lower surface. . That is, the i-InAlN layer 16 has the largest amount of In at the interface with the i-AlN layer 7 and the smallest amount at the interface with the n-AlGaN layer 5. Further, in order to keep the lattice constant on the lower surface (y2 = 0.15) of the i-InAlN layer 16 larger than the lattice constant of the n-AlGaN layer 5, the value of x1 is 0.4, for example. That is, the composition of the n-AlGaN layer 5 is represented by, for example, Al _0.4 Ga _0.6 N.

  Other configurations are the same as those of the first embodiment.

  The effect similar to 1st Embodiment can be acquired also by such 2nd Embodiment. Further, while the ratio of In in the p-InAlN layer 6 in the first embodiment is constant (for example, y1 = 0.18), in the second embodiment, the In content in the i-InAlN layer 16 is increased. The ratio changes (for example, y2 = 0.15 (interface with the n-AlGaN layer 5) to 0.23 (interface with the i-AlN layer 7)), and the ratio of In at the interface with the i-AlN layer 7 is It is high. For this reason, as shown in FIG. 10, the difference in lattice constant between the i-AlN layer 7 is large, 2DEG can be generated as compared with the first embodiment, and the on-current can be increased. In addition, since the difference in lattice constant at the interface with the n-AlGaN layer 5 is small, internal stress can be suppressed.

  Therefore, the threshold voltage Vth is further increased as shown in FIG. In addition, the drain current when the gate voltage is transferred positively further increases, and the rate at which the drain current increases with respect to the gate voltage (current amplification factor) also increases.

  When manufacturing the GaN-based HEMT according to the second embodiment, instead of forming the p-InAlN layer 6 in the first embodiment, the flow rate of the In and Al raw materials is gradually changed. The InAlN layer 16 may be formed.

  Note that the amount of 2DEG increases as the proportion of In on the upper surface side in the p-InAlN layer 6 or i-InAlN layer 16 increases, but when the energy band gap of these layers is lower than the energy band gap of GaN, The forward leakage current from the side surface of the gate electrode 11g increases. For this reason, the ratio of In is preferably in a range where the energy band gap of the p-InAlN layer 6 or the i-InAlN layer 16 is equal to or larger than the energy band gap of GaN. The lattice constant of the lower surface of the i-InAlN1 layer 6 is preferably larger than that of the n-AlGaN layer 5 and smaller than that of GaN. This is because if the lattice constant of the lower surface of the i-InAlN1 layer 6 is not larger than the lattice constant of the n-AlGaN layer 5, negative piezoelectric charges acting as acceptors may not be generated. Furthermore, the lattice constant of the lower surface of the i-InAlN layer 16 is smaller than that of the i-GaN layer 3 in order not to reduce the piezoelectric charge of the donor at the interface between the i-AlGaN layer 4 and the i-GaN layer 3. desirable. When the lattice constant of the lower surface of the i-InAlN layer 16 is not smaller than the lattice constant of the i-GaN layer 3, the donors at the interface between the i-AlGaN layer 4 and the i-GaN layer 3 are reduced due to the reverse strain. Because there are things.

  Further, a p-type InAlN layer may be used instead of the non-doped i-InAlN layer 16 functioning as a Schottky barrier layer. Moreover, the change of the ratio of In and Al does not need to be continuous, and may change in steps.

(Third embodiment)
Next, a third embodiment will be described. FIG. 12 is a cross-sectional view showing the structure of a GaN-based HEMT (compound semiconductor device) according to the third embodiment.

In the third embodiment, a tantalum oxide film (Ta ₂ O ₅ film) 17 having a thickness of about ₂ nm to 40 nm (for example, 10 nm) is formed along the inner surface of the opening 10g. A gate electrode 11g is provided in the opening 10g via the tantalum oxide film 17. The tantalum oxide film 17 covers the SiN layer 9, the source electrode 11s, and the drain electrode 11d. The tantalum oxide film 17 can be formed by atomic layer deposition (ALD), for example. In this case, for example, Ta organic substance and oxygen plasma may be introduced into the reaction furnace at 350 ° C. to form a film, and then annealing may be performed at 600 ° C. for 10 minutes to desorb hydrogen. Instead of the tantalum oxide film 17, a hafnium oxide film, an aluminum oxide film, or an oxide film of a mixture thereof may be formed as an insulating film, or an oxynitride (ON) film may be formed as an insulating film. You may form as.

  Other configurations are the same as those of the second embodiment.

  The effect similar to 2nd Embodiment can be acquired also by such 3rd Embodiment. In the second embodiment, a Schottky gate structure is adopted, whereas in the third embodiment, an insulated gate structure is adopted. For this reason, as shown in FIG. 13, the threshold voltage Vth is further increased. In addition, the drain current is further increased, and the range of the gate voltage at which the drain current greatly increases with respect to the gate voltage is further increased.

  In the third embodiment, a p-InAlN layer 6 may be provided instead of the i-InAlN layer 16.

  In any of the embodiments, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon substrate, a GaN substrate, a GaAs substrate, or the like may be used as the substrate 1. The substrate 1 may be conductive, semi-insulating, or insulating.

  Further, the structures of the gate electrode 11g, the source electrode 11s, and the drain electrode 11d are not limited to those of the above-described embodiment. For example, these may be composed of a single layer. Moreover, these formation methods are not limited to the lift-off method. Furthermore, if ohmic characteristics can be obtained, the heat treatment after the formation of the source electrode 11s and the drain electrode 11d may be omitted. Further, heat treatment may be performed on the gate electrode 11g.

  Further, the thickness and material of each layer are not limited to those of the above-described embodiment.

1: Substrate 2: AlN layer 3: i-GaN layer 4: i-AlGaN layer 5: n-AlGaN layer 6: p-InAlN layer 7: i-AlN layer 8: n-GaN layer 9: SiN layer 10: active Region 10g, 10s, 10d: Opening 11d: Drain electrode 11g: Gate electrode 11s: Source electrode 16: i-InAlN layer 17: Tantalum oxide film

Claims (6)

A substrate,
An electron transit layer formed above the substrate;
An electron supply layer formed above the electron transit layer and containing AlGaN;
A Schottky barrier layer formed on the electron supply layer and containing InAlN;
Have
The lattice constant of the crystal constituting the Schottky barrier layer is larger than the lattice constant of the crystal constituting the electron supply layer,
A compound semiconductor device, wherein a band gap of a material constituting the Schottky barrier layer is larger than a band gap of a material constituting the electron supply layer.   2. The compound semiconductor device according to claim 1, wherein the proportion of In in the Schottky barrier layer increases as the distance from the electron supply layer increases. A source electrode and a drain electrode that are in ohmic contact with the electron supply layer;
A gate electrode in Schottky contact with the Schottky barrier layer between the source electrode and the drain electrode;
The compound semiconductor device according to claim 1, comprising: A source electrode and a drain electrode that are in ohmic contact with the electron supply layer;
An insulating film formed on the Schottky barrier layer between the source electrode and the drain electrode;
A gate electrode formed on the insulating film;
The compound semiconductor device according to claim 1, comprising: The composition of the Schottky barrier layer is represented by an (In _x Al _1-x ) _y Ga _1-y N layer (0 <x ≦ 1, 0 <y <1). The compound semiconductor device according to any one of the above. Forming an electron transit layer above the substrate;
Forming an electron supply layer containing AlGaN above the electron transit layer;
Forming a Schottky barrier layer containing InAlN on the electron supply layer;
Have
The lattice constant of the crystal constituting the Schottky barrier layer is larger than the lattice constant of the crystal constituting the electron supply layer,
A method for manufacturing a compound semiconductor device, wherein a band gap of a material constituting the Schottky barrier layer is larger than a band gap of a material constituting the electron supply layer.

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