JP2013128190A5 - - Google Patents

Download PDF

Info

Publication number
JP2013128190A5
JP2013128190A5 JP2011276620A JP2011276620A JP2013128190A5 JP 2013128190 A5 JP2013128190 A5 JP 2013128190A5 JP 2011276620 A JP2011276620 A JP 2011276620A JP 2011276620 A JP2011276620 A JP 2011276620A JP 2013128190 A5 JP2013128190 A5 JP 2013128190A5
Authority
JP
Japan
Prior art keywords
memory
resistance element
wiring
transmission system
load capacity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2011276620A
Other languages
English (en)
Japanese (ja)
Other versions
JP5703206B2 (ja
JP2013128190A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2011276620A priority Critical patent/JP5703206B2/ja
Priority claimed from JP2011276620A external-priority patent/JP5703206B2/ja
Priority to US13/586,104 priority patent/US8866282B2/en
Publication of JP2013128190A publication Critical patent/JP2013128190A/ja
Publication of JP2013128190A5 publication Critical patent/JP2013128190A5/ja
Application granted granted Critical
Publication of JP5703206B2 publication Critical patent/JP5703206B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2011276620A 2011-12-19 2011-12-19 半導体装置、信号伝送システム及び信号伝送方法 Expired - Fee Related JP5703206B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2011276620A JP5703206B2 (ja) 2011-12-19 2011-12-19 半導体装置、信号伝送システム及び信号伝送方法
US13/586,104 US8866282B2 (en) 2011-12-19 2012-08-15 Semiconductor apparatus, signal transmission system and signal transmission method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011276620A JP5703206B2 (ja) 2011-12-19 2011-12-19 半導体装置、信号伝送システム及び信号伝送方法

Publications (3)

Publication Number Publication Date
JP2013128190A JP2013128190A (ja) 2013-06-27
JP2013128190A5 true JP2013128190A5 (enExample) 2014-03-13
JP5703206B2 JP5703206B2 (ja) 2015-04-15

Family

ID=48778485

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011276620A Expired - Fee Related JP5703206B2 (ja) 2011-12-19 2011-12-19 半導体装置、信号伝送システム及び信号伝送方法

Country Status (2)

Country Link
US (1) US8866282B2 (enExample)
JP (1) JP5703206B2 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9852988B2 (en) 2015-12-18 2017-12-26 Invensas Bonding Technologies, Inc. Increased contact alignment tolerance for direct bonding
US9544864B1 (en) 2016-03-07 2017-01-10 Panasonic Liquid Crystal Display Co., Ltd. Data transmission system and receiving device
US10446487B2 (en) * 2016-09-30 2019-10-15 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10580735B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Stacked IC structure with system level wiring on multiple sides of the IC die
KR20190092584A (ko) 2016-12-29 2019-08-07 인벤사스 본딩 테크놀로지스 인코포레이티드 집적된 수동 컴포넌트를 구비한 접합된 구조체
US10276909B2 (en) 2016-12-30 2019-04-30 Invensas Bonding Technologies, Inc. Structure comprising at least a first element bonded to a carrier having a closed metallic channel waveguide formed therein
US10629577B2 (en) 2017-03-16 2020-04-21 Invensas Corporation Direct-bonded LED arrays and applications
WO2018183739A1 (en) 2017-03-31 2018-10-04 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US11169326B2 (en) 2018-02-26 2021-11-09 Invensas Bonding Technologies, Inc. Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US11256004B2 (en) 2018-03-20 2022-02-22 Invensas Bonding Technologies, Inc. Direct-bonded lamination for improved image clarity in optical devices
US11515291B2 (en) 2018-08-28 2022-11-29 Adeia Semiconductor Inc. Integrated voltage regulator and passive components
US11901281B2 (en) 2019-03-11 2024-02-13 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
JP7406895B2 (ja) * 2019-10-23 2023-12-28 キヤノン株式会社 情報処理装置および情報処理装置の制御方法
US11762200B2 (en) 2019-12-17 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded optical devices
JP7449785B2 (ja) * 2020-06-17 2024-03-14 日立Astemo株式会社 電子制御装置、判定方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2870288B2 (ja) * 1992-03-17 1999-03-17 株式会社日立製作所 双方向信号伝送回路
JPH1065744A (ja) * 1996-08-13 1998-03-06 Oki Electric Ind Co Ltd バスインターフェース回路
JPH11122142A (ja) * 1997-10-14 1999-04-30 Pfu Ltd 伝送路における波形割れ除去装置
JP2003134177A (ja) * 2001-10-25 2003-05-09 Nec Corp デジタル信号伝送回路の設計方法
JP4221238B2 (ja) * 2002-09-26 2009-02-12 エルピーダメモリ株式会社 メモリモジュール
JP2004281960A (ja) * 2003-03-19 2004-10-07 Renesas Technology Corp 符号間干渉抑制抵抗を用いた超高速インタフェース
JP4972270B2 (ja) * 2003-11-19 2012-07-11 独立行政法人科学技術振興機構 高周波用配線構造及び高周波用配線構造の形成方法並びに高周波信号の波形整形方法
US7224180B2 (en) * 2004-11-18 2007-05-29 Seiko Epson Corporation Methods and systems for rise-time improvements in differential signal outputs
JP4855101B2 (ja) * 2005-02-25 2012-01-18 三菱電機株式会社 信号伝送回路、ｉｃパッケージ及び実装基板
JP5197080B2 (ja) * 2008-03-19 2013-05-15 ルネサスエレクトロニクス株式会社 半導体装置及びデータプロセッサ
JP5610970B2 (ja) * 2010-10-19 2014-10-22 キヤノン株式会社 プリント回路板

Similar Documents

Publication Publication Date Title
JP2013128190A5 (enExample)
JP2017502444A5 (enExample)
EP2884535A3 (en) Packaging DRAM and SOC in an IC package
WO2015019197A3 (en) Computational imaging pipeline
TW201613066A (en) Package-on-package options with multiple layer 3-D stacking
WO2010138480A3 (en) Stacked semiconductor device assembly
IN2015DN02935A (enExample)
WO2012082480A3 (en) Multi-die dram banks arrangement and wiring
JP2011171723A5 (ja) 信号処理回路
WO2011100444A3 (en) Memory dies, stacked memories, memory devices and methods
JP2010187510A5 (enExample)
WO2012087548A3 (en) Vector conflict instructions
JP2014158250A5 (enExample)
JP2013251888A5 (enExample)
EP2760048A3 (en) Manufacturing method of semiconductor device
JP2011014894A5 (enExample)
JP2013009306A5 (enExample)
JP2012084862A5 (enExample)
WO2014088639A3 (en) Iii-n semiconductor-on-silicon structures and techniques
WO2013121085A3 (en) Method, apparatus, and computer program product for inter-core communication in multi-core processors
JP2016149550A5 (ja) 半導体装置
JP2013145952A5 (enExample)
WO2013181603A3 (en) Inter-chip memory interface structure
IN2014DE00712A (enExample)
WO2014160009A3 (en) Microelectronic elements with master/slave configurability