JP2013073660A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2013073660A
JP2013073660A JP2011213698A JP2011213698A JP2013073660A JP 2013073660 A JP2013073660 A JP 2013073660A JP 2011213698 A JP2011213698 A JP 2011213698A JP 2011213698 A JP2011213698 A JP 2011213698A JP 2013073660 A JP2013073660 A JP 2013073660A
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JP
Japan
Prior art keywords
signal
inverter
output
circuit
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
JP2011213698A
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English (en)
Japanese (ja)
Other versions
JP2013073660A5 (enExample
Inventor
Takenori Sato
武範 佐藤
Shinya Miyazaki
晋也 宮崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Hitachi Solutions Technology Ltd
Original Assignee
Hitachi ULSI Systems Co Ltd
Elpida Memory Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi ULSI Systems Co Ltd, Elpida Memory Inc filed Critical Hitachi ULSI Systems Co Ltd
Priority to JP2011213698A priority Critical patent/JP2013073660A/ja
Priority to US13/610,541 priority patent/US8653874B2/en
Publication of JP2013073660A publication Critical patent/JP2013073660A/ja
Publication of JP2013073660A5 publication Critical patent/JP2013073660A5/ja
Abandoned legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Dram (AREA)
  • Manipulation Of Pulses (AREA)
JP2011213698A 2011-09-29 2011-09-29 半導体装置 Abandoned JP2013073660A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2011213698A JP2013073660A (ja) 2011-09-29 2011-09-29 半導体装置
US13/610,541 US8653874B2 (en) 2011-09-29 2012-09-11 Semiconductor device generates complementary output signals

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011213698A JP2013073660A (ja) 2011-09-29 2011-09-29 半導体装置

Publications (2)

Publication Number Publication Date
JP2013073660A true JP2013073660A (ja) 2013-04-22
JP2013073660A5 JP2013073660A5 (enExample) 2014-11-13

Family

ID=47991981

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011213698A Abandoned JP2013073660A (ja) 2011-09-29 2011-09-29 半導体装置

Country Status (2)

Country Link
US (1) US8653874B2 (enExample)
JP (1) JP2013073660A (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140146368A (ko) * 2013-06-17 2014-12-26 에스케이하이닉스 주식회사 입출력 장치 및 이를 포함하는 입출력 시스템
EP3934096A1 (en) * 2020-06-29 2022-01-05 Ams Ag Driver circuit for low voltage differential signaling, lvds, line driver arrangement for lvds and method for operating an lvds driver circuit
US20250300645A1 (en) * 2024-03-21 2025-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. System, Device, and Method for Transforming a Single-Ended Input Signal Into Differential Output Signals

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100263485B1 (ko) * 1998-04-25 2000-08-01 김영환 위상 분리기
US6304122B1 (en) * 2000-08-17 2001-10-16 International Business Machines Corporation Low power LSSD flip flops and a flushable single clock splitter for flip flops
US6420920B1 (en) * 2000-08-28 2002-07-16 Micron Technology, Inc. Method and apparatus for phase-splitting a clock signal
KR100432883B1 (ko) * 2001-12-18 2004-05-22 삼성전자주식회사 클럭 듀티/스큐 보정 기능을 갖는 위상 분주 회로
US6664836B1 (en) * 2002-12-12 2003-12-16 International Business Machines Corporation Dynamic phase splitter circuit and method for low-noise and simultaneous production of true and complement dynamic logic signals
KR101120047B1 (ko) * 2007-04-25 2012-03-23 삼성전자주식회사 단일 신호-차동 신호 변환기 및 변환 방법
KR100892647B1 (ko) * 2007-08-13 2009-04-09 주식회사 하이닉스반도체 반도체 메모리 장치의 클럭 생성 회로
JP4600467B2 (ja) 2007-12-03 2010-12-15 富士通セミコンダクター株式会社 電子装置及びダブル・データ・レート・シンクロナス・ダイナミック・ランダム・アクセス・メモリ

Also Published As

Publication number Publication date
US8653874B2 (en) 2014-02-18
US20130082743A1 (en) 2013-04-04

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