JP2013070034A - マルチチップ半導体パッケージ及びその形成方法 - Google Patents
マルチチップ半導体パッケージ及びその形成方法 Download PDFInfo
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- JP2013070034A JP2013070034A JP2012172674A JP2012172674A JP2013070034A JP 2013070034 A JP2013070034 A JP 2013070034A JP 2012172674 A JP2012172674 A JP 2012172674A JP 2012172674 A JP2012172674 A JP 2012172674A JP 2013070034 A JP2013070034 A JP 2013070034A
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Abstract
【解決手段】上面に第1突出電極17を有する第1半導体チップ11を準備する。前記第1半導体チップ上に第2突出電極27を有する第2半導体チップ21を前記第1突出電極が露出されるように搭載する。前記第1突出電極と前記第2突出電極との間に絶縁膜8を形成する。前記絶縁膜内に溝18Gを形成する。前記溝の内部を埋め込み、前記第1突出電極及び前記第2突出電極と接続される相互接続18を形成する。
【選択図】図1
Description
図11A及び図11Bを参照すると、第4半導体チップ41上に再配線フロア123が形成されることができる。再配線フロア123は、第1再配線パッド124、内部配線125及び第2再配線パッド126を含むことができる。第1再配線パッド124は第4チップパッド46に接続されることができる。第1再配線パッド124上に第4突出電極47が形成されることができる。第2再配線パッド126は内部配線125を経由して第1再配線パッド124に電気的に接続されることができる。第2再配線パッド126上に再配線突出電極127が形成されることができる。
3、213 基板
5A、5B、225 外部端子
6 フィンガー電極
7 基板突出電極
8 絶縁膜
11、21、31、41、51、61、71、81 半導体チップ
10、50 チップスタック
16、26、36、46、56、66、76、86 チップパッド
16A、26A UBM(under bump metal)
17、27、37、47、57、67、77、87 突出電極
18G、28G、38G、48G 溝
18M、28M、38M、48M 導電性物質
18、28、38、48、58、68、78、88 相互接続
92、292 封止材
113 インタポーザ
114 下部パッド
115 内部配線
116 上部パッド
117 インタポーザ突出電極
123 再配線フロア
124、126 再配線パッド
125 内部配線125
127 再配線突出電極
211 ロジックチップ
291 支持台
295 バッファチップ
1900 携帯電話
2100 電子システム
2110 ボディ
2120 マイクロプロセッサユニット
2130 パワーユニット
2140 機能ユニット
2150 ディスプレイコントローラユニット
2160 ディスプレイユニット
2170 外部装置
2180 通信ユニット
Claims (10)
- 上面に第1突出電極を有する第1半導体チップを準備する工程と、
第2突出電極を有する第2半導体チップを前記第1突出電極が露出されるように前記第1半導体チップ上に搭載する工程と、
前記第1突出電極と前記第2突出電極との間に絶縁膜を形成する工程と、
前記絶縁膜内に溝を形成する工程と、
前記溝の内部を埋め込み、前記第1突出電極及び前記第2突出電極と接続される相互接続を形成する工程と、を含むことを特徴とする半導体パッケージ形成方法。 - 前記溝を形成する工程が、
前記溝の幅を前記第1突出電極の幅よりも狭く形成する工程を含むことを特徴とする、請求項1に記載の半導体パッケージ形成方法。 - 前記溝を形成する工程が、
レーザを用いて前記絶縁膜の一部を除去する工程を含むことを特徴とする、請求項1に記載の半導体パッケージ形成方法。 - 前記相互接続を形成する工程が、
前記第2突出電極の一部を溶融して前記溝を埋め込む工程を含むことを特徴とする、請求項1に記載の半導体パッケージ形成方法。 - 前記相互接続が前記第2突出電極と同一物質からなる膜を含み、前記相互接続が前記第2突出電極と物質的に連続であることを特徴とする、請求項1に記載の半導体パッケージ形成方法。
- 前記相互接続を形成する工程が、
前記溝内に導電性ペースト、導電性ボール、またはこれらの組み合わせを提供する工程を含むことを特徴とする、請求項1に記載の半導体パッケージ形成方法。 - 前記相互接続が、前記第1突出電極及び前記第2突出電極よりも低い温度で溶融する物質を含むことを特徴とする、請求項1に記載の半導体パッケージ形成方法。
- 前記相互接続が、水平幅よりも大きい垂直深さを有することを特徴とする、請求項1に記載の半導体パッケージ形成方法。
- 前記相互接続が、前記絶縁膜の上部表面の一部を覆うことを特徴とする、請求項1に記載の半導体パッケージ形成方法。
- 第1チップパッド及び前記第1チップパッド上に形成された第1レーザブロッキング電極を有する第1半導体チップ、並びに第2チップパッド及び前記第2チップパッド上に形成された第2レーザブロッキング電極を有する第2半導体チップを準備する工程と、
前記第1レーザブロッキング電極が露出されるように前記第2半導体チップを前記第1半導体チップ上に搭載する工程と、
前記第1レーザブロッキング電極及び前記第2レーザブロッキング電極との間に絶縁膜を形成する工程と、
レーザを用いて前記絶縁膜内に溝を形成する工程と、
前記第1レーザブロッキング電極及び前記第2レーザブロッキング電極と接触する相互接続を前記溝内に形成する工程と、を含むことを特徴とする半導体パッケージ形成方法。
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KR20180130043A (ko) * | 2017-05-25 | 2018-12-06 | 에스케이하이닉스 주식회사 | 칩 스택들을 가지는 반도체 패키지 |
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US8772084B2 (en) | 2014-07-08 |
KR20130032187A (ko) | 2013-04-01 |
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