JP2013012598A - 抵抗変化メモリ及びその製造方法 - Google Patents
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
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- Mram Or Spin Memory Techniques (AREA)
- Semiconductor Memories (AREA)
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Abstract
【解決手段】実施形態に係わる抵抗変化メモリは、第1の方向及びこれに直交する第2の方向にそれぞれ交互に配置される複数の抵抗変化素子MTJ及び複数のビアV0と、複数の抵抗変化素子MTJの側壁上に配置される複数の側壁絶縁層PLとを備える。複数の抵抗変化素子MTJは、一定ピッチで格子状に配置され、複数の側壁絶縁層PLの側壁に垂直な方向の厚さは、複数の側壁絶縁層PLが互いに部分的に接触し、複数の側壁絶縁層PL間に複数のホールが形成される値に設定される。複数のビアV0は、これら複数のホール内に配置される。
【選択図】図1
Description
抵抗変化メモリの製造プロセスにおいて、PEP数の削減を図るために、抵抗変化素子と同一層内に配置されるビアを、PEPを用いることなく、セルフアラインで形成することが可能なプロセス技術を提案する。
t≧(√2×F)−Sm/2
に設定すれば、側壁絶縁層PL同士を互いに部分的に接触させることにより、複数の側壁絶縁層PL間にセルフアラインで複数のホールを形成できる。
Sc=4F−Sm−2t
となる。
t≧{((2×√2)−1)×F}/2
となる。
Sc=2×(2−√2)×F
となる。
抵抗変化メモリの製造方法について説明する。
本例では、上述の第1の基本構造を製造する方法を説明する。
上述の第1又は第2の基本構造が適用された抵抗変化メモリを説明する。
実施形態によれば、抵抗変化メモリの製造プロセスにおいて、PEP数を削減し、製造コストの低下を図ることができる。
Claims (5)
- 第1の方向及びこれに直交する第2の方向にそれぞれ交互に配置される複数の抵抗変化素子及び複数のビアと、前記複数の抵抗変化素子の側壁上に配置される複数の側壁絶縁層とを具備し、
前記複数の抵抗変化素子は、一定ピッチで格子状に配置され、前記複数の側壁絶縁層の前記側壁に垂直な方向の厚さは、前記複数の側壁絶縁層が互いに部分的に接触し、前記複数の側壁絶縁層間に複数のホールが形成される値に設定され、
前記複数のビアは、前記複数のホール内に配置される
抵抗変化メモリの製造方法において、
前記複数の抵抗変化素子を形成する工程と、
前記複数の抵抗変化素子を覆う絶縁材料を形成する工程と、
前記絶縁材料のエッチバックを行うことにより、前記複数の側壁絶縁層を形成すると同時に前記複数のホールをセルフアラインで形成する工程と、
前記複数のホール内に前記複数のビアを形成する工程と
を具備する抵抗変化メモリの製造方法。 - 前記エッチバックは、前記複数の抵抗変化素子が露出するまで行い、
前記複数のビアを形成すると同時に、各々が前記複数のビアのうちの1つ及び前記複数の抵抗変化素子のうちの1つに接続される複数の上部電極を形成する
請求項1に記載の抵抗変化メモリの製造方法。 - 第1の方向及びこれに直交する第2の方向にそれぞれ交互に配置される複数の抵抗変化素子及び複数のビアと、前記複数の抵抗変化素子の側壁上に配置される複数の側壁絶縁層とを具備し、
前記複数の抵抗変化素子は、一定ピッチで格子状に配置され、前記複数の側壁絶縁層の前記側壁に垂直な方向の厚さは、前記複数の側壁絶縁層が互いに部分的に接触し、前記複数の側壁絶縁層間に複数のホールが形成される値に設定され、
前記複数のビアは、前記複数のホール内に配置される
抵抗変化メモリ。 - 前記複数の側壁絶縁層の各々は、第1の材料を備える第1の層と、前記第1の材料とは異なる第2の層とを含む請求項3に記載の抵抗変化メモリ。
- 前記複数の抵抗変化素子及び前記複数のビアのうち前記第1の方向に隣接する第1の抵抗変化素子と第1のビアとの間に接続される第1のFETと、
前記複数の抵抗変化素子及び前記複数のビアのうち前記第1の方向に隣接する第2の抵抗変化素子と第2のビアとの間に接続される第2のFETと、
前記第1のFETのゲートに接続され、前記第2の方向に延びる第1のワード線と、
前記第2のFETのゲートに接続され、前記第2の方向に延びる第2のワード線と、
前記第1の抵抗変化素子に接続される第1の上部電極と、
前記第1のビア及び前記第2の抵抗変化素子に接続される第2の上部電極と、
前記第2のビアに接続される第3の上部電極と、
前記第1及び第3の上部電極に接続され、前記第1の方向に延びる第1のビット線と、
前記第2の上部電極に接続され、前記第1の方向に延びる第2のビット線とを具備し、
前記第1及び第2の抵抗変化素子は、前記一定ピッチで互いに隣接する
請求項3に記載の抵抗変化メモリ。
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