JP2013004779A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Semiconductor device and semiconductor device manufacturing method Download PDF

Info

Publication number
JP2013004779A
JP2013004779A JP2011135111A JP2011135111A JP2013004779A JP 2013004779 A JP2013004779 A JP 2013004779A JP 2011135111 A JP2011135111 A JP 2011135111A JP 2011135111 A JP2011135111 A JP 2011135111A JP 2013004779 A JP2013004779 A JP 2013004779A
Authority
JP
Japan
Prior art keywords
electrode pad
semiconductor device
metal layer
aluminum
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2011135111A
Other languages
Japanese (ja)
Inventor
Masanobu Sueishi
政信 末石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanken Electric Co Ltd
Original Assignee
Sanken Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanken Electric Co Ltd filed Critical Sanken Electric Co Ltd
Priority to JP2011135111A priority Critical patent/JP2013004779A/en
Publication of JP2013004779A publication Critical patent/JP2013004779A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/45565Single coating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/45599Material
    • H01L2224/456Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/45664Palladium (Pd) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48475Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48491Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being an additional member attached to the bonding area through an adhesive or solder, e.g. buffer pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48599Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a semiconductor device manufacturing method which avoids damages on a semiconductor element below an electrode pad at the time of bonding by a Cu wire.SOLUTION: A semiconductor device which can be electrically connected by a bonding wire consisting primarily of copper, comprises: a semiconductor element 10; an electrode pad 20 arranged on the semiconductor element 10 and composed of a metal harder than aluminum; and a metal layer 30 arranged on the electrode pad 20 and composed of an aluminum film to which the bonding wire is connected.

Description

本発明は、ボンディングワイヤが接続される電極パッドを有する半導体装置及び半導体装置の製造方法に関する。   The present invention relates to a semiconductor device having an electrode pad to which a bonding wire is connected and a method for manufacturing the semiconductor device.

半導体装置の電気的接続を行う接続部材として、銅(Cu)を主成分とするボンディングワイヤ(以下において「Cuワイヤ」という。)が用いられている。Cuワイヤは、金(Au)を主成分とするAuワイヤに比べて安価であるという利点がある。   A bonding wire (hereinafter referred to as “Cu wire”) containing copper (Cu) as a main component is used as a connection member for electrical connection of a semiconductor device. The Cu wire is advantageous in that it is cheaper than the Au wire mainly composed of gold (Au).

このため、Cuワイヤによるボンディング技術として種々の提案がなされている。例えば、硬いCuワイヤに対応するために、アルミニウム(Al)を主成分とする電極パッドに比較的高い割合でCuを添加する方法などが提案されている(例えば、特許文献1参照。)。Alを主成分とする電極パッドにCuを添加することにより、電極パッドの硬度が高まる。これにより、電極パッドにCuワイヤをボンディングした時の衝撃や振動のエネルギーを効果的に受けることができる。   For this reason, various proposals have been made as bonding techniques using Cu wires. For example, in order to cope with a hard Cu wire, a method of adding Cu at a relatively high rate to an electrode pad mainly composed of aluminum (Al) has been proposed (for example, see Patent Document 1). By adding Cu to the electrode pad mainly composed of Al, the hardness of the electrode pad is increased. Thereby, it is possible to effectively receive the energy of impact and vibration when the Cu wire is bonded to the electrode pad.

特開平1−187832号公報Japanese Patent Laid-Open No. 1-187832

しかしながら、Alを主成分とする電極パッドのCuの含有率を上げることによって、電極パッド表面のCuの酸化が進む。このため、ワイヤーボンディング時に新生面が出づらくなり、電極パッドとCuワイヤとの接合強度の低下を防ぐために接合時のパワーを上げる必要がある。その結果、硬いCuワイヤーによるボンディング時に、電極パッド下の半導体素子に損傷を与えるという問題があった。   However, by increasing the Cu content of the electrode pad mainly composed of Al, the oxidation of Cu on the electrode pad surface proceeds. For this reason, it becomes difficult for a new surface to appear at the time of wire bonding, and it is necessary to increase the power at the time of bonding in order to prevent a decrease in bonding strength between the electrode pad and the Cu wire. As a result, there is a problem that the semiconductor element under the electrode pad is damaged at the time of bonding with a hard Cu wire.

上記問題点に鑑み、本発明は、Cuワイヤーによるボンディング時に電極パッド下の半導体素子に損傷が生じない半導体装置及び半導体装置の製造方法を提供することを目的とする。   In view of the above problems, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device, in which a semiconductor element under an electrode pad is not damaged during bonding with a Cu wire.

本発明の一態様によれば、銅を主成分とするボンディングワイヤによる電気的接続が可能な半導体装置であって、半導体素子と、半導体素子上に配置されたアルミニウムよりも硬い金属からなる電極パッドと、電極パッド上に配置された、ボンディングワイヤが接続されるアルミニウム膜からなる金属層とを備える半導体装置が提供される。   According to one aspect of the present invention, a semiconductor device capable of electrical connection using a bonding wire containing copper as a main component, the electrode pad comprising a semiconductor element and a metal harder than aluminum disposed on the semiconductor element And a metal layer formed on the electrode pad and made of an aluminum film to which a bonding wire is connected.

本発明の他の態様によれば、半導体素子と、記半導体素子上に配置され、アルミニウムよりも硬い金属からなる電極パッドと、電極パッド上に配置された、アルミニウムからなる金属層と、金属層の上部に形成された、銅とアルミニウムの合金層と、合金層に接続された、銅を主成分とするボンディングワイヤとを備える半導体装置が提供される。   According to another aspect of the present invention, a semiconductor element, an electrode pad disposed on the semiconductor element and made of a metal harder than aluminum, a metal layer made of aluminum and disposed on the electrode pad, and a metal layer There is provided a semiconductor device including an alloy layer of copper and aluminum formed on an upper portion of the substrate and a bonding wire mainly composed of copper connected to the alloy layer.

本発明の更に他の態様によれば、アルミニウムよりも硬い金属からなる電極パッドが表面に配置された半導体素子を準備するステップと、電極パッド上にアルミニウム膜からなる金属層を形成するステップと、金属層に銅を主成分とするボンディングワイヤを接合するステップとを含む半導体装置の製造方法が提供される。   According to still another aspect of the present invention, preparing a semiconductor element having an electrode pad made of a metal harder than aluminum disposed on the surface, forming a metal layer made of an aluminum film on the electrode pad, There is provided a method of manufacturing a semiconductor device including a step of bonding a bonding wire containing copper as a main component to a metal layer.

本発明によれば、Cuワイヤーによるボンディング時に電極パッド下の半導体素子に損傷が生じない半導体装置及び半導体装置の製造方法を提供できる。   ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which does not damage a semiconductor element under an electrode pad at the time of bonding by Cu wire, and the manufacturing method of a semiconductor device can be provided.

本発明の実施形態に係る半導体装置の構造を示す模式図である。It is a mimetic diagram showing the structure of the semiconductor device concerning the embodiment of the present invention. 本発明の実施形態に係る半導体装置のボンディング後の構造を示す模式図である。It is a mimetic diagram showing structure after bonding of a semiconductor device concerning an embodiment of the present invention.

次に、図面を参照して、本発明の実施形態を説明する。以下の図面の記載において、同一又は類似の部分には同一又は類似の符号を付している。ただし、図面は模式的なものであり、各部の厚みの比率等は現実のものとは異なることに留意すべきである。したがって、具体的な厚みや寸法は以下の説明を参酌して判断すべきものである。又、図面相互間においても互いの寸法の関係や比率が異なる部分が含まれていることはもちろんである。   Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic and ratios of thicknesses of the respective parts are different from actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

又、以下に示す実施形態は、この発明の技術的思想を具体化するための装置や方法を例示するものであって、この発明の実施形態は、構成部品の材質、形状、構造、配置等を下記のものに特定するものでない。この発明の実施形態は、特許請求の範囲において、種々の変更を加えることができる。   Further, the embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the embodiments of the present invention include the material, shape, structure, arrangement, etc. of the component parts. Is not specified as follows. The embodiment of the present invention can be variously modified within the scope of the claims.

本発明の実施形態に係る半導体装置1は、Cuを主成分とするボンディングワイヤによる電気的接続が可能な半導体装置である。半導体装置1は、図1に示すように、半導体素子10と、半導体素子10上に配置された、Alよりも硬い金属からなる電極パッド20と、電極パッド20上に配置された、ボンディングワイヤが接続されるAl膜からなる金属層30とを備える。   A semiconductor device 1 according to an embodiment of the present invention is a semiconductor device that can be electrically connected by a bonding wire containing Cu as a main component. As shown in FIG. 1, the semiconductor device 1 includes a semiconductor element 10, an electrode pad 20 made of a metal harder than Al, disposed on the semiconductor element 10, and a bonding wire disposed on the electrode pad 20. And a metal layer 30 made of an Al film to be connected.

半導体素子10は、半導体基板上に各種の半導体層や絶縁膜を積層した積層体11からなり、図示を省略する電極や配線層を有する。積層体11の上面には、絶縁膜12が配置されている。電極パッド20は、絶縁膜12に設けられた開口部(図示略)において、半導体素子10の電極や配線層と電気的に接続している。絶縁膜12は、例えば酸化シリコン(SiO2)膜、窒化シリコン(SiN)膜、ポリミド膜などである。 The semiconductor element 10 includes a stacked body 11 in which various semiconductor layers and insulating films are stacked on a semiconductor substrate, and includes an electrode and a wiring layer (not shown). An insulating film 12 is disposed on the upper surface of the stacked body 11. The electrode pad 20 is electrically connected to an electrode and a wiring layer of the semiconductor element 10 in an opening (not shown) provided in the insulating film 12. The insulating film 12 is, for example, a silicon oxide (SiO 2 ) film, a silicon nitride (SiN) film, a polyimide film, or the like.

電極パッド20は、例えば、Alを主成分とし且つCuを含有する金属からなる。このとき、電極パッド20における銅の含有率は、例えば0.3〜5.0重量%程度である。電極パッド20の膜厚は、例えば1μm〜2μm程度である。   The electrode pad 20 is made of, for example, a metal containing Al as a main component and Cu. At this time, the copper content in the electrode pad 20 is, for example, about 0.3 to 5.0% by weight. The film thickness of the electrode pad 20 is, for example, about 1 μm to 2 μm.

金属層30は、99.99重量%以上のAl膜である。金属層30の膜厚は、1μm〜5μm程度、好ましくは3μm〜5μm程度である。金属層30の膜厚が3μm以上であれば、通常、金属層30にCuワイヤをボンディングした後も電極パッド20上に金属層30が残った状態になる。   The metal layer 30 is an Al film of 99.99% by weight or more. The film thickness of the metal layer 30 is about 1 μm to 5 μm, preferably about 3 μm to 5 μm. If the film thickness of the metal layer 30 is 3 μm or more, the metal layer 30 usually remains on the electrode pad 20 even after the Cu wire is bonded to the metal layer 30.

図1に示した半導体装置1にボンディングワイヤ40を接合した例を、図2に示す。ボンディングワイヤ40は、Cuを主成分とするCuワイヤである。   An example in which the bonding wire 40 is bonded to the semiconductor device 1 shown in FIG. 1 is shown in FIG. The bonding wire 40 is a Cu wire containing Cu as a main component.

ボンディングワイヤ40は、例えば超音波ボンディングによって金属層30に接合される。超音波によってボンディングワイヤ40と金属層30の表面が擦り合わされて、新生面がそれぞれ生成される。これらの新生面同士が密着することによって異種金属間の凝着が進行し、ボンディングワイヤ40と金属層30が接合される。このとき、金属層30の上部のAlがボンディングワイヤ40のCuと反応して、AlとCuの合金層35が形成される。   The bonding wire 40 is bonded to the metal layer 30 by, for example, ultrasonic bonding. The surfaces of the bonding wire 40 and the metal layer 30 are rubbed with each other by ultrasonic waves, and new surfaces are generated. When these new surfaces are brought into close contact with each other, adhesion between dissimilar metals proceeds, and the bonding wire 40 and the metal layer 30 are joined. At this time, Al on the upper part of the metal layer 30 reacts with Cu of the bonding wire 40 to form an alloy layer 35 of Al and Cu.

その結果、図2に示すように、ボンディングワイヤ40が接合された半導体装置1は、半導体素子10、電極パッド20、Al膜からなる金属層30、及びAlとCuの合金層35が積層された構造である。合金層35にボンディングワイヤ40が接続されている。   As a result, as shown in FIG. 2, the semiconductor device 1 to which the bonding wire 40 is bonded has the semiconductor element 10, the electrode pad 20, the metal layer 30 made of an Al film, and the alloy layer 35 of Al and Cu laminated. Structure. A bonding wire 40 is connected to the alloy layer 35.

ボンディングワイヤ40は、電極パッド20と半導体装置1のインナーリードとを電気的に接続するワイヤとしても、電極パッド20と半導体装置1を搭載するプリント基板上の配線パターンとを電気的に接続するワイヤとしても使用される。   The bonding wire 40 is a wire that electrically connects the electrode pad 20 and the inner lead of the semiconductor device 1 or a wire that electrically connects the electrode pad 20 and the wiring pattern on the printed circuit board on which the semiconductor device 1 is mounted. Also used as

半導体装置1では、電極パッド20上に金属層30を配置することにより、電極パッド20の表面が露出しない。このため、電極パッド20表面のCuの酸化を防止できる。   In the semiconductor device 1, the surface of the electrode pad 20 is not exposed by disposing the metal layer 30 on the electrode pad 20. For this reason, oxidation of Cu on the surface of the electrode pad 20 can be prevented.

Cuワイヤであるボンディングワイヤ40は硬いため、ボンディングワイヤ40を電極パッド20に接合するときに、電極パッド20下の半導体素子10に損傷を与えるおそれがある。   Since the bonding wire 40 which is a Cu wire is hard, there is a possibility that the semiconductor element 10 under the electrode pad 20 may be damaged when the bonding wire 40 is bonded to the electrode pad 20.

しかし、半導体装置1では、電極パッド20上に配置された金属層30が電極パッド20よりも柔らかい。このため、金属層30によってボンディング時の衝撃が緩衝され、ボンディング時における電極パッド20下方の絶縁膜12の損傷を抑制できる。   However, in the semiconductor device 1, the metal layer 30 disposed on the electrode pad 20 is softer than the electrode pad 20. For this reason, the impact at the time of bonding is buffered by the metal layer 30, and damage to the insulating film 12 below the electrode pad 20 at the time of bonding can be suppressed.

また、電極パッド20のCu含有率が高いと、ダイス工程時に水と反応して電極パッド20にピンホールが発生するコロージョンによって接合面積が減少し、ワイヤーボンディングの接合強度が低下する問題がある。しかし、半導体装置1では、電極パッド20上に金属層30が配置されているため、電極パッド20表面でのピンホール発生が防止される。このため、接合強度を高く維持できる。   In addition, when the Cu content of the electrode pad 20 is high, there is a problem that the bonding area is reduced due to the corrosion that reacts with water during the dicing process and pinholes are generated in the electrode pad 20, and the bonding strength of wire bonding is reduced. However, in the semiconductor device 1, since the metal layer 30 is disposed on the electrode pad 20, generation of pin holes on the surface of the electrode pad 20 is prevented. For this reason, the bonding strength can be maintained high.

したがって、半導体装置1では、電極パッド20上にAl膜からなる金属層30を配置することにより、電極パッド20にCuワイヤを直接接合する場合と比べて、ワイヤーボンディング条件を緩和することができる。例えば、ボンディング時の加重を大きくし、超音波のエネルギーを小さくできる。これにより、半導体素子10の受けるダメージを小さくできる。   Therefore, in the semiconductor device 1, by arranging the metal layer 30 made of the Al film on the electrode pad 20, the wire bonding conditions can be relaxed compared to the case where the Cu wire is directly bonded to the electrode pad 20. For example, it is possible to increase the weight during bonding and reduce the energy of ultrasonic waves. Thereby, the damage which the semiconductor element 10 receives can be made small.

上記のようにワイヤーボンディング条件を緩和することができるため、半導体装置1の製造が容易になる。   Since the wire bonding conditions can be relaxed as described above, the semiconductor device 1 can be easily manufactured.

以上に説明したように、本発明の実施形態に係る半導体装置1では、Alよりも硬い金属からなる電極パッド20上にAl膜からなる金属層30が配置され、金属層30にCuワイヤであるボンディングワイヤ40が接合される。金属層30によってボンディング時の衝撃が緩衝されるため、半導体装置1によれば、ボンディング時に電極パッド20下方の半導体素子10に損傷が生じない半導体装置を提供することができる。   As described above, in the semiconductor device 1 according to the embodiment of the present invention, the metal layer 30 made of an Al film is disposed on the electrode pad 20 made of a metal harder than Al, and the metal layer 30 is a Cu wire. Bonding wire 40 is joined. Since the impact during bonding is buffered by the metal layer 30, the semiconductor device 1 can provide a semiconductor device in which the semiconductor element 10 below the electrode pad 20 is not damaged during bonding.

(その他の実施形態)
上記のように本発明は実施形態によって記載したが、この開示の一部をなす論述及び図面はこの発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施形態、実施例及び運用技術が明らかとなろう。
(Other embodiments)
As described above, the present invention has been described according to the embodiments. However, it should not be understood that the descriptions and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

既に述べた実施形態の説明においては、電極パッド20の材料がAlとCuである場合を例示的に説明したが、Alを主成分とし且つCuを含有するのであれば、電極パッド20の材料はこれに限られない。例えば、Alを主成分とし、Cuの含有率が0.3〜5.0重量%であり、且つシリコン(Si)を含有させた電極パッド20であってもよい。   In the description of the embodiment already described, the case where the material of the electrode pad 20 is Al and Cu has been described as an example. However, if the material is mainly composed of Al and contains Cu, the material of the electrode pad 20 is It is not limited to this. For example, the electrode pad 20 which has Al as a main component, Cu content of 0.3 to 5.0 wt%, and silicon (Si) may be used.

また、本発明の実施形態は、半導体素子(半導体素子の電極パッドと半導体素子の金属層を含む)とワイヤを樹脂で覆った樹脂封止型半導体装置として適応することができる。例えば、樹脂はエポキシ樹脂、ハロゲンフリー樹脂を使用することができる。   The embodiment of the present invention can be applied as a resin-encapsulated semiconductor device in which a semiconductor element (including an electrode pad of a semiconductor element and a metal layer of the semiconductor element) and a wire are covered with a resin. For example, an epoxy resin or a halogen-free resin can be used as the resin.

また、ボンディングワイヤ40に、酸化防止のために金属めっきを被覆したワイヤも採用可能である。例えば、ボンディングワイヤ40にパラジウム(Pd)めっきCuワイヤを使用することができる。   Moreover, the wire which coat | covered the metal plating for the oxidation prevention to the bonding wire 40 is also employable. For example, palladium (Pd) plated Cu wire can be used for the bonding wire 40.

このように、本発明はここでは記載していない様々な実施形態等を含むことは勿論である。したがって、本発明の技術的範囲は上記の説明から妥当な特許請求の範囲に係る発明特定事項によってのみ定められるものである。   As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

1…半導体装置
10…半導体素子
11…積層体
12…絶縁膜
20…電極パッド
30…金属層
35…合金層
40…ボンディングワイヤ
DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 10 ... Semiconductor element 11 ... Laminated body 12 ... Insulating film 20 ... Electrode pad 30 ... Metal layer 35 ... Alloy layer 40 ... Bonding wire

Claims (7)

銅を主成分とするボンディングワイヤによる電気的接続が可能な半導体装置であって、
半導体素子と、
前記半導体素子上に配置された、アルミニウムよりも硬い金属からなる電極パッドと、
前記電極パッド上に配置された、前記ボンディングワイヤが接続されるアルミニウム膜からなる金属層と
を備えることを特徴とする半導体装置。
A semiconductor device capable of electrical connection by a bonding wire mainly composed of copper,
A semiconductor element;
An electrode pad made of a metal harder than aluminum, disposed on the semiconductor element;
And a metal layer made of an aluminum film disposed on the electrode pad and connected to the bonding wire.
半導体素子と、
前記半導体素子上に配置され、アルミニウムよりも硬い金属からなる電極パッドと、
前記電極パッド上に配置された、アルミニウムからなる金属層と、
前記金属層の上部に形成された、銅とアルミニウムの合金層と、
前記合金層に接続された、銅を主成分とするボンディングワイヤと
を備えることを特徴とする半導体装置。
A semiconductor element;
An electrode pad disposed on the semiconductor element and made of a metal harder than aluminum;
A metal layer made of aluminum and disposed on the electrode pad;
An alloy layer of copper and aluminum formed on the metal layer;
A semiconductor device comprising: a bonding wire mainly composed of copper connected to the alloy layer.
前記電極パッドが、アルミニウムを主成分とし且つ銅を含有することを特徴とする請求項1又は2に記載の半導体装置。   The semiconductor device according to claim 1, wherein the electrode pad contains aluminum as a main component and copper. 前記電極パッドにおける銅の含有率が0.3〜5.0重量%であることを特徴とする請求項3に記載の半導体装置。   4. The semiconductor device according to claim 3, wherein the copper content in the electrode pad is 0.3 to 5.0% by weight. アルミニウムよりも硬い金属からなる電極パッドが表面に配置された半導体素子を準備するステップと、
前記電極パッド上にアルミニウム膜からなる金属層を形成するステップと、
前記金属層に銅を主成分とするボンディングワイヤを接合するステップと
を含むことを特徴とする半導体装置の製造方法。
Preparing a semiconductor element having an electrode pad made of a metal harder than aluminum disposed on the surface;
Forming a metal layer made of an aluminum film on the electrode pad;
Bonding a bonding wire containing copper as a main component to the metal layer. A method for manufacturing a semiconductor device, comprising:
前記金属層の上部のアルミニウムと前記ボンディングワイヤに含まれる銅とを反応させて、銅とアルミニウムの合金層を形成することを特徴とする請求項5に記載の半導体装置の製造方法。   6. The method of manufacturing a semiconductor device according to claim 5, wherein an aluminum layer above the metal layer is reacted with copper contained in the bonding wire to form an alloy layer of copper and aluminum. 超音波ボンディングによって前記金属層に前記ボンディングワイヤを接合することを特徴とする請求項5又は6に記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 5, wherein the bonding wire is bonded to the metal layer by ultrasonic bonding.
JP2011135111A 2011-06-17 2011-06-17 Semiconductor device and semiconductor device manufacturing method Pending JP2013004779A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2011135111A JP2013004779A (en) 2011-06-17 2011-06-17 Semiconductor device and semiconductor device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011135111A JP2013004779A (en) 2011-06-17 2011-06-17 Semiconductor device and semiconductor device manufacturing method

Publications (1)

Publication Number Publication Date
JP2013004779A true JP2013004779A (en) 2013-01-07

Family

ID=47673012

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011135111A Pending JP2013004779A (en) 2011-06-17 2011-06-17 Semiconductor device and semiconductor device manufacturing method

Country Status (1)

Country Link
JP (1) JP2013004779A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014157868A (en) * 2013-02-14 2014-08-28 New Japan Radio Co Ltd Method of manufacturing semiconductor device by using bonding tool
WO2015170738A1 (en) * 2014-05-08 2015-11-12 ローム株式会社 Method for manufacturing wire bonding structure, wire bonding structure, and electronic device
JP2020113721A (en) * 2019-01-16 2020-07-27 富士電機株式会社 Semiconductor device and method for manufacturing semiconductor device
US11545460B2 (en) 2020-01-10 2023-01-03 Fuji Electric Co., Ltd. Semiconductor device and method for manufacturing semiconductor device having first and second wires in different diameter

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009177104A (en) * 2007-02-20 2009-08-06 Nec Electronics Corp Semiconductor device
JP2010258286A (en) * 2009-04-27 2010-11-11 Sanyo Electric Co Ltd Semiconductor device and method of manufacturing the same
JP2011018832A (en) * 2009-07-10 2011-01-27 Sanyo Electric Co Ltd Semiconductor device, and method of manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009177104A (en) * 2007-02-20 2009-08-06 Nec Electronics Corp Semiconductor device
JP2010258286A (en) * 2009-04-27 2010-11-11 Sanyo Electric Co Ltd Semiconductor device and method of manufacturing the same
JP2011018832A (en) * 2009-07-10 2011-01-27 Sanyo Electric Co Ltd Semiconductor device, and method of manufacturing the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014157868A (en) * 2013-02-14 2014-08-28 New Japan Radio Co Ltd Method of manufacturing semiconductor device by using bonding tool
WO2015170738A1 (en) * 2014-05-08 2015-11-12 ローム株式会社 Method for manufacturing wire bonding structure, wire bonding structure, and electronic device
JPWO2015170738A1 (en) * 2014-05-08 2017-04-20 ローム株式会社 Wire bonding structure manufacturing method, wire bonding structure, and electronic device
US10115699B2 (en) 2014-05-08 2018-10-30 Rohm Co., Ltd. Method for manufacturing wire bonding structure, wire bonding structure, and electronic device
JP2020113721A (en) * 2019-01-16 2020-07-27 富士電機株式会社 Semiconductor device and method for manufacturing semiconductor device
JP7383881B2 (en) 2019-01-16 2023-11-21 富士電機株式会社 Semiconductor device and semiconductor device manufacturing method
US11545460B2 (en) 2020-01-10 2023-01-03 Fuji Electric Co., Ltd. Semiconductor device and method for manufacturing semiconductor device having first and second wires in different diameter

Similar Documents

Publication Publication Date Title
JP2013004781A (en) Semiconductor device and semiconductor device manufacturing method
US8227341B2 (en) Semiconductor device and method of manufacturing the same
JP4379413B2 (en) Electronic component, method for manufacturing electronic component, circuit board, and electronic device
WO2019087920A1 (en) Power semiconductor device and manufacturing method for power semiconductor device
JP2010212645A (en) Connection structure, power module and method of manufacturing the same
JP2014056917A (en) Power semiconductor device and power semiconductor device manufacturing method
JP2013004779A (en) Semiconductor device and semiconductor device manufacturing method
JP5893266B2 (en) Semiconductor device and manufacturing method thereof
JP4247167B2 (en) Package structure
KR101951957B1 (en) Semiconductor device and production method thereof
US20100181675A1 (en) Semiconductor package with wedge bonded chip
JP5988489B2 (en) Semiconductor device and manufacturing method thereof
JP2005051084A (en) Semiconductor chip and semiconductor device using this
JP6397313B2 (en) Printed wiring board and semiconductor package
JP6354467B2 (en) Semiconductor device
JP2011193007A (en) Semiconductor chip and semiconductor device using the same
US9324675B2 (en) Structures for reducing corrosion in wire bonds
KR200483254Y1 (en) Semiconductor package
JP2010092974A (en) Semiconductor device and method of manufacturing the same, and electronic device
JP2020031081A (en) Semiconductor device
JP2010157544A (en) Semiconductor device, method of manufacturing the same, and electronic apparatus
JP2008010778A (en) Semiconductor device
JP2018125354A (en) Semiconductor device
WO2010143369A1 (en) Semiconductor device and fabricating method therefor
JP2015037151A (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20140520

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20150224

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20150630