WO2010143369A1 - Semiconductor device and fabricating method therefor - Google Patents

Semiconductor device and fabricating method therefor Download PDF

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Publication number
WO2010143369A1
WO2010143369A1 PCT/JP2010/003580 JP2010003580W WO2010143369A1 WO 2010143369 A1 WO2010143369 A1 WO 2010143369A1 JP 2010003580 W JP2010003580 W JP 2010003580W WO 2010143369 A1 WO2010143369 A1 WO 2010143369A1
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Prior art keywords
bump
semiconductor element
element substrate
film
semiconductor device
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PCT/JP2010/003580
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French (fr)
Japanese (ja)
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山口欣秀
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株式会社日立製作所
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Publication of WO2010143369A1 publication Critical patent/WO2010143369A1/en

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    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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Definitions

  • the present invention relates to a semiconductor device in which semiconductor elements of at least two stages or more are stacked and a manufacturing method thereof, and relates to a bump electrode structure of the semiconductor device and a bump electrode bonding method.
  • the second semiconductor element is stacked on top of the first semiconductor element to construct a so-called three-dimensional structure to realize the shortest connection between the semiconductor elements, thereby trying to maximize the performance of each semiconductor element. Attempts to do so have been proposed.
  • Patent Document 1 in order to connect two upper and lower semiconductor chips at the shortest distance, an interposer chip provided with a through hole is disposed between the upper and lower semiconductor chips, A structure has been proposed in which a protruding electrode provided on the surface of a semiconductor chip is pressed into a through hole.
  • a plurality of semiconductor chips are three-dimensionally stacked to achieve connection with the shortest wiring length.
  • the convex external connection terminal provided on the semiconductor chip arranged on the upper side is pressed and injected into the concave external connection terminal provided on the semiconductor chip arranged on the lower side.
  • a technique of compositionally flowing the metal of the external connection terminal is employed.
  • the vibration width of the bonding tool is required to be a minimum of about plus or minus 10 micrometers.
  • the amplitude width of the bonding tool is less than plus or minus 10 micrometers, the amount of plastic deformation of the metal bumps is reduced, and as a result, the amount of composition flow is also reduced, so that a sufficient connection cross-sectional area is obtained at the contact portion between the external connection terminals. This is because it is difficult to ensure the above.
  • the position displacement of the metal bumps is generated by about 10 micrometers, and such bump displacement reduces the position accuracy of the bonding.
  • Patent Document 1 since a through hole is provided in a chip, a large pressing load is applied to a semiconductor chip having a hole (usually made of a brittle material such as silicon). It cannot be denied that there is a risk that the chip will brittlely break. In addition, it is not preferable to apply an excessive pressing load in a brittle material processing step even for a semiconductor chip having no holes.
  • compound semiconductors other than silicon for example, semiconductor chips with low brittle fracture resistance such as SiC and GaN, needless to say, it is highly necessary to avoid an excessive pressing load from the viewpoint of suppressing brittle fracture of the chip.
  • the above Patent Document 1 uses a ball bonding method using Au wires (see Paragraph 0034 of the above Patent Document 1).
  • the tip of the Au wire is melted to form the Au ball part, and then the ultrasonic wave is applied by pressing the ball part against the desired electrode pad location on the chip surface.
  • the bumps are made by a series of processes of thermocompression bonding and cutting the ball tip from the Au wire.
  • Small-sized Au wires for example, small-diameter Au wires having a diameter of 20 micrometers or less, are difficult to handle and are therefore less expensive and therefore expensive.
  • the plating bump method is known as a method for arranging a large number of Au bumps at a full grid and a narrow pitch.
  • Au bumps often have poor adhesion to the underfill material, and as a result, there is a tendency for gaps to form at the interface between the underfill and Au bumps, leading to a decrease in insulation reliability.
  • Patent Document 1 is not necessarily advantageous for application to a three-dimensional stack of semiconductor chips having a large number of bumps.
  • the inventor of the present application has been able to obtain a good result by adopting the following structure, configuration, and means as a result of searching for a technique for improving the technique described in the above publication, and has reached the present invention.
  • one structure / configuration of a semiconductor device is as follows.
  • a convex metallic conductor bump formed on the surface of the first semiconductor element substrate and a convex metallic conductor bump formed on the surface of the second semiconductor element substrate are bonded to each other.
  • the tip of the first convex metallic conductor bump formed on the surface of the first semiconductor element substrate is sharpened in advance.
  • the second convex metallic conductor bump formed on the surface of the second semiconductor element substrate has a composite structure composed of at least three kinds of materials, that is, a top portion, a side wall portion, and a main body portion, and the main body portion is flexible. Metal.
  • the tip portion of the first convex metallic conductor bump having a sharp tip is press-fitted into the soft metal layer that is the main body portion of the second convex metallic conductor bump.
  • the first surface of the semiconductor element substrate has a first bump with a sharp tip
  • the second surface is made of at least three kinds of materials including a top portion, a side wall portion, and a main body portion made of a soft metal.
  • a semiconductor element substrate having a second bump having a composite structure is used.
  • At least three semiconductor element substrates with double-sided bumps having such a structure are prepared, the 1-1st bump having a sharp tip formed in advance on the first surface of the first semiconductor element substrate, A tip formed beforehand on the first surface of the second semiconductor element substrate is bonded to the second surface of the second semiconductor element substrate bonded to the second bump 2-2 containing a soft metal formed in advance.
  • the structure is such that the 2-1 bumps with sharp edges and the 3-2 bumps containing a soft metal formed in advance on the second surface of the third semiconductor element substrate are joined.
  • the present invention also provides a method for manufacturing the semiconductor device according to the present invention.
  • the manufacturing method of the semiconductor device provided by the present invention is as follows.
  • a first metal conductor layer having a uniform thickness is formed on the surface of the first semiconductor element substrate, and a desired portion of the first uniform thickness metal conductor film is selectively processed and removed by a wet etching method.
  • a first semiconductor element substrate with bumps is produced.
  • a method such as photolithography is desirable.
  • a second semiconductor element substrate is prepared separately from the first semiconductor element substrate, and a second metal conductor layer film is formed on the surface with a uniform film thickness.
  • a conductor layer film (third conductor layer, fourth conductor layer) made of various types of conductors, it is selectively removed leaving a desired portion of the second to fourth metal conductor layer films.
  • the method of forming the third conductor layer and the fourth conductor layer may be an etching method or a plating method.
  • the second and second plating layers are formed after the third and fourth conductor layers are continuously formed only at the locations where the plating is selectively deposited using photolithography technology. By removing unnecessary portions of the conductor layer film, desired portions of the second to fourth metal conductor layer films can be left.
  • the first bumped semiconductor element substrate and the second bumped semiconductor element substrate are arranged so that their relative positions are up and down, and the first bumped semiconductor element substrate The bump position of the substrate is matched with the bump position of the second bumped semiconductor element substrate.
  • the first bumped semiconductor element is so pressed that the bump provided on the first bumped semiconductor element substrate is pressed into the bump provided on the second bumped semiconductor element substrate.
  • the substrate and the second bumped semiconductor element substrate are moved relative to each other.
  • the present invention provides a manufacturing method for realizing a chip laminated structure in which at least two semiconductor chips are laminated and joined.
  • thermocompression bonding where multiple semiconductor chips stacked in three dimensions are connected with the shortest wiring length, a bump with a sharp tip is pressed into a soft metal bump. Reliable joining is possible.
  • FIG. 6 is a schematic diagram for explaining a cross-sectional structure in one form of the partial process in the method for manufacturing a semiconductor device according to the example of the present invention.
  • FIG. 10 is a schematic view for explaining a cross-sectional structure in one form of another partial process in the method for manufacturing a semiconductor device according to the example of the present invention.
  • FIG. 10 is a schematic view for explaining a cross-sectional structure in one form of still another partial process in the method for manufacturing a semiconductor device according to the example of the present invention. It is the schematic which shows the cross section of another 1 form of the semiconductor device concerning the Example of this invention.
  • FIG. 1 shows a schematic cross-sectional structure of the semiconductor device of this embodiment.
  • a plurality of convex metal conductor bumps 2 are formed on the surface of the first semiconductor element substrate 1, and a plurality of convex metal conductor bumps 4 are formed on the surface of the second semiconductor element substrate 3. Is formed.
  • the first semiconductor element substrate 1 and the second semiconductor element substrate 3 are arranged with their surfaces facing each other, and the convex metallic conductor bumps 2 provided on the first semiconductor element substrate 1 are second.
  • the convex metallic conductor bumps 4 provided on the semiconductor element substrate 3 are press-fitted to electrically connect the convex metallic conductor bumps 2 and 4 to each other.
  • the gap portion between the first semiconductor element substrate 1 and the second semiconductor element substrate 3 is filled with an underfill material 5 so as to fill the gap between the metallic conductor bumps.
  • the second semiconductor element substrate 3 is fixed so as not to be separated.
  • the underfill material 5 not only fixes the semiconductor element substrate 1 and the second semiconductor element substrate 3, but also ensures insulation reliability between the metallic conductor bumps, and the stress of the underfill material 5 itself. Distributing action contributes to securing connection reliability.
  • the metallic conductor bump 4 provided on the second semiconductor element substrate 3 uses a composite structure made of at least three kinds of materials.
  • a composite structure made of four kinds of materials that is, a height matching layer 4a, a soft metal layer 4b, a top layer 4c, and a side wall portion 4d was used.
  • the height matching layer 4a employed in the present embodiment is a layer for controlling the press-fitting depth when the convex metallic conductor bump 2 is press-fitted into the convex metallic conductor bump 4.
  • the gap between the semiconductor element substrate 1 and the semiconductor element substrate 3 is precisely controlled so as to have a desired value.
  • the numerical variation range can also be controlled. More specifically, the variation range of the gap value between the semiconductor element substrate 1 and the semiconductor element substrate 3 is substantially the same as the thickness variation range of the height matching layer 4a. It is relatively easy to manufacture the thickness variation of the height matching layer 4a so that the average thickness of the height matching layer 4a is equal to or less than 10%.
  • Control of the variation range of the gap value between the substrate 1 and the semiconductor element substrate 3 to plus or minus 10% or less is easily realized.
  • the details of the manufacturing method of the height matching layer 4a will be described later, but if the manufacturing method of the height matching layer 4a is devised, the variation range of the gap value can be further suppressed. More specifically, when the average thickness of the height matching layer 4a is 5 micrometers, the variation range of the gap value between the semiconductor element substrate 1 and the semiconductor element substrate 3 is plus or minus 0.5 micrometers. Control is performed as follows.
  • the height matching layer 4a as described above, precise control of the gap between the semiconductor element substrates is realized, and as a result, the occurrence of defects in the filling process of the underfill material 5 has been successfully reduced. .
  • This is considered to be because the underfill filling conditions that are optimum for the desired gap value can be selected because the gap between the semiconductor element substrates can be precisely controlled.
  • the gap between semiconductor element substrates is one of the main factors of flow path resistance in the filling process of the underfill 5.
  • the height matching layer 4a for precisely controlling the gap between the semiconductor element substrates as in this embodiment.
  • the height matching layer 4a is not provided, the flow resistance in the filling process of the underfill 5 is reduced unless another control method or manufacturing method for stabilizing the value of the gap between the semiconductor element substrates is employed. There is an increased risk of underfill filling problems due to instability.
  • the soft metal layer 4 b is a main body portion of the metal conductor bump 4, and the metal conductor bump 2 is press-fitted to form a bonding interface with the metal conductor bump 2.
  • the metal conductor bump 2 is press-fitted to form a bonding interface with the metal conductor bump 2.
  • a wide variety of materials are known as easily deformable conductors, but the present inventors prefer a metal material or an alloy material rather than a conductive resin from the viewpoint of forming a reliable bonding interface with the metallic conductor bump 2. It was judged.
  • the applicability to the technology of the present invention was examined, and a metallic material having a Brunel hardness of 100 MPa or less is desirable, and a guideline is obtained that the Brunel hardness is particularly preferably less than 50 MPa. It was. On the other hand, if the Brunner hardness is 50 MPa or more, the load required in the process of press-fitting the metallic conductor bump 2 becomes large, which may affect the operating characteristics of the semiconductor element.
  • Sn does not fall within the category of the most preferable conductor metal as the soft metal layer 4b of the present invention because the Brunel hardness is 51 MPa.
  • a bump top layer 4 c is provided on the top of the bump of the metal conductor bump 4, and serves as a film that prevents oxidation of the top of the metal conductor bump 4. Since the bump top layer 4c needs to be broken when the convex metallic conductor bump 2 is press-fitted into the convex metallic conductor bump 4, it is desirable that the bump top layer 4c be a film that can be easily broken. As a result of studying the applicability of the present invention to some materials that can be easily broken, the inventor of the present application press-fits the convex metallic conductor bump 2 if the film has a shear strength of 50 GPa or less.
  • the guideline was obtained that it is difficult to cause an obstacle when the shear strength is 30 GPa or less and the film thickness is 1.0 micrometer or less.
  • a metal thin film is desirable for the bump top layer 4c of the present invention.
  • the thickness is limited to 1.0 ⁇ m or less at the maximum.
  • the bump top layer 4c was fabricated in a thickness range of 0.05 to 0.40 micrometers. This is because if the thickness of the bump top layer 4c is less than 0.05 micrometers, there is a tendency that the effect of preventing the oxidation of the metallic conductor bump 4 cannot be sufficiently obtained. If the bump top layer 4c produced with a film thickness in the range of 0.05 to 0.40 micrometers is used, there will be no particular problem with the rupture when the convex metallic conductor bumps 2 are press-fitted. Further, if the bump top layer 4c is thick, a fractured fragment that becomes a remnant of the bump top layer 4c may be generated near the interface between the metal conductor bump 2 and the metal conductor bump 4.
  • the film thickness is limited in the range of 0.05 to 0.40 micrometers, the generation of breakage fragments that become debris is negligible.
  • a slightly broken piece reacts with In employed as the soft metal layer 4b to form an In—Ag eutectic (eutectic temperature of 141 ° C.) and diffuses into the soft metal layer 4b, so that the bump top layer
  • In—Ag eutectic eutectic temperature of 141 ° C.
  • the bump top layer 4c having an appropriate film thickness (0.05 to 0.40 micrometer)
  • the fragments are the height of the conductor of the bump 2 and the inside of the conductor bump 4.
  • the metal conductor bump 4 further has a side wall portion 4d formed on the side wall portion thereof.
  • the side wall portion 4 d is a layer for ensuring adhesion with the underfill material 5, and may have a minimum thickness that can maintain adhesion with the underfill material 5. Therefore, depending on the material of the metal layer 4b, a natural oxide film that spontaneously forms on the side wall of the soft metal layer 4b may be used instead of actively forming a film.
  • the sidewall portion 4d is an indium oxide film generated by natural oxidation of In used for the soft metal layer 4b. The indium oxide film is quickly formed on the surface of In in the air to form a thin and strong film, and has the effect of chemically stabilizing In.
  • the natural oxide film of In naturally generated as described above as the side wall portion 4d.
  • an Ag thin film that is less ionized than In used in the soft metal layer 4b that is the main body portion of the bump 4 is formed on the bump top layer 4c. The structure facilitates the formation of a natural oxide film of In.
  • the convex metal conductor bumps 2 are press-fitted into the metal conductor bumps 4 made of four kinds of materials, that is, the height matching layer 4a, the soft metal layer 4b, the top layer 4c, and the side wall 4d shown in FIG.
  • An example of a schematic cross-sectional structure in which the state is enlarged is shown in FIG.
  • the convex metallic conductor bumps 2 do not penetrate deeper than they hit the top of the height matching layer 4a.
  • the thickness of the height matching layer 4a is about 50% with respect to the metallic conductor bump 4
  • the thickness of the soft metal layer 4b is about 48% with respect to the entire thickness of the metallic conductor bump 4, and the top layer 4c.
  • the thickness of the convex metallic conductor bump 2 is slightly thicker than that of the soft metal layer 4b, and is about 50% of the thickness of the metallic conductor bump 4 in this embodiment.
  • the thickness of the convex metallic conductor bump 2 should be equal to or greater than the thickness of the soft metal layer 4b, and be in the range of 10 to 95% with respect to the total thickness of the metallic conductor bump 4. Is desirable.
  • the soft metal layer 4b must be thinned as a result. There is a growing concern that the bonding interface between the shape metallic conductor bump 2 and the metallic conductor bump 4 becomes small and the bonding reliability is insufficient. On the contrary, when the thickness of the convex metallic conductor bump 2 exceeds 95% with respect to the entire thickness of the metallic conductor bump 4, the ratio of the soft metal layer 4 b to the entire metallic conductor bump 4 inevitably. Is increased, in other words, the proportion of the height matching layer 4a is decreased, and therefore, the tendency for the gap controllability between the semiconductor element substrate 1 and the semiconductor element substrate 3 to decrease is increased.
  • the convex metallic conductor bump 2 As illustrated in FIG. 3, the convex metallic conductor bump 2 has a pointed tip, and the tip on the small diameter side is a top layer 4 c formed on the surface of the convex metallic conductor bump 4. It penetrates, is press-fitted into the soft metal layer 4b, and is joined in a state of abutting against the height matching layer 4a. On the other hand, the tip on the large-diameter side of the convex metallic conductor bump 2 is connected to the surface of the first semiconductor element substrate, which is omitted in FIG.
  • the tip diameter on the large diameter side of the convex metallic conductor bump 2 is desirable to make the tip diameter on the large diameter side of the convex metallic conductor bump 2 larger than the thickness (height) of the convex metallic conductor bump 2. More specifically, the tip diameter on the large diameter side of the convex metallic conductor bump 2 is desirably about 200% or more with respect to the thickness (height) of the convex metallic conductor bump 2. . This is because, by setting such a diameter / thickness ratio, a simple manufacturing process can be adopted, and the cost can be reduced. In this embodiment, the tip diameter on the large diameter side of the convex metallic conductor bump 2 is 10 micrometers, and the thickness (height) of the convex metallic conductor bump 2 is 4.8 micrometers.
  • the ratio of the diameter of the large-diameter side to the small-diameter side of the convex-shaped metallic conductor bump 2 is a numerical value that represents the sharpness of the tip of the convex-shaped metallic conductor bump 2.
  • the tip of the convex metallic conductor bump 2 is pointed. Since specific specifications are employed in which the film thickness and material of the top layer 4c of the bump 4 and the soft metal layer 4b inside the bump 4 are limited, the tip of the conductor bump 2 does not need to be extremely sharp.
  • the conductor bump 2 of the present embodiment has an axis substantially perpendicular to the semiconductor surface, and an angle 8 formed between the outer surface near the tip and a plane parallel to the semiconductor surface is about 35 to 55 degrees. It is made to be a range. If it is excessively sharp beyond 55 degrees, there is a higher risk of problems such as buckling of the bump tip during the manufacturing process. Conversely, at an obtuse angle of less than 35 degrees, the convex metallic conductor bump 4 There is a tendency that a large load is required in the penetration process of the top layer 4c formed on the surface and the press-fitting process into the soft metal layer 4b.
  • the angle is not limited to the tip but strictly near the tip, and a minute region including the tip of the bump 4 may be a flat shape or a rounded shape parallel to the semiconductor element substrate.
  • the convex metallic conductor bump 2 of the present invention is press-fitted into the soft metal layer 4b inside the convex metallic conductor bump 4 as described above, the material is higher in hardness than the soft metal layer 4b. It is necessary that buckling does not occur in the press-fitting process. From such a viewpoint, in the present invention, it is desirable to select a metal conductor having a shear strength of 25 GPa or more for the convex metallic conductor bump 2. More specifically, Au, Ag, Cu, Ni, NiCu alloy, CuSn alloy (speculum alloy), Ti, and the like.
  • the height matching layer 4a in the convex metallic conductor bump 4 with which the tip of the metallic conductor bump 2 abuts can be easily deformed or buckled due to the abutting of the tip of the metallic conductor bump 2. It is desirable that this does not occur.
  • the material of the height matching layer 4a is preferably selected from a conductor having a Mohs hardness of 0.5 or more higher than that of the metallic conductor bump 2.
  • a nickel film (Mohs hardness 4.0) having a Mohs hardness 1.0 larger than the copper film (Mohs hardness 3.0) is employed.
  • the hardness of the nickel film can be controlled by its manufacturing method, and the height matching layer 4a was produced using a plating method having a wide hardness control range (details of the manufacturing method of the height matching layer 4a will be described later).
  • a method for controlling the film hardness using a plating method is as follows: an additive called a leveler or brightener is added to the plating solution to suppress unevenness on the surface of the plating film so that a smooth surface is obtained. good.
  • an additive called a leveler or brightener is added to the plating solution to suppress unevenness on the surface of the plating film so that a smooth surface is obtained. good.
  • the material of the conductor bump 2, the internal structure of the conductor bump 4, and the material, thickness, hardness, and shape of each constituent layer are finely defined, so that reliable bonding at low temperature and low load can be realized. .
  • more than 1,000 bumps can be bonded together, and when semiconductor chips with low brittle fracture resistance such as SiC and GaN are laminated and bonded according to the specifications of the present embodiment, there is no chip destruction. We were able to join.
  • FIG. 4 is a diagram showing a schematic cross-sectional structure for explaining a manufacturing method for producing the conductor bump 2 on the first semiconductor element substrate 1.
  • FIG. 4A is a schematic diagram showing a cross-sectional structure of the first semiconductor element substrate 1 used in this example. Although the detailed structure is omitted here, at least one semiconductor circuit is formed on the first semiconductor element substrate 1, and the first surface of the first semiconductor element substrate 1 is external to each semiconductor circuit. An output terminal 6 is provided.
  • a first uniform thickness conductor layer 7 is formed with a uniform thickness so as to completely cover the external output terminal 6 (FIG. 4B). Since this figure is only a schematic diagram, the detailed layer structure of the first uniform-thickness conductor layer 7 is not described, but the first uniform-thickness conductor layer 7 is a multilayer film for convenience of the manufacturing process. It does not matter.
  • the uniform-thickness conductor layer 7 employs a two-layer film made of two kinds of materials, Cr and Cu, and in order to ensure film thickness uniformity, both layers are continuously formed using a sputtering method. Filmed.
  • a Cr film having a thickness of 75 nanometers is used in order to ensure that the first semiconductor element substrate 1 and the first uniform thickness conductor layer 7 are in close contact with each other.
  • other materials such as Ti and W are used.
  • an adhesive film may be used instead.
  • the Cu film of the first uniform thickness conductor layer 7 is formed so as to have a thickness of 4.9 micrometers.
  • the first semiconductor element substrate 1 having the conductor bumps 2 is produced by selectively etching away the desired position of the first uniform thickness conductor layer 7 (FIG. 4C).
  • a photosensitive resist is formed on the surface of the uniform-thickness conductor layer 7 in order to selectively remove the desired position of the uniform-thickness conductor layer 7, and a desired portion to be selectively removed by exposure and development. After the etching resist was removed, the remaining portion of the resist was used as an etching mask and treated with an etching solution for dissolving the uniform-thickness conductor layer 7.
  • the photosensitive etching resist suitable for the present invention may be a material that can obtain a desired shape and resolution, so that it is not necessary to use a special material, but it can be formed with a film thickness of 10 micrometers or less.
  • a resist is desirable. This is because when the film thickness exceeds 10 micrometers, the risk that the size of the resist opening width and the density of the opening affect the etching shape and the film thickness uniformity of the etching shape increases.
  • a positive dry film resist having a film thickness of 2.3 ⁇ m is used, and an etching solution of a sulfuric acid-hydrogen peroxide mixture system is used to remove the Cu film having a thickness of 4.9 ⁇ m.
  • the etching on the upper side proceeds faster than the etching on the lower side (the side in close contact with the substrate). Formed spontaneously.
  • the bump 2 having a uniform inclination angle 8 in the surface could be formed.
  • the remaining Cr film between the bumps 2 is removed by etching with an alkaline Cr etching solution, and finally the resist is peeled off, whereby the conductor bumps having sharp points are formed.
  • the first semiconductor element substrate 1 in which 2 was formed at a desired location could be produced.
  • FIG. 4 is omitted because it is a schematic structural diagram, but it is needless to point out that a 75 nm thick Cr film remains at the boundary between the conductor bump 2 and the semiconductor element substrate 1. .
  • an antioxidant film may be formed on the surface of the conductor bump 2 in order to suppress surface oxidation that causes a decrease in the bonding property of the conductor bump 2 having a sharp tip.
  • the conductor bump 2 is a precisely controlled fine-cone-shaped Cu, it is possible to form a film simply and at low cost, without affecting the bonding property, and An Sn plating film serving as an antioxidant film having a good surface slip was formed by a displacement plating method.
  • a film other than Sn may be used as long as the anti-slip film has good surface slipperiness and low cost.
  • Organic anti-oxidation coatings such as preflux and so-called OSP (Organic Solderability Preservative) have a good anti-oxidation effect but are insufficient in terms of surface slipping, and are therefore not preferred for application to the present invention. .
  • the bump 2 having a sharp tip shape is manufactured by a wet etching method, so that the bump 2 having a uniform shape can be manufactured at low cost, and the shape cloth of the bump 2 is caused by nonuniformity. It was possible to suppress the decrease in bonding yield. Such yield reduction suppression exhibits a special effect in terms of manufacturing yield, manufacturing cost, and quality in the multi-layer laminated structure described later.
  • FIG. 5 is a diagram showing a schematic cross-sectional structure for explaining a manufacturing method for producing the conductor bump 4 on the second semiconductor element substrate 3, and FIG. 5 (a) shows the second structure used in this embodiment.
  • 2 is a schematic view showing a cross-sectional structure of a semiconductor element substrate 3.
  • FIG. Although the detailed structure is omitted here, at least one semiconductor circuit is formed on the second semiconductor element substrate 3, and the first surface of the second semiconductor element substrate 3 is external to each semiconductor circuit.
  • An output terminal 9 is provided.
  • the second uniform-thickness conductor layer 10 is formed with a uniform thickness so as to completely cover the external output terminal 9 (FIG. 5 ( b)).
  • the second uniform-thickness conductor layer 10 is a multilayer film for convenience of the manufacturing process. It does not matter.
  • a multilayer structure composed of two kinds of materials, Cr and Cu, is employed as the uniform-thickness conductor layer 10, and continuous film formation is performed by a sputtering method in order to ensure film thickness uniformity.
  • the second uniform-thickness conductor layer 10 is a conductor film for the plating base used to produce the bumps 4 on the first surface of the second semiconductor element substrate 3, so that the plating step It is sufficient to have a film thickness that can ensure the adhesion and current density distribution required for the above.
  • a 75 nm thick Cr film was used as the adhesion film
  • a 500 nm thick Cu film was used as the conductor film.
  • a conductor bump 4 is formed at a desired position of the second uniform film thickness conductor layer 10 (FIG. 5C).
  • a photosensitive resist is formed on the surface of the uniform-thickness conductor layer 10 in order to selectively grow a conductor structure that selectively becomes bumps 4 at desired positions of the uniform-thickness conductor layer 10.
  • a predetermined exposure and development process is performed on the photosensitive resist to remove the resist at a desired portion, and then a conductor to be the bump 4 is grown by plating using the remaining portion of the resist as a plating resist mask.
  • the metallic conductor bump 4 provided on the second semiconductor element substrate 3 uses a composite structure made of at least three kinds of materials.
  • a three-layer continuous plating technique of the height matching layer 4a, the soft metal layer 4b, and the top layer 4c is applied, and about 4 micron is applied.
  • the height matching layer 4a has a metric thickness
  • the soft metal layer 4b has a thickness of about 3.8 micrometers
  • the top layer 4c has a thickness of 0.05 to 0.40 micrometers.
  • the photosensitive plating resist suitable for the present invention may be any material that can obtain a desired shape and resolution, so that it is not necessary to use a special material, but a film thickness of 10 micrometers or more is 20 micrometers. It is desirable that the resist has a resolution of a certain degree. In this embodiment, such a resist is used by forming a film with a film thickness exceeding 10 ⁇ m. When the film thickness is less than 10 micrometers, the above-described height matching layer 4a (film thickness 4 micrometers), soft metal layer 4b (film thickness 3.8 micrometers), and top layer 4c (film thickness 0.05-0. This is because it becomes difficult to apply to 40-micrometer) three-layer continuous plating.
  • a negative dry film resist having a thickness of 14.8 micrometers is used, and the height matching layer 4a having a thickness of 4 micrometers is plated with nickel sulfamate and a soft metal having a thickness of 3.8 micrometers.
  • Indium sulfate-based acidic indium plating was applied to the layer 4b, and flash silver plating was applied to the top layer 4c. After performing a predetermined three-layer continuous plating process, resist removal and pattern separation were performed, whereby the second semiconductor element substrate 3 in which the conductor bumps 4 having a three-layer structure were formed at desired locations could be produced.
  • FIG. 5 is omitted because it is a schematic structural diagram, but a 500 nm thick Cu conductor film and a 75 nm thick Cr film remain at the boundary between the conductor bump 4 and the semiconductor element substrate 3. There is no need to point it out again.
  • FIG. 6 shows a bonding of the bumped semiconductor element substrate 1 manufactured based on the manufacturing method described with reference to FIG. 4 and the bumped semiconductor element substrate 3 manufactured based on the manufacturing method described using FIG. It is a schematic sectional drawing for demonstrating the process to do.
  • the semiconductor element substrate 1 with the first bump and the semiconductor element substrate 3 with the second bump are arranged at the upper and lower opposing positions, and the bump positions are aligned with each other (FIG. 6A).
  • the bump 2 provided on the first bumped semiconductor element substrate 1 is moved by relatively moving the first bumped semiconductor element substrate 1 and the second bumped semiconductor element substrate 3. Is press-fitted into the bumps 4 provided on the second bumped semiconductor element substrate 3.
  • the first semiconductor element substrate 1 may be fixed and the second semiconductor element substrate 3 may be moved, in the present embodiment, the second bumped semiconductor element fixedly installed on the lower side
  • the conductor bumps 2 with sharp tips provided on the surface of the first semiconductor element substrate 1 are changed into the second bumps. It was intended to press fit into the conductor bump 4 having a soft metal layer provided on the surface of the attached semiconductor element substrate 3.
  • the first semiconductor element substrate 1 and the second semiconductor are disposed when the first semiconductor element substrate 1 is disposed on the upper side and the second semiconductor element substrate 3 is disposed on the lower side.
  • a predetermined amount of the underfill material 5 to be filled in the gap portion between the element substrates 3 is weighed, the predetermined amount of the underfill material 5 is placed on the second semiconductor element substrate 3, and then the first A process of moving the semiconductor element substrate 1 and press-fitting it was adopted.
  • the underfill material 5 is filled using a capillary phenomenon in which the gap between the semiconductor element substrates becomes a capillary.
  • the height of the conductive bump 2 having a sharp tip formed on the surface of the first semiconductor element substrate 1 is the conductor bump containing the soft metal layer formed on the surface of the second semiconductor element substrate 3.
  • the height of the bump 2 having a sharp tip is desirably in the range of 10 to 95% with respect to the total height of the soft metal layer-containing bump 4.
  • the present invention has realized a chip laminated structure in which at least two semiconductor chips are laminated and joined.
  • FIG. 7 is a schematic diagram for explaining another embodiment of the semiconductor device according to the present invention.
  • a third semiconductor element substrate 12 having bumps on both the front and back surfaces is stacked in multiple stages and mounted on the package substrate 11. 1 shows a schematic cross-section of the structure of a semiconductor device.
  • the first semiconductor in which the sharp bumps 2 are formed in the above-described Example 1. The element substrate 1 was diverted.
  • the third semiconductor element substrate 12 of the present embodiment is manufactured by applying the bump 2 and bump 4 manufacturing method described in Example 1 above. Although a detailed description is omitted, first, the bump 2 having a sharp tip is formed on the first surface of the semiconductor element substrate 12, and a plating resist is formed on the entire first surface. Thereafter, the bumps 4 including the soft metal layer can be formed on the second surface of the semiconductor element substrate 12.
  • the plating resist material formed on the entire surface of the first surface is different from the plating resist material for forming the bumps on the second surface. The occurrence of problems is suppressed.
  • the semiconductor element substrate 12 used in the present embodiment is formed with wiring for ensuring electrical connection between the bumps formed on the front and back surfaces (not shown).
  • a specific example of the wiring for ensuring electrical connection is a through-hole wiring that penetrates the semiconductor element substrate 12 in the plate thickness direction.
  • the front and back surfaces are electrically connected using fine wiring formed on the side wall surface of the semiconductor element substrate 12.

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Abstract

Provided is a method for joining a plurality of semiconductor device substrates at room temperature with a light load when electrically connecting the substrates to each other at the shortest distance using a large number of bumps. When a first semiconductor device substrate disposed above is joined to a second semiconductor device substrate disposed below through projecting metal conductor bumps, the projecting bumps, each tip end of which has been pointed, are press-fit into bumps containing soft metal. The bump containing soft metal has a composite structure formed of at least three kinds of materials for a top portion, side wall portion, and soft metal main portion.

Description

半導体装置およびその製造方法Semiconductor device and manufacturing method thereof
　本発明は、少なくとも2段以上の半導体素子を積み重ねてなる半導体装置およびその製造方法に関し、半導体装置のバンプ電極構造およびバンプ電極の接合方法に関する。 The present invention relates to a semiconductor device in which semiconductor elements of at least two stages or more are stacked and a manufacturing method thereof, and relates to a bump electrode structure of the semiconductor device and a bump electrode bonding method.
　電気電子機器には、近年、ますます高機能かつ高速な情報処理が求められるようになってきた。そこで、このようなニーズをタイムリーに実現することを目的に、複数個の半導体素子が組み合わせて使用される例が増え始めている。 In recent years, electrical and electronic devices have been increasingly required to have high-performance and high-speed information processing. Therefore, an example in which a plurality of semiconductor elements are used in combination for the purpose of realizing such needs in a timely manner has begun to increase.
　複数個の半導体素子を組み合わせて使用する際に、それぞれの半導体素子の性能を最大限に引き出すには、一般的には、半導体素子間を電気的に接続する導体長を最小化することが望ましいと言われている。そこで、第1の半導体素子の上部に第2の半導体素子を積み重ねていわゆる3次元的な構造を構築して半導体素子間の最短接続を実現し、それによって各半導体素子の性能を最大限引き出そうとする試みが提案されている。 In order to maximize the performance of each semiconductor element when a plurality of semiconductor elements are used in combination, it is generally desirable to minimize the length of a conductor that electrically connects the semiconductor elements. It is said. Therefore, the second semiconductor element is stacked on top of the first semiconductor element to construct a so-called three-dimensional structure to realize the shortest connection between the semiconductor elements, thereby trying to maximize the performance of each semiconductor element. Attempts to do so have been proposed.
　例えば、特開2006-210745号公報（特許文献１）では、上下２個の半導体チップ間を最短距離で接続するために、貫通孔を設けたインターポーザチップを上下の半導体チップ間に配置して、半導体チップ表面に設けた突起電極を貫通孔に圧接注入させた構造を提案している。 For example, in Japanese Unexamined Patent Publication No. 2006-210745 (Patent Document 1), in order to connect two upper and lower semiconductor chips at the shortest distance, an interposer chip provided with a through hole is disposed between the upper and lower semiconductor chips, A structure has been proposed in which a protruding electrode provided on the surface of a semiconductor chip is pressed into a through hole.
特開2006-210745号公報Japanese Unexamined Patent Publication No. 2006-210745
　上記特許技術１においては、複数の半導体チップ間を３次元的に積み重ねて最短の配線長での接続を実現している。その際、上側に配置した半導体チップに設けた凸形状の外部接続端子を、下側に配置した半導体チップに設けた凹形状の外部接続端子に圧接注入するわけであるが、その際、上下の半導体チップ間の電気的な接続を加熱せずに確実に実現するために、前記外部接続端子の金属を組成流動させる技術を採用している。 In the above-mentioned patent technology 1, a plurality of semiconductor chips are three-dimensionally stacked to achieve connection with the shortest wiring length. At that time, the convex external connection terminal provided on the semiconductor chip arranged on the upper side is pressed and injected into the concave external connection terminal provided on the semiconductor chip arranged on the lower side. In order to reliably realize the electrical connection between the semiconductor chips without heating, a technique of compositionally flowing the metal of the external connection terminal is employed.
　金属を組成流動させるためには、実用上は、半導体チップを加圧しながら超音波振動を付加する方法、いわゆる超音波ボンディング法が採られる。超音波ボンディング法では、半導体チップに設けた金属性バンプ（外部接続端子）をその金属の融点以下の温度で組成流動させるために荷重下での超音波印加を実施する。このような超音波ボンディング法では、一般に、そのボンディングツールの振動幅が最小でプラスマイナス１０マイクロメートル程度は必要とされている。ボンディングツールの振幅幅がプラスマイナス１０マイクロメートルを下回ると、金属性バンプの塑性変形量が小さくなり、その結果として、組成流動量も小さくなって外部接続端子同士の接触部で十分な接続断面積を確保することが難しくなるからである。ボンディングツールがプラスマイナス１０マイクロメートルの振幅を持つように超音波を印加すると、金属バンプの位置変位が１０マイクロメートル程度は発生することになり、そのようなバンプの変位は接合の位置精度を低下させて高位置精度の接合の歩留を下げる原因の１つとなったり、小径バンプの場合にはバンプの破断原因の１つとなったりする傾向がある。従って、狭ピッチで接続する用途、特に小径バンプで狭ピッチ接続する用途へ超音波ボンディング技術を適用する場合には改善の余地が大きい。 In order to make the metal composition flow, a method of applying ultrasonic vibration while applying pressure to the semiconductor chip, that is, a so-called ultrasonic bonding method is practically used. In the ultrasonic bonding method, ultrasonic application under a load is performed in order to cause a metallic bump (external connection terminal) provided on a semiconductor chip to flow compositionally at a temperature below the melting point of the metal. In such an ultrasonic bonding method, generally, the vibration width of the bonding tool is required to be a minimum of about plus or minus 10 micrometers. When the amplitude width of the bonding tool is less than plus or minus 10 micrometers, the amount of plastic deformation of the metal bumps is reduced, and as a result, the amount of composition flow is also reduced, so that a sufficient connection cross-sectional area is obtained at the contact portion between the external connection terminals. This is because it is difficult to ensure the above. When ultrasonic waves are applied so that the bonding tool has an amplitude of plus or minus 10 micrometers, the position displacement of the metal bumps is generated by about 10 micrometers, and such bump displacement reduces the position accuracy of the bonding. As a result, it tends to be one of the causes of lowering the yield of high-position accuracy bonding, and in the case of a small-diameter bump, it may be one of the causes of bump breakage. Therefore, there is a lot of room for improvement when the ultrasonic bonding technology is applied to a connection with a narrow pitch, particularly a narrow pitch connection with a small-diameter bump.
　また、上述の通り、金属バンプを塑性流動させるためには、超音波に加えて加圧力を併用印加することが一般的に行われる。加圧力を最適化するためには、バンプは金属製であること、バンプ金属の弾性限界を越えて塑性変形させる荷重が印加される必要があること、などを鑑みる必要がある。超音波ボンディング技術においては、一般に、バンプ径にもよるが１バンプ当たり１０グラム程度、少なくとも数グラム程度の押圧荷重を超音波振動と同時に印加する。従って、バンプ数が多い半導体チップへ適用する場合には、例えば具体例として５００本を超える多数のバンプを有する半導体チップを接合するためには、半導体チップ全体としてはかなり大きな値の押圧荷重を印加することになる。上記特許文献１の技術においては、チップに貫通孔を設けているので、孔の開いた半導体チップ（通常、シリコンなどの脆性材料からなる）に対して大きな押圧荷重を印加することになり、半導体チップが脆性破壊する危険性があることは否定できない。また、孔の開いていない半導体チップであっても、脆性材料の加工工程において過大な押圧荷重を印加することは好ましい事とは言えない。特に、シリコン以外の化合物半導体、例えば、SiCやGaNなどの脆性破壊耐性が小さい半導体チップでは、チップの脆性破壊抑制の観点から、過大な押圧荷重を避ける必要性が高いことはいうまでもない。 Also, as described above, in order to plastically flow the metal bumps, it is generally performed to apply a pressure in addition to the ultrasonic waves. In order to optimize the applied pressure, it is necessary to consider that the bump is made of metal and that a load that causes plastic deformation beyond the elastic limit of the bump metal needs to be applied. In the ultrasonic bonding technique, generally, although depending on the bump diameter, a pressing load of about 10 grams per bump, at least about several grams, is applied simultaneously with ultrasonic vibration. Accordingly, when applied to a semiconductor chip having a large number of bumps, for example, in order to join a semiconductor chip having a large number of bumps exceeding 500 as a specific example, a considerably large value of pressing load is applied to the entire semiconductor chip. Will do. In the technique of Patent Document 1, since a through hole is provided in a chip, a large pressing load is applied to a semiconductor chip having a hole (usually made of a brittle material such as silicon). It cannot be denied that there is a risk that the chip will brittlely break. In addition, it is not preferable to apply an excessive pressing load in a brittle material processing step even for a semiconductor chip having no holes. In particular, compound semiconductors other than silicon, for example, semiconductor chips with low brittle fracture resistance such as SiC and GaN, needless to say, it is highly necessary to avoid an excessive pressing load from the viewpoint of suppressing brittle fracture of the chip.
　上記外部接続端子として金属製バンプを形成する方法として、上記特許文献１では、Auワイヤを用いたボールボンディング法を用いている（上記特許文献１の段落００３４参照）。ボールボンディング法を用いてバンプを形成する場合は、Auワイヤの先端を溶融してAuボール部を形成した後に、そのボール部をチップ表面の所望の電極パッド箇所に押し当てて超音波振動を印加しながら熱圧着し、Auワイヤからボール先端を切断するという一連の工程によってバンプが作られる。細径のAuワイヤ、例えば、径が２０マイクロメートル以下の細径Auワイヤは取り扱いが難しいため需要が少なく、従って高価であるゆえ、小径バンプをボールボンディング法で作製すると高価とならざるを得ない。また、Auワイヤからボール先端を切断する際には、隣接するバンプとの間に隙間が必要なため、実用上は、狭ピッチバンプを実現するバンプレイアウトは外周１列に制限されている。したがって、逆にボールボンディング法を用いてフルグリッド配置でバンプ形成する場合には狭ピッチ配列をとり得ず、多数バンプを高密度で配置するという観点では改善の余地が有るといえる。 As a method for forming metal bumps as the external connection terminals, the above Patent Document 1 uses a ball bonding method using Au wires (see Paragraph 0034 of the above Patent Document 1). When bumps are formed using the ball bonding method, the tip of the Au wire is melted to form the Au ball part, and then the ultrasonic wave is applied by pressing the ball part against the desired electrode pad location on the chip surface. The bumps are made by a series of processes of thermocompression bonding and cutting the ball tip from the Au wire. Small-sized Au wires, for example, small-diameter Au wires having a diameter of 20 micrometers or less, are difficult to handle and are therefore less expensive and therefore expensive. Therefore, if small-diameter bumps are produced by the ball bonding method, they must be expensive. . Further, when the ball tip is cut from the Au wire, a gap is required between the adjacent bumps. Therefore, in practice, the bump layout for realizing the narrow pitch bump is limited to one row on the outer periphery. Therefore, conversely, when bumps are formed in a full grid arrangement using the ball bonding method, a narrow pitch arrangement cannot be taken, and it can be said that there is room for improvement in terms of arranging a large number of bumps at a high density.
　多数のＡｕバンプをフルグリッドかつ狭ピッチに配置できる方法としてめっきバンプ法が知られている。しかしながら、Ａｕバンプはアンダーフィル材との接着性が乏しい場合が多く、その結果として、アンダーフィルとＡｕバンプとの界面に隙間が生じて絶縁信頼性低下を招きやすい傾向があるので、フルグリッドかつ狭ピッチに配置された多数バンプを用いて半導体チップを接合する用途に使用する場合には、一定の制限がある。 The plating bump method is known as a method for arranging a large number of Au bumps at a full grid and a narrow pitch. However, Au bumps often have poor adhesion to the underfill material, and as a result, there is a tendency for gaps to form at the interface between the underfill and Au bumps, leading to a decrease in insulation reliability. There are certain limitations when used in applications where semiconductor chips are bonded using a large number of bumps arranged at a narrow pitch.
　上述のような様々な観点から考えると、上記特許文献１の技術は、多数のバンプを有する半導体チップの3次元積層への適用は必ずしも有利とは言えない。 Considering from various viewpoints as described above, the technique of the above-mentioned Patent Document 1 is not necessarily advantageous for application to a three-dimensional stack of semiconductor chips having a large number of bumps.
　本願発明者は、上記公報に記載された技術の改善策を探った結果、下記のような構造・構成、手段を採る事によって良好な結果を得ることができ、本願発明に至った。 The inventor of the present application has been able to obtain a good result by adopting the following structure, configuration, and means as a result of searching for a technique for improving the technique described in the above publication, and has reached the present invention.
　まず、本願発明にかかる半導体装置の1つの構造・構成は下記の通りである。第1の半導体素子基板の表面に形成した凸形状の金属性導体バンプと第2の半導体素子基板の表面に形成した凸形状の金属性導体バンプとを互いに接合させる。その際、前記第1の半導体素子基板の表面に形成した第1の凸形状金属性導体バンプは、あらかじめその先端を尖らせておく。一方、前記第2の半導体素子基板の表面に形成した第2の凸形状金属性導体バンプはその頂部、側壁部、および本体部の少なくとも３種類の材質からなる複合構造とし、その本体部は軟性金属とする。さらに、先端の尖った前記第1の凸形状金属性導体バンプの先端部分が前記第2の凸形状金属性導体バンプの本体部分である軟性金属層に圧入された構造とする。このような構造、構成により、半導体チップを積層してなるチップ積層構造体が実現できる。 First, one structure / configuration of a semiconductor device according to the present invention is as follows. A convex metallic conductor bump formed on the surface of the first semiconductor element substrate and a convex metallic conductor bump formed on the surface of the second semiconductor element substrate are bonded to each other. At that time, the tip of the first convex metallic conductor bump formed on the surface of the first semiconductor element substrate is sharpened in advance. On the other hand, the second convex metallic conductor bump formed on the surface of the second semiconductor element substrate has a composite structure composed of at least three kinds of materials, that is, a top portion, a side wall portion, and a main body portion, and the main body portion is flexible. Metal. Furthermore, the tip portion of the first convex metallic conductor bump having a sharp tip is press-fitted into the soft metal layer that is the main body portion of the second convex metallic conductor bump. With such a structure and configuration, a chip stacked structure in which semiconductor chips are stacked can be realized.
　本願発明にかかる半導体装置の別の１つの構造・構成として、上記構造・構成を応用して、半導体チップを多段に積層接合してなるチップ多段積層構造体を提供する。その際、半導体素子基板の第1の面には先端が尖った第1のバンプを有し、第2の面には頂部、側壁部、および軟性金属からなる本体部の少なくとも3種類の材質からなる複合構造となる第2のバンプを有した半導体素子基板を用いる。このような構造からなる両面バンプつき半導体素子基板を少なくとも３個以上用意し、第1の半導体素子基板の第1の面にあらかじめ形成されている先端が尖った第1-1のバンプと、第2の半導体素子基板の第2の面にあらかじめ形成されている軟性金属を含有する第2-2のバンプとを接合し、第２の半導体素子基板の第1の面にあらかじめ形成されている先端が尖った第2-1のバンプと、第３の半導体素子基板の第2の面にあらかじめ形成されている軟性金属を含有する第3-2のバンプとを接合する構造とする。このような構造を所望段数繰り返すことによって、所望段数の接合が為された構造および構成となり、所望段数の半導体チップを積層接合してなるチップ多段積層構造体を実現できる。 As another structure / configuration of the semiconductor device according to the present invention, there is provided a chip multi-stage stacked structure formed by stacking and joining semiconductor chips in multiple stages by applying the above structure / configuration. At that time, the first surface of the semiconductor element substrate has a first bump with a sharp tip, and the second surface is made of at least three kinds of materials including a top portion, a side wall portion, and a main body portion made of a soft metal. A semiconductor element substrate having a second bump having a composite structure is used. At least three semiconductor element substrates with double-sided bumps having such a structure are prepared, the 1-1st bump having a sharp tip formed in advance on the first surface of the first semiconductor element substrate, A tip formed beforehand on the first surface of the second semiconductor element substrate is bonded to the second surface of the second semiconductor element substrate bonded to the second bump 2-2 containing a soft metal formed in advance. The structure is such that the 2-1 bumps with sharp edges and the 3-2 bumps containing a soft metal formed in advance on the second surface of the third semiconductor element substrate are joined. By repeating such a structure for a desired number of stages, a structure and a structure in which a desired number of stages are joined are obtained, and a chip multistage laminated structure in which semiconductor chips having a desired number of stages are laminated and joined can be realized.
　本願発明では、本願発明に掛かる上記半導体装置の製造方法もあわせて提供する。本願発明の提供する半導体装置の製造方法は下記の通りである。 The present invention also provides a method for manufacturing the semiconductor device according to the present invention. The manufacturing method of the semiconductor device provided by the present invention is as follows.
　まず始めに、第1の半導体素子基板表面に均一膜厚にて第1の金属導体層を形成し、その第1の均一膜厚金属導体膜の所望箇所を選択的に湿式エッチング法によって加工除去して第1のバンプ付き半導体素子基板を作製する。湿式エッチング法を用いて所望箇所を選択的に除去する際には、フォトリソグラフィーなどの方法が望ましい。一方、上記第1の半導体素子基板とは別に、第2の半導体素子基板を用意し、この表面にも均一膜厚にて第2の金属導体層膜を形成して、さらにその上に少なくとも２種類の導体からなる導体層膜（第3の導体層、第4の導体層）を連続成膜した後に、前記第2～第4の金属導体層膜の所望部分を残して選択的に除去することによって第2のバンプ付き半導体素子基板を作製する。第3の導体層および第4の導体層の形成方法は、エッチング法でもめっき法でも構わない。めっき法を採用する場合には、フォトリソグラフィー技術を使って選択的にめっき析出させる箇所のみに第3および第4の導体層を連続的に形成した後に、めっきの種膜となった第2の導体層膜の不要な箇所を取り除くことによって前記第2～第4の金属導体層膜の所望部分を残すことができる。 First, a first metal conductor layer having a uniform thickness is formed on the surface of the first semiconductor element substrate, and a desired portion of the first uniform thickness metal conductor film is selectively processed and removed by a wet etching method. Thus, a first semiconductor element substrate with bumps is produced. When a desired portion is selectively removed using a wet etching method, a method such as photolithography is desirable. On the other hand, a second semiconductor element substrate is prepared separately from the first semiconductor element substrate, and a second metal conductor layer film is formed on the surface with a uniform film thickness. After continuously forming a conductor layer film (third conductor layer, fourth conductor layer) made of various types of conductors, it is selectively removed leaving a desired portion of the second to fourth metal conductor layer films. As a result, a second bumped semiconductor element substrate is fabricated. The method of forming the third conductor layer and the fourth conductor layer may be an etching method or a plating method. When the plating method is adopted, the second and second plating layers are formed after the third and fourth conductor layers are continuously formed only at the locations where the plating is selectively deposited using photolithography technology. By removing unnecessary portions of the conductor layer film, desired portions of the second to fourth metal conductor layer films can be left.
　その次の段階で、前記第1のバンプつき半導体素子基板と前記第2のバンプ付き半導体素子基板とを互いの相対的な位置が上下となるように配置し、前記第1のバンプ付き半導体素子基板のバンプ位置と前記第2のバンプ付き半導体素子基板のバンプ位置とを整合させる。 In the next step, the first bumped semiconductor element substrate and the second bumped semiconductor element substrate are arranged so that their relative positions are up and down, and the first bumped semiconductor element substrate The bump position of the substrate is matched with the bump position of the second bumped semiconductor element substrate.
　さらに次の工程では、第1のバンプ付き半導体素子基板上に設けられたバンプが第2のバンプ付き半導体素子基板上に設けられたバンプに圧入されるように、前記第1のバンプ付き半導体素子基板と前記第2のバンプ付き半導体素子基板とが相対的に移動させる。 Further, in the next step, the first bumped semiconductor element is so pressed that the bump provided on the first bumped semiconductor element substrate is pressed into the bump provided on the second bumped semiconductor element substrate. The substrate and the second bumped semiconductor element substrate are moved relative to each other.
　このような工程により、本願発明では少なくとも２個以上の半導体チップを積層接合してなるチップ積層構造体を実現するための製造方法を提供する。 By such a process, the present invention provides a manufacturing method for realizing a chip laminated structure in which at least two semiconductor chips are laminated and joined.
　本願発明の提供する技術によって得られる効果は下記の通りである。 The effects obtained by the technology provided by the present invention are as follows.
　3次元的に多段積層される複数の半導体チップ間を最短配線長で接続する熱圧着接合において、先端が尖ったバンプを軟性金属バンプへ圧入する構造としたことにより、従来と比べて低荷重で確実な接合が可能となる。 In thermocompression bonding where multiple semiconductor chips stacked in three dimensions are connected with the shortest wiring length, a bump with a sharp tip is pressed into a soft metal bump. Reliable joining is possible.
本発明の実施例にかかる半導体装置の1形態の断面を示す概略図である。It is the schematic which shows the cross section of 1 form of the semiconductor device concerning the Example of this invention. 本発明の実施例にかかる半導体素子基板の1形態の部分拡大構造断面を示す概略図であり、凸形状金属性導体バンプの断面構造の一例を示す概略図である。It is the schematic which shows the partial expanded structure cross section of one form of the semiconductor element substrate concerning the Example of this invention, and is schematic which shows an example of the cross-section of a convex-shaped metallic conductor bump. 本発明の実施例にかかる半導体装置の1形態の部分拡大構造断面を示す概略図であり、バンプ接合部の断面構造の一例を示す概略図である。It is the schematic which shows the partial expanded structure cross section of 1 form of the semiconductor device concerning the Example of this invention, and is schematic which shows an example of the cross-section of a bump junction part. 本発明の実施例にかかる半導体装置の製造方法において、その部分工程の1形態における断面構造を説明するための概略図である。FIG. 6 is a schematic diagram for explaining a cross-sectional structure in one form of the partial process in the method for manufacturing a semiconductor device according to the example of the present invention. 本発明の実施例にかかる半導体装置の製造方法において、別の部分工程の1形態における断面構造を説明するための概略図である。FIG. 10 is a schematic view for explaining a cross-sectional structure in one form of another partial process in the method for manufacturing a semiconductor device according to the example of the present invention. 本発明の実施例にかかる半導体装置の製造方法において、さらに別の部分工程の1形態における断面構造を説明するための概略図である。FIG. 10 is a schematic view for explaining a cross-sectional structure in one form of still another partial process in the method for manufacturing a semiconductor device according to the example of the present invention. 本発明の実施例にかかる半導体装置の別の1形態の断面を示す概略図である。It is the schematic which shows the cross section of another 1 form of the semiconductor device concerning the Example of this invention.
　以下、本願発明を実施するための形態を図面に基づいて説明する。なお、図面を構成する各部品にはそれぞれ符号を付して説明を施すが、同一機能の場合には符号や説明を省略する場合がある。また、図中に示した各部品の寸法は実際の部品寸法を反映した縮尺には必ずしも一致していない場合がある。 Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In addition, although it attaches | subjects and demonstrates each component which comprises drawing, a code | symbol and description may be abbreviate | omitted in the case of the same function. In addition, the dimensions of the parts shown in the drawing may not necessarily match the scale reflecting the actual part dimensions.
　本実施形態の半導体装置の断面概略構造を図１に示す。 FIG. 1 shows a schematic cross-sectional structure of the semiconductor device of this embodiment.
　第1の半導体素子基板１の表面には複数個の凸形状の金属性導体バンプ２が形成されており、第2の半導体素子基板３の表面には複数個の凸形状の金属性導体バンプ４が形成されている。第1の半導体素子基板１と第2の半導体素子基板３とはお互いにその表面を向かい合わせに配置され、第1の半導体素子基板１上に設けられた凸形状金属性導体バンプ２は第2の半導体素子基板３上に設けられた凸形状の金属性導体バンプ４に圧入されてそれぞれの凸形状の金属性導体バンプ２と４とを電気的に接続している。第1の半導体素子基板１と第2の半導体素子基板３との間のギャップ部には、金属性導体バンプの隙間を埋めるようにアンダーフィル材５が充填され、第1の半導体素子基板１と第2の半導体素子基板３とが分離しないように固定されている。アンダーフィル材５は、半導体素子基板１と第2の半導体素子基板３とを固定するだけではなく、金属性導体バンプ間の絶縁信頼性を確保し、また、そのアンダーフィル材５自身が有する応力分散作用によって接続信頼性の確保に寄与している。またアンダーフィル材５の熱収縮作用および硬化収縮作用によって、第1の半導体素子基板1上に設けられた金属性導体バンプ２と第2の半導体素子基板３上に設けられた金属性導体バンプ４との接合界面に適正な応力が作用し続ける構造となっている。 A plurality of convex metal conductor bumps 2 are formed on the surface of the first semiconductor element substrate 1, and a plurality of convex metal conductor bumps 4 are formed on the surface of the second semiconductor element substrate 3. Is formed. The first semiconductor element substrate 1 and the second semiconductor element substrate 3 are arranged with their surfaces facing each other, and the convex metallic conductor bumps 2 provided on the first semiconductor element substrate 1 are second. The convex metallic conductor bumps 4 provided on the semiconductor element substrate 3 are press-fitted to electrically connect the convex metallic conductor bumps 2 and 4 to each other. The gap portion between the first semiconductor element substrate 1 and the second semiconductor element substrate 3 is filled with an underfill material 5 so as to fill the gap between the metallic conductor bumps. The second semiconductor element substrate 3 is fixed so as not to be separated. The underfill material 5 not only fixes the semiconductor element substrate 1 and the second semiconductor element substrate 3, but also ensures insulation reliability between the metallic conductor bumps, and the stress of the underfill material 5 itself. Distributing action contributes to securing connection reliability. Further, the metal conductor bumps 2 provided on the first semiconductor element substrate 1 and the metal conductor bumps 4 provided on the second semiconductor element substrate 3 by the heat shrinkage action and the hardening shrinkage action of the underfill material 5. Appropriate stress continues to act on the joint interface.
　本願発明では、第2の半導体素子基板３上に設けられた金属性導体バンプ４は、少なくとも３種類以上の材質からなる複合構造体を使用する。本実施形態では、図２に示してあるとおり、高さ整合層４ａ、軟性金属層４ｂ、頂部層４ｃ、側壁部４ｄの４種類の材質からなる複合構造体を用いた。 In the present invention, the metallic conductor bump 4 provided on the second semiconductor element substrate 3 uses a composite structure made of at least three kinds of materials. In this embodiment, as shown in FIG. 2, a composite structure made of four kinds of materials, that is, a height matching layer 4a, a soft metal layer 4b, a top layer 4c, and a side wall portion 4d was used.
　本実施形態で採用した高さ整合層４ａは、凸形状金属性導体バンプ２を凸形状金属性導体バンプ４に圧入する際に、その圧入深さを制御するための層である。本実施形態においては、高さ整合層４ａを内包する導体バンプ４を用いたことにより、半導体素子基板１と半導体素子基板３との間のギャップが所望の値となるように精密に制御され、またその数値ばらつき範囲も制御できる。より具体的には、半導体素子基板１と半導体素子基板３との間のギャップ値のばらつき範囲は高さ整合層４ａの厚みばらつき範囲とほぼ同じとなる。高さ整合層４ａの厚みばらつきは、高さ整合層４ａ平均厚みのプラスマイナス１０％以下となるように製造することは比較的容易であり、一般にそのような仕様で作製されるので、半導体素子基板１と半導体素子基板３との間のギャップ値のばらつき範囲をプラスマイナス１０％以下に制御することは容易に実現される。高さ整合層４ａの製造方法の詳細については後述するが、高さ整合層４ａの製造方法を工夫すれば、ギャップ値のばらつき範囲を更に抑制できる。更に具体的に一例を示すなら、高さ整合層４ａの平均厚みが５マイクロメートルの場合、半導体素子基板１と半導体素子基板３との間のギャップ値のばらつき範囲はプラスマイナス０．５マイクロメートル以下となるように制御される。 The height matching layer 4a employed in the present embodiment is a layer for controlling the press-fitting depth when the convex metallic conductor bump 2 is press-fitted into the convex metallic conductor bump 4. In the present embodiment, by using the conductor bump 4 including the height matching layer 4a, the gap between the semiconductor element substrate 1 and the semiconductor element substrate 3 is precisely controlled so as to have a desired value. The numerical variation range can also be controlled. More specifically, the variation range of the gap value between the semiconductor element substrate 1 and the semiconductor element substrate 3 is substantially the same as the thickness variation range of the height matching layer 4a. It is relatively easy to manufacture the thickness variation of the height matching layer 4a so that the average thickness of the height matching layer 4a is equal to or less than 10%. Control of the variation range of the gap value between the substrate 1 and the semiconductor element substrate 3 to plus or minus 10% or less is easily realized. The details of the manufacturing method of the height matching layer 4a will be described later, but if the manufacturing method of the height matching layer 4a is devised, the variation range of the gap value can be further suppressed. More specifically, when the average thickness of the height matching layer 4a is 5 micrometers, the variation range of the gap value between the semiconductor element substrate 1 and the semiconductor element substrate 3 is plus or minus 0.5 micrometers. Control is performed as follows.
　本実施形態では、上述のような高さ整合層４ａを設けたことによって半導体素子基板間ギャップの精密制御を実現し、その結果として、アンダーフィル材５の充填工程における不具合発生の低減に成功した。半導体素子基板間ギャップを精密に制御できるようになったことにより、その所望のギャップ値において最適となるようなアンダーフィル充填条件を選択できたためであると考えている。一般に、半導体素子基板間のギャップが５０マイクロメートル以下となるような積層実装構造においては、半導体素子基板間ギャップがアンダーフィル５の充填工程における流路抵抗の主要要因の１つとなる。従って、アンダーフィル充填工程における不具合発生を抑制するためには、本実施形態のように半導体素子基板間ギャップを精密に制御するための高さ整合層４ａを設けることが望ましいわけである。逆に、高さ整合層４ａを設けない場合には、半導体素子基板間ギャップの値を安定させるための別種の制御方法や製造方法を採らなければ、アンダーフィル５の充填工程における流路抵抗が安定しないことに起因してアンダーフィル充填不具合発生の危険性が高まる。 In the present embodiment, by providing the height matching layer 4a as described above, precise control of the gap between the semiconductor element substrates is realized, and as a result, the occurrence of defects in the filling process of the underfill material 5 has been successfully reduced. . This is considered to be because the underfill filling conditions that are optimum for the desired gap value can be selected because the gap between the semiconductor element substrates can be precisely controlled. In general, in a stacked mounting structure in which the gap between semiconductor element substrates is 50 micrometers or less, the gap between semiconductor element substrates is one of the main factors of flow path resistance in the filling process of the underfill 5. Therefore, in order to suppress the occurrence of problems in the underfill filling process, it is desirable to provide the height matching layer 4a for precisely controlling the gap between the semiconductor element substrates as in this embodiment. On the other hand, when the height matching layer 4a is not provided, the flow resistance in the filling process of the underfill 5 is reduced unless another control method or manufacturing method for stabilizing the value of the gap between the semiconductor element substrates is employed. There is an increased risk of underfill filling problems due to instability.
　軟性金属層４ｂは金属性導体バンプ４の本体部分であり、金属性導体バンプ２が圧入されて、金属性導体バンプ２との間で接合界面を為す層となる。金属性導体バンプ２を圧入する工程において低荷重での圧入を実現するためには、軟性金属層４ｂに変形容易な導体を用いることが望ましい。変形容易な導体として多種多様な材料が知られているが、本願発明者は金属性導体バンプ２との確実な接合界面を形成するという観点から、導電性樹脂よりも金属材料あるいは合金材料が望ましいと判断した。さらに、さまざまな金属材料あるいは合金材料について、本願発明技術への適用可能性を検討し、ブリュネル硬度が１００ＭＰａ以下となる金属性材料が望ましく、ブリュネル硬度が５０ＭＰａ未満であれば特に好ましいという指針を得た。逆にブリュネル硬度が５０ＭＰａ以上となると、金属性導体バンプ２を圧入する工程において必要な荷重が大きくなり、半導体素子の動作特性に影響が現れることがある。ブリュネル硬度が５０ＭＰａ以下となる導体金属の具体例を挙げると、例えば、Ｉｎ（ブリュネル硬度＝９ＭＰａ）、Ｎａ（ブリュネル硬度＝０．７ＭＰａ）、Ａｇ（ブリュネル硬度＝２５ＭＰａ）、Ｐｂ（ブリュネル硬度＝３８ＭＰａ）などが挙げられる。ちなみに、Ｓｎはブリュネル硬度＝５１ＭＰａであるので、本願発明の軟性金属層４ｂとして最も好ましい導体金属の範疇には入らない。また、ブリュネル硬度が５０ＭＰａ未満の幾つかの金属、例えば、Ｎａ（ブリュネル硬度＝０．７ＭＰａ）は安全性の観点から実用的とは言えないし、環境的な観点で法的な規制が設けられているＰｂ（ブリュネル硬度＝３８ＭＰａ）やＰｂ含有導体はその実用性には制限が有る。こうした観点を総合的に鑑み、本実施形態では軟性金属層４ｂに最も好ましい材料として金属Ｉｎ（ブリュネル硬度＝９ＭＰａ）を採用した。 The soft metal layer 4 b is a main body portion of the metal conductor bump 4, and the metal conductor bump 2 is press-fitted to form a bonding interface with the metal conductor bump 2. In order to realize press-fitting with a low load in the step of press-fitting the metallic conductor bump 2, it is desirable to use a conductor that can be easily deformed for the soft metal layer 4b. A wide variety of materials are known as easily deformable conductors, but the present inventors prefer a metal material or an alloy material rather than a conductive resin from the viewpoint of forming a reliable bonding interface with the metallic conductor bump 2. It was judged. Furthermore, for various metal materials or alloy materials, the applicability to the technology of the present invention was examined, and a metallic material having a Brunel hardness of 100 MPa or less is desirable, and a guideline is obtained that the Brunel hardness is particularly preferably less than 50 MPa. It was. On the other hand, if the Brunner hardness is 50 MPa or more, the load required in the process of press-fitting the metallic conductor bump 2 becomes large, which may affect the operating characteristics of the semiconductor element. Specific examples of the conductor metal having a Brunel hardness of 50 MPa or less include, for example, In (Brunel hardness = 9 MPa), Na (Brunel hardness = 0.7 MPa), Ag (Brunel hardness = 25 MPa), Pb (Brunel hardness = 38 MPa). ) And the like. Incidentally, Sn does not fall within the category of the most preferable conductor metal as the soft metal layer 4b of the present invention because the Brunel hardness is 51 MPa. In addition, some metals having a Brunel hardness of less than 50 MPa, such as Na (Brunel hardness = 0.7 MPa), are not practical from the viewpoint of safety, and are legally restricted from an environmental viewpoint. Pb (Brunel hardness = 38 MPa) and Pb-containing conductors are limited in their practicality. Considering such a viewpoint comprehensively, in this embodiment, metal In (Brünel hardness = 9 MPa) is adopted as the most preferable material for the soft metal layer 4b.
　金属性導体バンプ４のバンプ頂部にはバンプ頂部層４ｃが設けられており、金属性導体バンプ４の頂上部分の酸化を防止する膜となっている。このバンプ頂部層４ｃは凸形状金属性導体バンプ２を凸形状金属性導体バンプ４に圧入する際に破断される必要があるので、破断が容易な膜であることが望ましい。本願発明者は破断が容易ないくつかの材料について本願発明技術への適用可能性を検討した結果、シェア強度（Ｓｈｅａｒ　Ｍｏｄｕｌｕｓ）が５０ＧＰａ以下となる皮膜であれば凸形状金属性導体バンプ２を圧入する際に障害となりにくく、シェア強度が３０ＧＰａ以下でかつ膜厚が１．０マイクロメータ以下であれば障害になることはほとんどないという指針を得た。製造のし易さ、酸化防止作用、導体抵抗を考慮すれば、本願発明のバンプ頂部層４ｃには金属の薄膜が望ましい。本実施形態においては、最も好ましい材料としてＡｇ（Ｓｈｅａｒ　Ｍｏｄｕｌｕｓ＝３０ＧＰａ）を採用し、その厚みを最大でも１．０マイクロメータ以下となるように制限した上で用いる。バンプ頂部層４ｃの膜厚が１．０マイクロメートルを越えて大きくなる場合、凸形状金属性導体バンプ２を圧入する工程において破断に必要な荷重が大きくなり、その結果として、半導体素子の動作特性に影響が現れることがある。本実施形態では、バンプ頂部層４ｃの膜厚０．０５～０．４０マイクロメートルの範囲で作製した。バンプ頂部層４ｃの膜厚が０．０５マイクロメートルを下回ると、金属性導体バンプ４の酸化防止の作用が十分に得られない傾向が見られるためである。膜厚０．０５～０．４０マイクロメートルの範囲で作製されたバンプ頂部層４ｃを用いれば、凸形状金属性導体バンプ２の圧入時の破断には特段の問題は発生しない。また、バンプ頂部層４ｃの膜厚が厚ければ、バンプ頂部層４ｃの残骸となる破断断片が金属性導体バンプ２と金属性導体バンプ４との界面付近に生成することがあるが、本実施形態では膜厚０．０５～０．４０マイクロメートルの範囲で制限したため、残骸となる破断断片の発生はごく僅かである。また、僅かに発生する破断断片は、軟性金属層４ｂとして採用したＩｎと反応してＩｎ-Ａｇ共晶（共晶温度１４１℃）となって軟性金属層４ｂ内へ拡散するので、バンプ頂部層４ｃの残骸が金属性導体バンプ２と金属性導体バンプ４との接合性を損なうことはない。逆に、本実施形態においては、適切な膜厚（０．０５～０．４０マイクロメートル）のバンプ頂部層４ｃを用いたことにより、その断片がバンプ２の導体および導体バンプ４内部の高さ整合層４ａの導体と合金化し、あるいはバンプ２の導体と導体バンプ４内部の高さ整合層４ａ導体との合金化反応を促進して、バンプ２とバンプ４との間の接合面を強化する作用があった。 A bump top layer 4 c is provided on the top of the bump of the metal conductor bump 4, and serves as a film that prevents oxidation of the top of the metal conductor bump 4. Since the bump top layer 4c needs to be broken when the convex metallic conductor bump 2 is press-fitted into the convex metallic conductor bump 4, it is desirable that the bump top layer 4c be a film that can be easily broken. As a result of studying the applicability of the present invention to some materials that can be easily broken, the inventor of the present application press-fits the convex metallic conductor bump 2 if the film has a shear strength of 50 GPa or less. The guideline was obtained that it is difficult to cause an obstacle when the shear strength is 30 GPa or less and the film thickness is 1.0 micrometer or less. In view of ease of manufacture, antioxidant action, and conductor resistance, a metal thin film is desirable for the bump top layer 4c of the present invention. In the present embodiment, Ag (Shear Modulus = 30 GPa) is adopted as the most preferable material, and the thickness is limited to 1.0 μm or less at the maximum. When the thickness of the bump top layer 4c exceeds 1.0 μm, the load required for breaking increases in the process of press-fitting the convex metallic conductor bump 2, resulting in the operating characteristics of the semiconductor element. May have an effect. In the present embodiment, the bump top layer 4c was fabricated in a thickness range of 0.05 to 0.40 micrometers. This is because if the thickness of the bump top layer 4c is less than 0.05 micrometers, there is a tendency that the effect of preventing the oxidation of the metallic conductor bump 4 cannot be sufficiently obtained. If the bump top layer 4c produced with a film thickness in the range of 0.05 to 0.40 micrometers is used, there will be no particular problem with the rupture when the convex metallic conductor bumps 2 are press-fitted. Further, if the bump top layer 4c is thick, a fractured fragment that becomes a remnant of the bump top layer 4c may be generated near the interface between the metal conductor bump 2 and the metal conductor bump 4. In the form, since the film thickness is limited in the range of 0.05 to 0.40 micrometers, the generation of breakage fragments that become debris is negligible. In addition, a slightly broken piece reacts with In employed as the soft metal layer 4b to form an In—Ag eutectic (eutectic temperature of 141 ° C.) and diffuses into the soft metal layer 4b, so that the bump top layer The debris of 4c does not impair the bondability between the metallic conductor bump 2 and the metallic conductor bump 4. On the contrary, in this embodiment, by using the bump top layer 4c having an appropriate film thickness (0.05 to 0.40 micrometer), the fragments are the height of the conductor of the bump 2 and the inside of the conductor bump 4. Alloying with the conductor of the matching layer 4a, or promoting the alloying reaction between the conductor of the bump 2 and the conductor of the height matching layer 4a inside the conductor bump 4, thereby strengthening the bonding surface between the bump 2 and the bump 4. There was an effect.
　金属性導体バンプ４には、更に、その側壁部分に側壁部４ｄが形成されている。側壁部４ｄはアンダーフィル材５との接着性を確保するための層であり、アンダーフィル材５との接着性が維持できる最小の厚みで構わない。従って、金属層４ｂの材質によっては、敢えて積極的に成膜せずに軟性金属層４ｂの側壁に自然生成する自然酸化膜を活用しても構わない。本実施形態においては、軟性金属層４ｂに使用したＩｎの自然酸化によって生成した酸化インジウム膜を側壁部４ｄとした。酸化インジウム膜は空気中でＩｎの表面に速やかに生成して薄くて強固な皮膜となり、Ｉｎを化学的に安定化させる作用がある。本実施形態では金属性導体バンプ４の本体部分にはＩｎを使用しているので、上記のようにして自然に生成するＩｎの自然酸化膜を側壁部４ｄとして使用することは好適である。なお、本実施形態においては、バンプ４の本体部分である軟性金属層４ｂに用いたＩｎよりもイオン化しにくいＡｇ薄膜をバンプ頂部層４ｃに形成してあるので、それらの間に発現する局部電池作用によってＩｎの自然酸化膜ができやすい構成となっている。 The metal conductor bump 4 further has a side wall portion 4d formed on the side wall portion thereof. The side wall portion 4 d is a layer for ensuring adhesion with the underfill material 5, and may have a minimum thickness that can maintain adhesion with the underfill material 5. Therefore, depending on the material of the metal layer 4b, a natural oxide film that spontaneously forms on the side wall of the soft metal layer 4b may be used instead of actively forming a film. In the present embodiment, the sidewall portion 4d is an indium oxide film generated by natural oxidation of In used for the soft metal layer 4b. The indium oxide film is quickly formed on the surface of In in the air to form a thin and strong film, and has the effect of chemically stabilizing In. In the present embodiment, since In is used for the main body portion of the metallic conductor bump 4, it is preferable to use the natural oxide film of In naturally generated as described above as the side wall portion 4d. In the present embodiment, an Ag thin film that is less ionized than In used in the soft metal layer 4b that is the main body portion of the bump 4 is formed on the bump top layer 4c. The structure facilitates the formation of a natural oxide film of In.
　上記および図２に示した高さ整合層４ａ、軟性金属層４ｂ、頂部層４ｃ、側壁部４ｄの４種類の材質からなる金属性導体バンプ４へ凸形状金属性導体バンプ２が圧入されている状態を拡大した概略断面構造の一例を図３に示す。凸形状金属性導体バンプ２は高さ整合層４ａの上部に突き当った以上の深さには侵入しない。本実施形態では高さ整合層４ａの厚みは金属性導体バンプ４に対して約５０％、軟性金属層４ｂの厚みは金属性導体バンプ４全体の膜厚に対して約４８％、頂部層４ｃの厚みは高さ整合層４ａと軟性金属層４ｂの合計厚みに対して約２％とした。また、凸形状金属性導体バンプ２の厚みは軟性金属層４ｂよりも若干厚めとし、本実施形態では金属性導体バンプ４に対して約５０％の厚みとした。高さ整合層４ａ、軟性金属層４ｂ、凸形状金属性導体バンプ２のそれぞれの厚みに関して必ずしも本実施形態の数値にこだわる必要はないが、最も好ましい構成比の１例である。本願発明においては、凸形状金属性導体バンプ２の厚みは軟性金属層４ｂの膜厚と同等以上とし、かつ、金属性導体バンプ４全体の膜厚に対して１０～９５％の範囲とすることが望ましい。凸形状金属性導体バンプ２の厚みが金属性導体バンプ４全体の膜厚に対して１０％未満の場合には、必然的に軟性金属層４ｂも薄くせざるを得ず、その結果として、凸形状金属性導体バンプ２と金属性導体バンプ４との接合界面が小さくなって接合信頼性が不足する懸念が高まる。逆に、凸形状金属性導体バンプ２の厚みが金属性導体バンプ４全体の膜厚に対して９５％を超える場合には、必然的に軟性金属層４ｂが金属性導体バンプ４全体に占める割合が大きくなって、言い換えると高さ整合層４ａの占める割合が小さくなるので、半導体素子基板１と半導体素子基板３との間のギャップ制御性が低下する傾向が高まる。 The convex metal conductor bumps 2 are press-fitted into the metal conductor bumps 4 made of four kinds of materials, that is, the height matching layer 4a, the soft metal layer 4b, the top layer 4c, and the side wall 4d shown in FIG. An example of a schematic cross-sectional structure in which the state is enlarged is shown in FIG. The convex metallic conductor bumps 2 do not penetrate deeper than they hit the top of the height matching layer 4a. In this embodiment, the thickness of the height matching layer 4a is about 50% with respect to the metallic conductor bump 4, the thickness of the soft metal layer 4b is about 48% with respect to the entire thickness of the metallic conductor bump 4, and the top layer 4c. Was about 2% of the total thickness of the height matching layer 4a and the soft metal layer 4b. Further, the thickness of the convex metallic conductor bump 2 is slightly thicker than that of the soft metal layer 4b, and is about 50% of the thickness of the metallic conductor bump 4 in this embodiment. Although it is not always necessary to stick to the numerical values of the present embodiment with respect to the thicknesses of the height matching layer 4a, the soft metal layer 4b, and the convex metallic conductor bumps 2, it is an example of the most preferable configuration ratio. In the present invention, the thickness of the convex metallic conductor bump 2 should be equal to or greater than the thickness of the soft metal layer 4b, and be in the range of 10 to 95% with respect to the total thickness of the metallic conductor bump 4. Is desirable. If the thickness of the convex metal conductor bump 2 is less than 10% of the total thickness of the metal conductor bump 4, the soft metal layer 4b must be thinned as a result. There is a growing concern that the bonding interface between the shape metallic conductor bump 2 and the metallic conductor bump 4 becomes small and the bonding reliability is insufficient. On the contrary, when the thickness of the convex metallic conductor bump 2 exceeds 95% with respect to the entire thickness of the metallic conductor bump 4, the ratio of the soft metal layer 4 b to the entire metallic conductor bump 4 inevitably. Is increased, in other words, the proportion of the height matching layer 4a is decreased, and therefore, the tendency for the gap controllability between the semiconductor element substrate 1 and the semiconductor element substrate 3 to decrease is increased.
　次に、凸形状金属性導体バンプ２について説明する。図３に例示されている通り、凸形状金属性導体バンプ２は先端が尖った形状となっていて、その小径側の先端が凸形状金属性導体バンプ４の表面に形成された頂部層４ｃを貫通して軟性金属層４ｂに圧入され、高さ整合層４ａに突き当たった状態で接合されている。一方、凸形状金属性導体バンプ２の大径側の先端は、図３では省略されているが、第１の半導体素子基板の表面に繋がっている。 Next, the convex metallic conductor bump 2 will be described. As illustrated in FIG. 3, the convex metallic conductor bump 2 has a pointed tip, and the tip on the small diameter side is a top layer 4 c formed on the surface of the convex metallic conductor bump 4. It penetrates, is press-fitted into the soft metal layer 4b, and is joined in a state of abutting against the height matching layer 4a. On the other hand, the tip on the large-diameter side of the convex metallic conductor bump 2 is connected to the surface of the first semiconductor element substrate, which is omitted in FIG.
　本願発明では、凸形状金属性導体バンプ２の大径側の先端径を凸形状金属性導体バンプ２の厚み（高さ）より大きくすることが望ましい。より具体的に例示すれば、凸形状金属性導体バンプ２の大径側の先端径は凸形状金属性導体バンプ２の厚み（高さ）に対して約２００％程度あるいはそれ以上あることが望ましい。このような径／厚み比とすることによって、簡略な製造工程を採用でき、従って低コスト化が出来るからである。本実施形態においては、凸形状金属性導体バンプ２の大径側の先端径を１０マイクロメートル、凸形状金属性導体バンプ２の厚み（高さ）を４．８マイクロメートルとした。凸形状金属性導体バンプ２の大径側と小径側の径の比は、言い換えると、凸形状金属性導体バンプ２の先端の尖り具合をあらわす数値である。凸形状金属性導体バンプ４の表面に形成された頂部層４ｃを低荷重で貫通させるためには、凸形状金属性導体バンプ２の先端が尖っていることが望ましいが、本願発明では金属性導体バンプ４の頂部層４ｃおよびバンプ４内部の軟性金属層４ｂの膜厚や材質に制限を設けた特定の仕様を採用しているので、導体バンプ２の先端が極端に尖っている必要はない。本実施形態の導体バンプ２は、その軸は半導体表面に略垂直であり、その先端付近の外表面が半導体表面に対して平行となる面との間で為す角８が約３５～５５度の範囲となるように作られている。５５度を越えて過剰に尖っていると製造工程途中でバンプ先端が座屈するなどの不具合が発生する危険性が高まるし、逆に、３５度に満たない鈍角では凸形状金属性導体バンプ４の表面に形成された頂部層４ｃの貫通および軟性金属層４ｂへの圧入工程で大きな荷重が必要になるという傾向が高まる。なお、上記角度にするのは、厳密に先端ではなく先端付近であればよく、バンプ４の先端を含む微小な領域を半導体素子基板に平行な平坦形状や丸みを帯びた形状にしてもよい。 In the present invention, it is desirable to make the tip diameter on the large diameter side of the convex metallic conductor bump 2 larger than the thickness (height) of the convex metallic conductor bump 2. More specifically, the tip diameter on the large diameter side of the convex metallic conductor bump 2 is desirably about 200% or more with respect to the thickness (height) of the convex metallic conductor bump 2. . This is because, by setting such a diameter / thickness ratio, a simple manufacturing process can be adopted, and the cost can be reduced. In this embodiment, the tip diameter on the large diameter side of the convex metallic conductor bump 2 is 10 micrometers, and the thickness (height) of the convex metallic conductor bump 2 is 4.8 micrometers. In other words, the ratio of the diameter of the large-diameter side to the small-diameter side of the convex-shaped metallic conductor bump 2 is a numerical value that represents the sharpness of the tip of the convex-shaped metallic conductor bump 2. In order to penetrate the top layer 4c formed on the surface of the convex metallic conductor bump 4 with a low load, it is desirable that the tip of the convex metallic conductor bump 2 is pointed. Since specific specifications are employed in which the film thickness and material of the top layer 4c of the bump 4 and the soft metal layer 4b inside the bump 4 are limited, the tip of the conductor bump 2 does not need to be extremely sharp. The conductor bump 2 of the present embodiment has an axis substantially perpendicular to the semiconductor surface, and an angle 8 formed between the outer surface near the tip and a plane parallel to the semiconductor surface is about 35 to 55 degrees. It is made to be a range. If it is excessively sharp beyond 55 degrees, there is a higher risk of problems such as buckling of the bump tip during the manufacturing process. Conversely, at an obtuse angle of less than 35 degrees, the convex metallic conductor bump 4 There is a tendency that a large load is required in the penetration process of the top layer 4c formed on the surface and the press-fitting process into the soft metal layer 4b. The angle is not limited to the tip but strictly near the tip, and a minute region including the tip of the bump 4 may be a flat shape or a rounded shape parallel to the semiconductor element substrate.
　本願発明の凸形状金属性導体バンプ２は、上述の通り、凸形状金属性導体バンプ４内部の軟性金属層４ｂへ圧入するので、軟性金属層４ｂと比べて高硬度な材料であって、例えば、圧入工程において座屈などが起こらないことが必要である。このような観点から、本願発明においては凸形状金属性導体バンプ２にはシェア強度（Ｓｈｅａｒ　Ｍｏｄｕｌｕｓ）２５ＧＰａ以上の金属導体を選択することが望ましい。より具体的には、Ａｕ、Ａｇ、Ｃｕ、Ｎｉ、ＮｉＣｕ合金、ＣｕＳｎ合金（スペキュラム合金）、Ｔｉなどである。本実施形態においては、軟性金属層４ｂのＩｎ材への圧入容易性の観点に加えて、フォトリソグラフィを用いた高精度な加工が容易、良導電性、安価、などの観点を考慮して、銅（４８ＧＰａ）を採用した。なお、シェア強度１００ＧＰaを越える材料の場合、高精度加工の困難さに加えて、バンプ製造過程でバンプ内部に発生する内部応力が大きくなり易いため、本願発明の金属性導体バンプ２としては必ずしも適切な材料とは言えないので、適用する前に事前の評価が必要である。 Since the convex metallic conductor bump 2 of the present invention is press-fitted into the soft metal layer 4b inside the convex metallic conductor bump 4 as described above, the material is higher in hardness than the soft metal layer 4b. It is necessary that buckling does not occur in the press-fitting process. From such a viewpoint, in the present invention, it is desirable to select a metal conductor having a shear strength of 25 GPa or more for the convex metallic conductor bump 2. More specifically, Au, Ag, Cu, Ni, NiCu alloy, CuSn alloy (speculum alloy), Ti, and the like. In the present embodiment, in addition to the viewpoint of ease of press-fitting the soft metal layer 4b into the In material, high-precision processing using photolithography is easy, considering good conductivity, low cost, etc. Copper (48 GPa) was employed. In addition, in the case of a material having a shear strength of over 100 GPa, in addition to difficulty in high-precision processing, internal stress generated inside the bump tends to increase during the bump manufacturing process, so that it is not always suitable as the metallic conductor bump 2 of the present invention. Since it is not a good material, prior evaluation is required before application.
　一方、金属性導体バンプ２の先端が突き当たる凸形状金属性導体バンプ４内部の高さ整合層４ａとしては、金属性導体バンプ２の先端が突き当たったことによって容易に変形したり、座屈したりなどが起こらないことが望ましい。検討の結果、本願発明の構造では、金属性導体バンプ２よりもモース硬度が０．５以上大きい導体であれば、このような問題が発生する危険性を抑制できることがわかった。つまり、本願発明では高さ整合層４ａの材質には、金属性導体バンプ２よりモース硬度が０．５以上大きい導体から選定することが望ましい。本実施形態においては銅膜（モース硬度３．０）よりもモース硬度が１．０大きいニッケル膜（モース硬度４．０）を採用した。なお、ニッケル膜はその製造方法によって硬度を制御できる場合があり、硬度の制御範囲が広いめっき法を用いて高さ整合層４ａを作製した（高さ整合層４ａの製造方法の詳細は後述）。めっき法を用いて皮膜硬度を制御する方法を具体的に挙げると、レベラーあるいはブライトナーと呼ばれる添加剤をめっき液に添加してめっき皮膜表面の凹凸を抑制して平滑面となるようにすれば良い。レベラーあるいはブライトナーと呼ばれる添加剤が添加されためっき液を用いてニッケルめっきを行うと、析出した皮膜は微細な結晶粒の集合体となっており、従って硬い皮膜となるのである。 On the other hand, the height matching layer 4a in the convex metallic conductor bump 4 with which the tip of the metallic conductor bump 2 abuts can be easily deformed or buckled due to the abutting of the tip of the metallic conductor bump 2. It is desirable that this does not occur. As a result of the study, it has been found that, in the structure of the present invention, if the conductor has a Mohs hardness of 0.5 or more higher than that of the metallic conductor bump 2, the risk of occurrence of such a problem can be suppressed. In other words, in the present invention, the material of the height matching layer 4a is preferably selected from a conductor having a Mohs hardness of 0.5 or more higher than that of the metallic conductor bump 2. In this embodiment, a nickel film (Mohs hardness 4.0) having a Mohs hardness 1.0 larger than the copper film (Mohs hardness 3.0) is employed. In some cases, the hardness of the nickel film can be controlled by its manufacturing method, and the height matching layer 4a was produced using a plating method having a wide hardness control range (details of the manufacturing method of the height matching layer 4a will be described later). . Specifically, a method for controlling the film hardness using a plating method is as follows: an additive called a leveler or brightener is added to the plating solution to suppress unevenness on the surface of the plating film so that a smooth surface is obtained. good. When nickel plating is performed using a plating solution to which an additive called a leveler or brightener is added, the deposited film becomes an aggregate of fine crystal grains, and thus becomes a hard film.
　上述のように、本願発明では導体バンプ２の材質、導体バンプ４の内部構造および各構成層の材質および厚み、硬度、形状を細かく規定したことにより、低温低荷重での確実な接合を実現できる。これにより、1、000本を超えるバンプを一括接合することが可能となり、また、本願実施形態の仕様にてSiCやGaNなどの脆性破壊耐性が小さい半導体チップを積層接合したところ、チップ破壊なしで接合できた。 As described above, according to the present invention, the material of the conductor bump 2, the internal structure of the conductor bump 4, and the material, thickness, hardness, and shape of each constituent layer are finely defined, so that reliable bonding at low temperature and low load can be realized. . As a result, more than 1,000 bumps can be bonded together, and when semiconductor chips with low brittle fracture resistance such as SiC and GaN are laminated and bonded according to the specifications of the present embodiment, there is no chip destruction. We were able to join.
　次に図４～図６に基づいて製造方法の詳細を説明する。 Next, the details of the manufacturing method will be described with reference to FIGS.
　図４は第1の半導体素子基板１に導体バンプ２を作製するための製造方法を説明するための断面概略構造を示す図である。図４（ａ）は本実施例で使用した第1の半導体素子基板１の断面構造を示す概略図である。ここでは詳細構造が省略されているが、第1の半導体素子基板１には少なくとも１個以上の半導体回路が形成され、第1の半導体素子基板１の第1の面には各半導体回路の外部出力端子６が設けられている。 FIG. 4 is a diagram showing a schematic cross-sectional structure for explaining a manufacturing method for producing the conductor bump 2 on the first semiconductor element substrate 1. FIG. 4A is a schematic diagram showing a cross-sectional structure of the first semiconductor element substrate 1 used in this example. Although the detailed structure is omitted here, at least one semiconductor circuit is formed on the first semiconductor element substrate 1, and the first surface of the first semiconductor element substrate 1 is external to each semiconductor circuit. An output terminal 6 is provided.
　まず始めにこの外部出力端子６を完全に覆うように均一膜厚にて第1の均一膜厚導体層７を形成する（図４（ｂ））。この図はあくまでも概略図であるため、第1の均一膜厚導体層７の詳細な層構成を記載していないが、製造工程上の都合で第1の均一膜厚導体層７が多層膜であっても構わない。本実施形態においては、均一膜厚導体層７はＣｒとＣｕの2種類の材料からなる2層膜を採用し、膜厚均一性を確保するために2層いずれもスパッタ法を用いて連続成膜した。本実施形態では第1の半導体素子基板１と第1の均一膜厚導体層７とを確実に密着させるために７５ナノメートル厚のＣｒ膜を使用したが、他の材質、例えばＴｉやＷなどの密着膜で代用しても良い。本実施形態では４．８マイクロメートル厚の金属性導体バンプ２を確保するために、第1の均一膜厚導体層７のＣｕ膜は４．９マイクロメートル厚となるように成膜した。 First, a first uniform thickness conductor layer 7 is formed with a uniform thickness so as to completely cover the external output terminal 6 (FIG. 4B). Since this figure is only a schematic diagram, the detailed layer structure of the first uniform-thickness conductor layer 7 is not described, but the first uniform-thickness conductor layer 7 is a multilayer film for convenience of the manufacturing process. It does not matter. In the present embodiment, the uniform-thickness conductor layer 7 employs a two-layer film made of two kinds of materials, Cr and Cu, and in order to ensure film thickness uniformity, both layers are continuously formed using a sputtering method. Filmed. In this embodiment, a Cr film having a thickness of 75 nanometers is used in order to ensure that the first semiconductor element substrate 1 and the first uniform thickness conductor layer 7 are in close contact with each other. However, other materials such as Ti and W are used. Alternatively, an adhesive film may be used instead. In this embodiment, in order to secure the metallic conductor bump 2 having a thickness of 4.8 micrometers, the Cu film of the first uniform thickness conductor layer 7 is formed so as to have a thickness of 4.9 micrometers.
　次に、上記第1の均一膜厚導体層７の所望位置を選択的にエッチング除去することによって導体バンプ２を有する第1の半導体素子基板１を作製する（図４（ｃ））。本実施形態では、均一膜厚導体層７の所望位置を選択的にエッチング除去するために、均一膜厚導体層７の表面に感光性レジストを成膜し、露光現像によって選択除去すべき所望箇所のエッチングレジストを除去した後に、残った部分のレジストをエッチングマスクとして均一膜厚導体層７を溶解するエッチング液で処理した。本願発明に好適な感光性のエッチングレジストは、所望の形状および解像度が得られる材料であれば良いので特殊な材料を使用する必要は無いが、膜厚１０マイクロメートル以下の膜厚で成膜できるレジストであることが望ましい。膜厚が１０マイクロメートルを越えると、レジスト開口幅の大小や開口部の粗密がエッチング形状やエッチング形状の膜厚均一性に影響する危険性が高まるからである。本実施形態においては、膜厚２．３マイクロメートルのポジ型ドライフィルムレジストを用い、４．９マイクロメートル厚のＣｕ膜を除去するために硫酸-過酸化水素混合系のエッチング液を用いた。エッチング処理においては上部（レジストに密着している側）のエッチングは、下部（基板に密着している側）のエッチングよりも進み方が早い、いわゆるサイドエッチング現象が生じて先端が尖ったバンプが自発的に形成される。本実施形態においては、基板面内で均一なエッチング反応が進むように十分に注意を払ってエッチング処理したところ、面内で均一な傾斜角８を有するバンプ２が形成できた。本実施形態ではこの後、バンプ２をパターン分離するためにアルカリ性Ｃｒエッチング液にてバンプ２間に残っているＣｒ膜をエッチング除去し、最後にレジストを剥離することによって、先端が尖った導体バンプ２が所望箇所に形成された第1の半導体素子基板１を作製できた。なお、図４はあくまでも概略構造図なので省略されているが、導体バンプ２と半導体素子基板１との境界部には７５ナノメートル厚のＣｒ膜が残存していることは改めて指摘するまでも無い。また、先端が尖った導体バンプ２の接合性低下の原因となる表面酸化を抑制するために、導体バンプ２の表面に酸化防止膜を成膜しても良い。本実施形態においては、導体バンプ２が精密に制御された形状の微細円錐形状のＣｕであることに着目して、簡便かつ低コストに成膜でき、かつ、接合性に影響を与えず、また、表面のすべり性のよい酸化防止膜となるＳｎめっき皮膜を置換めっき法にて形成した。表面のすべり性が良好で低コストな酸化防止膜であればＳｎ以外の皮膜でも構わない。有機性の酸化防止皮膜、例えばプリフラックスやいわゆるＯＳＰ（Ｏｒｇａｎｉｃ　Ｓｏｌｄｅｒａｂｉｌｉｔｙ　Ｐｒｅｓｅｒｖａｔｉｖｅ）は、酸化防止作用は良好であるが表面すべり性の観点で不十分であるため、本願発明への適用はあまり好ましくはない。 Next, the first semiconductor element substrate 1 having the conductor bumps 2 is produced by selectively etching away the desired position of the first uniform thickness conductor layer 7 (FIG. 4C). In the present embodiment, a photosensitive resist is formed on the surface of the uniform-thickness conductor layer 7 in order to selectively remove the desired position of the uniform-thickness conductor layer 7, and a desired portion to be selectively removed by exposure and development. After the etching resist was removed, the remaining portion of the resist was used as an etching mask and treated with an etching solution for dissolving the uniform-thickness conductor layer 7. The photosensitive etching resist suitable for the present invention may be a material that can obtain a desired shape and resolution, so that it is not necessary to use a special material, but it can be formed with a film thickness of 10 micrometers or less. A resist is desirable. This is because when the film thickness exceeds 10 micrometers, the risk that the size of the resist opening width and the density of the opening affect the etching shape and the film thickness uniformity of the etching shape increases. In the present embodiment, a positive dry film resist having a film thickness of 2.3 μm is used, and an etching solution of a sulfuric acid-hydrogen peroxide mixture system is used to remove the Cu film having a thickness of 4.9 μm. In the etching process, the etching on the upper side (the side in close contact with the resist) proceeds faster than the etching on the lower side (the side in close contact with the substrate). Formed spontaneously. In the present embodiment, when the etching process was performed with sufficient care so that a uniform etching reaction progressed in the substrate surface, the bump 2 having a uniform inclination angle 8 in the surface could be formed. In this embodiment, thereafter, in order to pattern-separate the bump 2, the remaining Cr film between the bumps 2 is removed by etching with an alkaline Cr etching solution, and finally the resist is peeled off, whereby the conductor bumps having sharp points are formed. Thus, the first semiconductor element substrate 1 in which 2 was formed at a desired location could be produced. Note that FIG. 4 is omitted because it is a schematic structural diagram, but it is needless to point out that a 75 nm thick Cr film remains at the boundary between the conductor bump 2 and the semiconductor element substrate 1. . Further, an antioxidant film may be formed on the surface of the conductor bump 2 in order to suppress surface oxidation that causes a decrease in the bonding property of the conductor bump 2 having a sharp tip. In this embodiment, paying attention to the fact that the conductor bump 2 is a precisely controlled fine-cone-shaped Cu, it is possible to form a film simply and at low cost, without affecting the bonding property, and An Sn plating film serving as an antioxidant film having a good surface slip was formed by a displacement plating method. A film other than Sn may be used as long as the anti-slip film has good surface slipperiness and low cost. Organic anti-oxidation coatings such as preflux and so-called OSP (Organic Solderability Preservative) have a good anti-oxidation effect but are insufficient in terms of surface slipping, and are therefore not preferred for application to the present invention. .
　このように本実施形態においては、先端が尖った形状のバンプ２を湿式エッチング法で作製することによって均一形状のバンプ２の低コストな製造を可能にし、バンプ２の形状布不均一性に起因する接合歩留低下を抑制できた。このような歩留低下抑制は、後述する多段積層構造体においては、製造歩留、製造コスト、品質の観点で特段の効果を発揮する。 As described above, in the present embodiment, the bump 2 having a sharp tip shape is manufactured by a wet etching method, so that the bump 2 having a uniform shape can be manufactured at low cost, and the shape cloth of the bump 2 is caused by nonuniformity. It was possible to suppress the decrease in bonding yield. Such yield reduction suppression exhibits a special effect in terms of manufacturing yield, manufacturing cost, and quality in the multi-layer laminated structure described later.
　図５は第２の半導体素子基板３に導体バンプ４を作製するための製造方法を説明するための断面概略構造を示す図であり、図５（ａ）は本実施例で使用した第２の半導体素子基板３の断面構造を示す概略図である。ここでは詳細構造が省略されているが、第２の半導体素子基板３には少なくとも１個以上の半導体回路が形成され、第２の半導体素子基板３の第1の面には各半導体回路の外部出力端子９が設けられている。図４に示した第1の半導体素子基板１の場合と同様、この外部出力端子９を完全に覆い隠すように均一膜厚にて第2の均一膜厚導体層１０を形成する（図５（ｂ））。この図はあくまでも概略図であるため、第２の均一膜厚導体層１０の詳細な層構成を記載していないが、製造工程上の都合で第２の均一膜厚導体層１０が多層膜であっても構わない。本実施形態においては、均一膜厚導体層１０としてＣｒとＣｕの2種類の材料からなる多層構造を採用し、膜厚均一性を確保するためにスパッタ法にて連続成膜した。本実施形態では、第２の均一膜厚導体層１０は第２の半導体素子基板３の第1の面にバンプ４を作製するために使用するめっき下地のための導体膜となるので、めっき工程に要求される密着性と電流密度分布を確保できる膜厚があれば十分である。本実施形態においては、密着膜としては上記第1の半導体素子基板の場合と同様、７５ナノメートル厚のＣｒ膜を使用し、導体膜としては５００ナノメートル厚のＣｕ膜とした。 FIG. 5 is a diagram showing a schematic cross-sectional structure for explaining a manufacturing method for producing the conductor bump 4 on the second semiconductor element substrate 3, and FIG. 5 (a) shows the second structure used in this embodiment. 2 is a schematic view showing a cross-sectional structure of a semiconductor element substrate 3. FIG. Although the detailed structure is omitted here, at least one semiconductor circuit is formed on the second semiconductor element substrate 3, and the first surface of the second semiconductor element substrate 3 is external to each semiconductor circuit. An output terminal 9 is provided. As in the case of the first semiconductor element substrate 1 shown in FIG. 4, the second uniform-thickness conductor layer 10 is formed with a uniform thickness so as to completely cover the external output terminal 9 (FIG. 5 ( b)). Since this figure is only a schematic diagram, the detailed layer configuration of the second uniform-thickness conductor layer 10 is not described, but the second uniform-thickness conductor layer 10 is a multilayer film for convenience of the manufacturing process. It does not matter. In the present embodiment, a multilayer structure composed of two kinds of materials, Cr and Cu, is employed as the uniform-thickness conductor layer 10, and continuous film formation is performed by a sputtering method in order to ensure film thickness uniformity. In the present embodiment, the second uniform-thickness conductor layer 10 is a conductor film for the plating base used to produce the bumps 4 on the first surface of the second semiconductor element substrate 3, so that the plating step It is sufficient to have a film thickness that can ensure the adhesion and current density distribution required for the above. In this embodiment, as in the case of the first semiconductor element substrate, a 75 nm thick Cr film was used as the adhesion film, and a 500 nm thick Cu film was used as the conductor film.
　次に、上記第２の均一膜厚導体層１０の所望位置に導体バンプ４を作成する（図５（ｃ））。本実施形態では、均一膜厚導体層１０の所望位置を選択的にバンプ４となる導体構造を選択的に成長させるために、均一膜厚導体層１０の表面に感光性レジストを成膜する。この感光性レジストに対して所定の露光現像処理を施して所望箇所のレジストを除去した後に、残った部分のレジストをめっきレジストマスクとしてバンプ４となる導体をめっき成長させる。 Next, a conductor bump 4 is formed at a desired position of the second uniform film thickness conductor layer 10 (FIG. 5C). In the present embodiment, a photosensitive resist is formed on the surface of the uniform-thickness conductor layer 10 in order to selectively grow a conductor structure that selectively becomes bumps 4 at desired positions of the uniform-thickness conductor layer 10. A predetermined exposure and development process is performed on the photosensitive resist to remove the resist at a desired portion, and then a conductor to be the bump 4 is grown by plating using the remaining portion of the resist as a plating resist mask.
　上述の通り、第2の半導体素子基板３上に設けられた金属性導体バンプ４は、少なくとも３種類以上の材質からなる複合構造体を使用する。このような複雑な構造体を最小コスト、最短工程で作製するために、本実施形態では高さ整合層４ａ、軟性金属層４ｂ、頂部層４ｃの３層連続めっき技術を適用し、約４マイクロメートル厚の高さ整合層４ａ、約３．８マイクロメートル厚の軟性金属層４ｂ、０．０５～０．４０マイクロメートル厚の頂部層４ｃという構成とした。 As described above, the metallic conductor bump 4 provided on the second semiconductor element substrate 3 uses a composite structure made of at least three kinds of materials. In order to manufacture such a complex structure with the minimum cost and the shortest process, in this embodiment, a three-layer continuous plating technique of the height matching layer 4a, the soft metal layer 4b, and the top layer 4c is applied, and about 4 micron is applied. The height matching layer 4a has a metric thickness, the soft metal layer 4b has a thickness of about 3.8 micrometers, and the top layer 4c has a thickness of 0.05 to 0.40 micrometers.
　本願発明に好適な感光性のめっきレジストは、所望の形状および解像度が得られる材料であれば良いので特殊な材料を使用する必要は無いが、膜厚１０マイクロメートル以上の膜厚で２０マイクロメートル程度の解像度が得られるレジストであることが望ましく、本実施形態ではそのようなレジストを少なくとも膜厚１０マイクロメートルを越える膜厚で成膜して使用する。膜厚が１０マイクロメートルを下回ると上述の高さ整合層４ａ（膜厚４マイクロメートル）、軟性金属層４ｂ（膜厚３．８マイクロメートル）、頂部層４ｃ（膜厚０．０５～０．４０マイクロメートル）の３層連続めっきへの適用が困難となるからである。本実施形態においては、膜厚１４．８マイクロメートルのネガ型ドライフィルムレジストを用い、膜厚４マイクロメートルの高さ整合層４ａにはスルファミン酸ニッケルめっき、膜厚３．８マイクロメートルの軟性金属層４ｂには硫酸インジウム系酸性インジウムめっき、頂部層４ｃにはフラッシュ銀めっきを適用した。所定の３層連続めっき処理を施した後、レジスト除去、パターン分離を行うことによって、３層構造を有する導体バンプ４が所望箇所に形成された第２の半導体素子基板３を作製できた。なお、本実施形態においては、パターン分離工程で５００ナノメートル厚のＣｕ導体膜および７５ナノメートル厚のＣｒ膜をエッチング除去する際には、酸性エッチング液を使用せず、必ずアルカリ性のエッチング液とすることが肝要であった。酸性エッチング液を使用すると軟性金属層４ｂへのダメージが生じるためである。なお、図５はあくまでも概略構造図なので省略されているが、導体バンプ４と半導体素子基板３との境界部には、５００ナノメートル厚のＣｕ導体膜および７５ナノメートル厚のＣｒ膜が残存していることは改めて指摘するまでも無い。 The photosensitive plating resist suitable for the present invention may be any material that can obtain a desired shape and resolution, so that it is not necessary to use a special material, but a film thickness of 10 micrometers or more is 20 micrometers. It is desirable that the resist has a resolution of a certain degree. In this embodiment, such a resist is used by forming a film with a film thickness exceeding 10 μm. When the film thickness is less than 10 micrometers, the above-described height matching layer 4a (film thickness 4 micrometers), soft metal layer 4b (film thickness 3.8 micrometers), and top layer 4c (film thickness 0.05-0. This is because it becomes difficult to apply to 40-micrometer) three-layer continuous plating. In the present embodiment, a negative dry film resist having a thickness of 14.8 micrometers is used, and the height matching layer 4a having a thickness of 4 micrometers is plated with nickel sulfamate and a soft metal having a thickness of 3.8 micrometers. Indium sulfate-based acidic indium plating was applied to the layer 4b, and flash silver plating was applied to the top layer 4c. After performing a predetermined three-layer continuous plating process, resist removal and pattern separation were performed, whereby the second semiconductor element substrate 3 in which the conductor bumps 4 having a three-layer structure were formed at desired locations could be produced. In this embodiment, when etching and removing the 500 nanometer-thick Cu conductor film and the 75 nanometer-thick Cr film in the pattern separation step, an acidic etchant is not used, and an alkaline etchant is always used. It was important to do. This is because use of an acidic etching solution causes damage to the soft metal layer 4b. Note that FIG. 5 is omitted because it is a schematic structural diagram, but a 500 nm thick Cu conductor film and a 75 nm thick Cr film remain at the boundary between the conductor bump 4 and the semiconductor element substrate 3. There is no need to point it out again.
　図６は、図４を用いて説明した製造方法に基づいて作製したバンプ付き半導体素子基板１と、図５を用いて説明した製造方法に基づいて作製したバンプつき半導体素子基板３とを、接合する工程を説明するための概略断面構造図である。 FIG. 6 shows a bonding of the bumped semiconductor element substrate 1 manufactured based on the manufacturing method described with reference to FIG. 4 and the bumped semiconductor element substrate 3 manufactured based on the manufacturing method described using FIG. It is a schematic sectional drawing for demonstrating the process to do.
　まず始めに、第1のバンプ付き半導体素子基板１と第2のバンプつき半導体素子基板３を上下の相対する位置に配置し、さらに、互いのバンプ位置を整合させる（図６（ａ））。 First, the semiconductor element substrate 1 with the first bump and the semiconductor element substrate 3 with the second bump are arranged at the upper and lower opposing positions, and the bump positions are aligned with each other (FIG. 6A).
　次の工程で、第1のバンプ付き半導体素子基板１と第2のバンプ付き半導体素子基板３とを相対的に移動することによって、第1のバンプ付き半導体素子基板１上に設けられたバンプ２を第2のバンプ付き半導体素子基板３上に設けられたバンプ４に圧入させる。第1の半導体素子基板１を固定しておいて第2の半導体素子基板３を移動しても構わないが、本実施形態においては、下側に固定設置されている第2のバンプ付き半導体素子基板３に対して、上側に配置した第1の半導体素子基板１を移動させることによって、第1の半導体素子基板１の表面に設けられている先端の尖った導体バンプ２が、第2のバンプ付き半導体素子基板３の表面に設けられている軟性金属層を有する導体バンプ４に圧入するように仕向けた。また、本実施形態においては、第1の半導体素子基板１を上側に、第2の半導体素子基板３を下側となるように配置した時点で、第1の半導体素子基板１と第2の半導体素子基板３の間のギャップ部分に充填させるべきアンダーフィル材５の所定量を量り採り、該所定量のアンダーフィル材５を第2の半導体素子基板３の上に載せ、しかる後に、第1の半導体素子基板１を移動して圧入接合するという工程を採用した。アンダーフィル材５は、第1の半導体素子基板１と第2の半導体素子基板３とを圧入接合して一体となった後に、半導体素子基板間のギャップが毛管となる毛管現象を使って充填する、いわゆるキャピラリー充填しても良いが、本願発明者の検討によると、第2の半導体素子基板３に先に載せてから圧入接合するという手順を取ったほうがボイド発生率が低減しやすい傾向があった。本実施形態においては、この検討結果を考慮して、圧入接合工程に先立ってアンダーフィルを載せる工程を採用した。 In the next step, the bump 2 provided on the first bumped semiconductor element substrate 1 is moved by relatively moving the first bumped semiconductor element substrate 1 and the second bumped semiconductor element substrate 3. Is press-fitted into the bumps 4 provided on the second bumped semiconductor element substrate 3. Although the first semiconductor element substrate 1 may be fixed and the second semiconductor element substrate 3 may be moved, in the present embodiment, the second bumped semiconductor element fixedly installed on the lower side By moving the first semiconductor element substrate 1 arranged on the upper side with respect to the substrate 3, the conductor bumps 2 with sharp tips provided on the surface of the first semiconductor element substrate 1 are changed into the second bumps. It was intended to press fit into the conductor bump 4 having a soft metal layer provided on the surface of the attached semiconductor element substrate 3. In the present embodiment, the first semiconductor element substrate 1 and the second semiconductor are disposed when the first semiconductor element substrate 1 is disposed on the upper side and the second semiconductor element substrate 3 is disposed on the lower side. A predetermined amount of the underfill material 5 to be filled in the gap portion between the element substrates 3 is weighed, the predetermined amount of the underfill material 5 is placed on the second semiconductor element substrate 3, and then the first A process of moving the semiconductor element substrate 1 and press-fitting it was adopted. After the first semiconductor element substrate 1 and the second semiconductor element substrate 3 are integrally joined by press-fitting, the underfill material 5 is filled using a capillary phenomenon in which the gap between the semiconductor element substrates becomes a capillary. So-called capillary filling may be used, but according to the study of the present inventor, the void generation rate tends to be reduced when the procedure of press-fitting and joining the second semiconductor element substrate 3 first is performed. It was. In the present embodiment, in consideration of this examination result, a process of placing an underfill prior to the press-fit joining process is adopted.
　なお、第1の半導体素子基板１の表面に形成した先端部の尖った導体バンプ２の高さは、前記第2の半導体素子基板３の表面に形成してある軟性金属層を内包する導体バンプ４の高さよりも低めが望ましく、先端が尖ったバンプ２の高さは、軟性金属層内包バンプ４の全体高さに対して10～95％の範囲に入っていることが望ましい。このように先端の尖ったバンプ２の高さを軟性金属層内包バンプ４の高さより低くすることにより、第2の半導体素子基板３の半導体素子へのダメージを最小限に抑制できる。 The height of the conductive bump 2 having a sharp tip formed on the surface of the first semiconductor element substrate 1 is the conductor bump containing the soft metal layer formed on the surface of the second semiconductor element substrate 3. The height of the bump 2 having a sharp tip is desirably in the range of 10 to 95% with respect to the total height of the soft metal layer-containing bump 4. Thus, the damage to the semiconductor element of the second semiconductor element substrate 3 can be minimized by making the height of the bump 2 with the sharp tip lower than the height of the soft metal layer inclusion bump 4.
　図４～図６を用いて説明したような工程を用いることにより、本願発明では少なくとも２個以上の半導体チップを積層接合してなるチップ積層構造体を実現できた。 By using the processes as described with reference to FIGS. 4 to 6, the present invention has realized a chip laminated structure in which at least two semiconductor chips are laminated and joined.
　図７は本願発明にかかる半導体装置の別の1実施形態を説明するための概略図であり、表裏両面にバンプを有する第3の半導体素子基板１２を多段積層してパッケージ基板１１上に実装した半導体装置の構造概略断面を示している。なお、この構造では積層最上段となる半導体素子基板には片面のみにバンプが形成されていれば良いので、本実施形態では上記実施例１において先の尖ったバンプ２を形成した第1の半導体素子基板１を流用した。 FIG. 7 is a schematic diagram for explaining another embodiment of the semiconductor device according to the present invention. A third semiconductor element substrate 12 having bumps on both the front and back surfaces is stacked in multiple stages and mounted on the package substrate 11. 1 shows a schematic cross-section of the structure of a semiconductor device. In this structure, since it is sufficient that bumps are formed on only one side of the semiconductor element substrate which is the uppermost layer of the stack, in this embodiment, the first semiconductor in which the sharp bumps 2 are formed in the above-described Example 1. The element substrate 1 was diverted.
　本実施形態の第3の半導体素子基板１２は、上述の実施例１に記載したバンプ２およびバンプ４の製造方法を応用して作製する。詳細な説明は省略するが、まず、先端が尖った形状となっているバンプ２を半導体素子基板１２の第1の面に形成し、その第1の面の全面にめっきレジストを成膜し、しかる後に、半導体素子基板１２の第2の面に軟性金属層を内包するバンプ４を形成するという工程によって作製できる。なお、本実施形態では、第1の面の全面に成膜されるめっきレジスト材料は、第２の面のバンプ形成のためのめっきレジスト材料とは異なる材料を使用することによって、製造工程途中での不具合発生を抑制している。 The third semiconductor element substrate 12 of the present embodiment is manufactured by applying the bump 2 and bump 4 manufacturing method described in Example 1 above. Although a detailed description is omitted, first, the bump 2 having a sharp tip is formed on the first surface of the semiconductor element substrate 12, and a plating resist is formed on the entire first surface. Thereafter, the bumps 4 including the soft metal layer can be formed on the second surface of the semiconductor element substrate 12. In the present embodiment, the plating resist material formed on the entire surface of the first surface is different from the plating resist material for forming the bumps on the second surface. The occurrence of problems is suppressed.
　本実施形態で使用する半導体素子基板１２には、その表裏に形成されたバンプ間の電気的な接続を確保するための配線が形成されている（図示せず）。電気的な接続を確保するための配線として具体的に一例を挙げれば、半導体素子基板１２を板厚方向に貫通する貫通孔配線が挙げられる。本実施形態では、半導体素子基板１２の側壁面に形成した微細配線を用いて表裏を電気的に接続した。必要配線本数が比較的少ない場合は、貫通孔配線を使って表裏接続するよりも側壁配線を使って接続する構造をとることによって製造コストを削減できる。 The semiconductor element substrate 12 used in the present embodiment is formed with wiring for ensuring electrical connection between the bumps formed on the front and back surfaces (not shown). A specific example of the wiring for ensuring electrical connection is a through-hole wiring that penetrates the semiconductor element substrate 12 in the plate thickness direction. In this embodiment, the front and back surfaces are electrically connected using fine wiring formed on the side wall surface of the semiconductor element substrate 12. When the required number of wirings is relatively small, the manufacturing cost can be reduced by adopting a structure in which the side wall wiring is used for the connection rather than the front / back connection using the through hole wiring.
　１・・・第1の半導体素子基板
　２・・・第1の半導体素子基板上に形成した第1の凸形状金属性導体バンプ
　３・・・第２の半導体素子基板
　４・・・第２の半導体素子基板上に形成した第２の凸形状金属性導体バンプ
　４ａ・・・第２の凸形状金属性導体バンプの部分構造の１つ
　４ｂ・・・第２の凸形状金属性導体バンプの別の部分構造の１つ
　４ｃ・・・第２の凸形状金属性導体バンプの更に別の部分構造の１つ
　４ｄ・・・第２の凸形状金属性導体バンプの更に別の部分構造の１つ
　５・・・アンダーフィル材
　６・・・第1の半導体素子基板上の半導体チップの外部出力端子
　７・・・第1の半導体素子基板上に形成した均一膜厚導体層
　８・・・バンプ２の傾斜角
　９・・・第２の半導体素子基板上の半導体チップの外部出力端子
　１０・・・第２の半導体素子基板上に形成した均一膜厚導体層
　１１・・・パッケージ基板
　１２・・・第3の半導体素子基板。 DESCRIPTION OF SYMBOLS 1 ... 1st semiconductor element substrate 2 ... 1st convex-shaped metallic conductor bump formed on 1st semiconductor element substrate 3 ... 2nd semiconductor element substrate 4 ... 2nd Second convex metallic conductor bump 4a formed on the semiconductor element substrate 4a ... One of the partial structures of the second convex metallic conductor bump 4b ... Different from the second convex metallic conductor bump 4c: One of the other partial structures of the second convex metallic conductor bump 4d: One of the other partial structures of the second convex metallic conductor bump 5... Underfill material 6... External output terminal of semiconductor chip on first semiconductor element substrate 7... Uniform film thickness conductor layer formed on first semiconductor element substrate 8. Of the semiconductor chip on the second semiconductor element substrate 10... Second half Uniform thickness conductive layer 11 ... package substrate 12 ... third semiconductor element substrate formed in the body element substrate.

Claims (17)

  1. 　第1の半導体素子基板と、
    　第2の半導体素子基板とを備え、
    　前記第１の半導体素子基板と、第２の半導体素子基板とを接合してなる半導体装置であって、
    　前記第1の半導体素子基板は、その表面に形成した金属性導体の第1のバンプを有し、
    　前記第2の半導体素子基板は、その表面に形成した金属性導体の第2のバンプを有し、
    　前記第2のバンプの本体部は軟性金属層であって、
    　前記第1のバンプが、前記第2のバンプの本体部である軟性金属層に圧入された構造であることを特徴とする半導体装置。     A first semiconductor element substrate;
    A second semiconductor element substrate,
    A semiconductor device formed by bonding the first semiconductor element substrate and the second semiconductor element substrate,
    The first semiconductor element substrate has a first bump of a metallic conductor formed on the surface thereof,
    The second semiconductor element substrate has a second bump of a metallic conductor formed on the surface thereof,
    The main body of the second bump is a soft metal layer,
    The semiconductor device, wherein the first bump has a structure pressed into a soft metal layer which is a main body of the second bump.
  2. 　請求項１において、
    　前記第２のバンプの軟性金属層は、ブリュネル硬度が５０ＭＰａ以下であることを特徴とする半導体装置。     In claim 1,
    The soft metal layer of the second bump has a Brunel hardness of 50 MPa or less.
  3. 　請求項２において、
    　前記第２のバンプの軟性金属層は、Ｉｎ層であることを特徴とする半導体装置。     In claim 2,
    The semiconductor device according to claim 1, wherein the soft metal layer of the second bump is an In layer.
  4. 　請求項１において、
    　前記軟性金属層の頂部に酸化防止膜を備え、
    　前記酸化防止膜を備えた領域から、前記第１のバンプが前記第２のバンプに圧入されていることを特徴とする半導体装置。     In claim 1,
    Provided with an antioxidant film on top of the soft metal layer,
    The semiconductor device, wherein the first bump is press-fitted into the second bump from a region having the antioxidant film.
  5. 　請求項３において、
    　前記Ｉｎ層の頂部にAg膜を備え、
    　前記Ag膜を備えた領域から、前記第１のバンプが前記第２のバンプに圧入されていることを特徴とする半導体装置。     In claim 3,
    An Ag film is provided on the top of the In layer,
    A semiconductor device, wherein the first bump is press-fitted into the second bump from a region having the Ag film.
  6. 　請求項４または請求項５において、
    　前記第２のバンプの表面であり、前記酸化防止膜または前記Ａｇ膜を設けていない位置に、前記軟性金属層の酸化膜を備え、
    　前記第１の半導体素子基板と前記第２の半導体素子基板との間であり、前記酸化膜に接する位置に、樹脂を備えたことを特徴とする半導体装置。     In claim 4 or claim 5,
    The surface of the second bump is provided with an oxide film of the soft metal layer at a position where the antioxidant film or the Ag film is not provided,
    A semiconductor device comprising resin at a position between the first semiconductor element substrate and the second semiconductor element substrate and in contact with the oxide film.
  7. 　請求項６において、
    　前記樹脂は、アンダーフィルであることを特徴とする半導体装置。     In claim 6,
    The semiconductor device, wherein the resin is underfill.
  8. 　請求項１において、
    　前記第1のバンプの高さは、前記第2のバンプの高さの10%以上95%以下の範囲であることを特徴とする半導体装置。     In claim 1,
    The semiconductor device according to claim 1, wherein a height of the first bump is in a range of 10% to 95% of a height of the second bump.
  9. 　請求項１において、
    　前記第１のバンプは、シェア硬度が５０ＭＰａ以上であることを特徴とする半導体装置。     In claim 1,
    The semiconductor device, wherein the first bump has a shear hardness of 50 MPa or more.
  10. 　請求項９において、
    　前記第１のバンプは、Ｃｕを主成分とすることを特徴とする半導体装置。     In claim 9,
    The semiconductor device, wherein the first bump has Cu as a main component.
  11. 　請求項１において、
    　前記第１のバンプは、先端付近の外表面が前記半導体基板の面と形成する角度が３５～５５度であることを特徴とする半導体装置。     In claim 1,
    The semiconductor device according to claim 1, wherein the first bump has an angle of 35 to 55 degrees with the outer surface near the tip and the surface of the semiconductor substrate.
  12. 　基板と、
    　前記基板の一主面に形成された第１のバンプと、
    　前記一主面の反対の面に形成された第２のバンプとを備え、
    　前記第１のバンプは、シェア硬度が５０ＭＰａ以上であり、
    　前記第２のバンプは、ブリュネル硬度が５０ＭＰａ以下の軟性金属であることを特徴とする半導体素子基板。     A substrate,
    A first bump formed on one main surface of the substrate;
    A second bump formed on a surface opposite to the one main surface,
    The first bump has a shear hardness of 50 MPa or more,
    The second bump is a soft metal substrate having a Brunel hardness of 50 MPa or less.
  13. 　請求項１２において、
    　前記第一のバンプの主成分はＣｕであり、
    　前記第２のバンプの主成分はＩｎであることを特徴とする半導体素子基板。     In claim 12,
    The main component of the first bump is Cu,
    A semiconductor element substrate, wherein the main component of the second bump is In.
  14. 　第１の半導体素子基板の備えた第１のバンプを、第２の半導体素子基板の備えた第２のバンプに、常温で圧入する工程を有し、
    　前記第２のバンプは、軟性金属であることを特徴とする半導体装置の製造方法。     A step of press-fitting the first bump provided on the first semiconductor element substrate into the second bump provided on the second semiconductor element substrate at room temperature;
    The method of manufacturing a semiconductor device, wherein the second bump is made of a soft metal.
  15. 　請求項１４において、
    　前記第１の半導体素子基板上に、前記第１のバンプを形成する工程と、
    　前記第２の半導体素子基板上に、前記第２のバンプを形成する工程とを有し、
    　前記第２のバンプを形成する工程は、
    　前記第２のバンプ本体を形成する工程と、
    　前記第２のバンプ本体上に、酸化防止膜を形成する工程と、
    　前記酸化防止膜を形成後、前記第２のバンプの表面を酸化させる工程とを有することを特徴とする半導体装置の製造方法。     In claim 14,
    Forming the first bump on the first semiconductor element substrate;
    Forming the second bump on the second semiconductor element substrate,
    The step of forming the second bump includes
    Forming the second bump body;
    Forming an antioxidant film on the second bump body;
    And a step of oxidizing the surface of the second bump after the formation of the antioxidant film.
  16. 　請求項１５において、
    　前記圧入する工程では、前記第１のバンプを前記酸化防止膜を通じて前記第２のバンプに圧入することを特徴とする半導体装置の製造方法。     In claim 15,
    In the press-fitting step, the first bump is press-fitted into the second bump through the antioxidant film.
  17. 　請求項１６において、
    　前記圧入する工程の後に、前記第１の半導体素子基板と前記第２の半導体素子基板との間であり、前記第２のバンプの酸化した表面に接する位置に、アンダーフィルを形成する工程を有することを特徴とする半導体装置の製造方法。     In claim 16,
    After the press-fitting step, there is a step of forming an underfill between the first semiconductor element substrate and the second semiconductor element substrate at a position in contact with the oxidized surface of the second bump. A method for manufacturing a semiconductor device.
PCT/JP2010/003580 2009-06-10 2010-05-28 Semiconductor device and fabricating method therefor WO2010143369A1 (en)

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FR2971081B1 (en) * 2011-02-02 2013-01-25 Commissariat Energie Atomique METHOD FOR MANUFACTURING TWO SUBSTRATES CONNECTED BY AT LEAST ONE MECHANICAL AND ELECTRICALLY CONDUCTIVE CONNECTION OBTAINED

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JP2001320012A (en) * 2000-05-08 2001-11-16 Rohm Co Ltd Semiconductor device
JP2006261264A (en) * 2005-03-16 2006-09-28 Oki Electric Ind Co Ltd Chip laminating method and manufacturing method of semiconductor device using the same method

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JPH025540A (en) * 1988-06-24 1990-01-10 Nec Corp Formation of bonding of bump electrode
JP2001320012A (en) * 2000-05-08 2001-11-16 Rohm Co Ltd Semiconductor device
JP2006261264A (en) * 2005-03-16 2006-09-28 Oki Electric Ind Co Ltd Chip laminating method and manufacturing method of semiconductor device using the same method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012253110A (en) * 2011-06-01 2012-12-20 Sumitomo Bakelite Co Ltd Semiconductor device and method for manufacturing the same

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