JP4086771B2 - Bump electrode, bump electrode manufacturing method, and bump electrode connection structure - Google Patents

Description

  The present invention relates to a method of flip-chip mounting a semiconductor device or the like, and more particularly to a bump electrode, a manufacturing method thereof, and a bump electrode connection structure.

  A semiconductor device such as an LSI chip is formed by arranging hundreds to thousands of bump electrodes on a chip surface at a fine pitch in response to demands for miniaturization, high integration, and high speed. A flip chip connection method for mounting on a wiring board has been developed. At this time, as a method of forming a large number of bump electrodes on the chip surface, a method of directly forming on the chip surface or a bump electrode manufactured in advance on another substrate and transferring the bump electrode onto a desired chip A forming method or the like is used.

  Patent Document 1 discloses a conventional example of a semiconductor device formed by bonding pyramidal projection electrodes onto pad electrodes arranged on a semiconductor chip. FIG. 7 is a diagram for explaining an outline of a method of manufacturing a pyramidal projection electrode (corresponding to a bump electrode in this specification) such as a quadrangular pyramid disclosed in Patent Document 1. Hereinafter, with reference to FIG. 7, an outline of the method for manufacturing the protruding electrode disclosed in Patent Document 1 will be described.

  First, a specific crystal orientation surface in which a silicon dioxide film 131 is formed on both surfaces of a silicon base material 132 having a <100> plane crystal orientation by thermal oxidation to a thickness of about 0.5 μm, and the silicon dioxide oxide film 131 is applied to the surface. A silicon wafer substrate having Next, as shown in FIG. 7A, a thermal oxide film 131 is processed on the silicon substrate into a pattern reverse to the pad electrode 103 of the semiconductor chip 102 by photolithography. Next, as shown in FIG. 7B, the silicon substrate is anisotropically etched using an alkaline etchant using the thermal oxide film 131 on the silicon substrate as a mask, and a quadrangular pyramid surrounded by <111> planes. The etching hole (square pyramid shape) 136 is formed on the silicon substrate. That is, on the silicon substrate, a quadrangular pyramid etching hole (quadrangular pyramid shape) 136 surrounded by the <111> plane is formed by anisotropic etching. Next, the thermal oxide film on the silicon substrate is removed, and a silicon dioxide film is newly formed on the <111> plane of the silicon substrate by thermal oxidation in wet oxygen to a thickness of about 0.5 μm. Then, as shown in FIG. 7C, a multilayer metal film composed of a plating power supply film (Cr film) 135 and a plating power supply film (Ni film) 134 is formed on the silicon substrate surface, and further has a quadrangular pyramid. A pattern 133 made of an organic material for forming a plating film to be a tip metal of the concave pattern is formed. Next, as shown in FIG. 7 (d), an opening of the pattern 33 made of an organic material is filled with a plating film 6 such as hard Ni or soft Cu by electroplating. Subsequently, the substrate after each of the above steps is washed, and then, as shown in FIG. 7E, the Sn plating film 111 is applied only to the hard Ni plating film 106. Thereafter, as shown in FIG. 7F, the pattern 133 made of an organic material is stripped using a resist stripping solution. Thus, the protruding electrode 105 having a pyramid shape such as a quadrangular pyramid is formed.

  Next, a method of connecting the pad electrode 103 of the semiconductor chip 102 and the quadrangular pyramid-shaped protruding electrode 105 formed on the silicon wafer base surface will be described. That is, the surface of the contact hole on the semiconductor chip side (pad electrode 103 of the semiconductor chip 102) is generally made of alloy aluminum. Therefore, as shown in FIG. 7G, an electroless nickel plating film 113 is applied to the surface of the contact hole (pad electrode 103) by a plating technique. Subsequently, a gold plating film 114 is applied. That is, the surface of the pad electrode 103 of the semiconductor chip 102 is modified to a surface made of nickel / gold. After that, as shown in FIG. 7 (h), a large number of pad electrodes 103 of a non-defective semiconductor chip 102 and a large number of pyramidal projection electrodes 105 such as a quadrangular pyramid formed on the silicon substrate surface are connected to each other. After alignment, thermocompression bonding is performed, and when the temperature is set to 230 ° C. or higher, the tin plating film 111 is melted, reacts with the gold plating film 114 to form an alloy of gold and tin, and is bonded and bonded. Thereafter, the chromium film 135 of the lowermost layer in contact with the silicon substrate surface among the multilayer metal films 135 and 134 that are plating power supply films on the silicon substrate surface on which the concave pattern having a quadrangular pyramid is formed does not attack other metals. By dissolving and removing with a selective etching solution, the pyramidal projection electrodes 5 are separated and transferred from the silicon substrate surface to the semiconductor chip. Subsequently, after cleaning, a gold plating film 108 is formed on the surface of the separated pyramidal protruding electrode (convex pattern) 105 as shown in FIG.

JP-A-11-97471 (FIGS. 7-9, p.6)

In the prior art in which a bump electrode is formed in advance on a silicon substrate or the like and connected / transferred to a desired pad electrode or the like of a semiconductor chip, for example, the bump electrode has a sharp tip like the protruding electrode of Patent Document 1 described above. It is common to form in a pyramid shape. However, when the tip of the bump electrode has a sharp shape such as a pyramid shape, the following problem may occur.
(1) When mounting an electronic device having such a bump electrode, such as a semiconductor chip, on a wiring board or package, etc., by connecting the mounting electrode such as the wiring board or package and the bump electrode by thermocompression bonding, In order to obtain bonding strength, it is necessary to make the bonding area between the bump electrode and the mounting electrode as large as possible. However, if the tip of the bump electrode is sharp, the amount of crushing must be increased, and the method of crushing is inefficient. If it is uniform, the bump electrode shape after bonding becomes non-uniform, which adversely affects reliability.
(2) In order to increase the amount of crushing, for example, in the example of Patent Document 1, the amount of Au used to increase the thickness of the gold plating film 8 must be increased, resulting in high costs.
(3) When bonding a mounting electrode such as a wiring board or package and a bump electrode with a conductive adhesive, it is necessary to transfer the conductive adhesive to the tip of the bump electrode. It is difficult to control the amount of the conductive adhesive transferred to the film, and it is necessary to increase the amount of the conductive adhesive to ensure the bonding strength. As the above-mentioned conductive adhesive, it is preferable to use a conductive adhesive (hereinafter referred to as a fine particle paste) containing fine particles having a particle diameter of about several nm to 100 nm, for example.

  The present invention has been made in view of the above problems, and when mounting an electronic device including a bump electrode on a wiring board, a package, or the like by performing flip chip connection between the bump electrode and the mounting electrode, The flip chip connection can be performed with low load and stress, and the bump electrode shape after connection is optimized, the gap between the electronic device and the wiring board, package, etc. is optimized, the yield and reliability of the flip chip connection It is an object of the present invention to provide a bump electrode, a manufacturing method thereof, and a bump electrode connection structure that can improve the performance.

In order to solve the above problems, the bump electrode of the present invention has a first surface and a second surface, and the second surface is connected to a conductive layer of a predetermined first substrate,
A first connection layer made of a first conductive material, and a core portion made of a second conductive material, the first connection layer being at least partially covered;
The first surface is formed in the first connection layer and has a flat portion, and the flat portion is at a position farthest from the first substrate. In other words, the bump electrode of the present invention has a first surface and a second surface facing each other, and the second surface is connected to a conductive layer of a predetermined first substrate,
A first connection layer made of a first conductive material, and a core portion made of a second conductive material, the core portion having a portion covered with the first connection layer;
The first surface is formed in the first connection layer and has a flat portion.

  At this time, the hardness of the second conductive material is preferably higher than the hardness of the first conductive material, and the surface in contact with the second surface and the first surface are parallel to each other. desirable.

The bump electrode manufacturing method of the present invention includes a pit forming step of providing a reverse trapezoidal pit having a bottom area smaller than an opening area on a silicon substrate,
Depositing a first conductive material in the pit to form a first connection layer; depositing a second conductive material on the first connection layer to form a core; and Depositing a third conductive material on the portion to form a second connection layer, wherein the first connection layer is formed in direct contact with the silicon substrate.

  At this time, the bottom surface area may be 10% or more and 60% or less of the opening area. Further, the silicon substrate preferably has a specific resistance of 1 Ω · cm or less, and the hardness of the second conductive material is preferably higher than the hardness of the first conductive material.

  The bump connection structure of the present invention is a bump electrode connection structure in which a first substrate having a plurality of bump electrodes according to the present invention described above is mounted on a second substrate via the bump electrodes, The substrate of 2 has mounting electrodes corresponding to the respective positions of the bump electrodes, and the mounting electrodes and the corresponding bump electrodes are connected using a conductive adhesive or a low melting point metal brazing material, or The connection is made by thermocompression bonding.

  According to the present invention, the first surface, which is the tip of the bump electrode connected to the conductive layer of the first substrate, includes the flat portion substantially parallel to the surface of the first substrate, and the area of the flat portion. If it is designed appropriately, the bonding area with the mounting electrodes such as the wiring substrate and the package as the second substrate can be widened and the bonding strength can be ensured while suppressing the crushing amount of the bump electrode. Moreover, since the amount of bump electrode crushing can be suppressed, variations in the shape of the bump electrode after bonding can be reduced, and the amount of Au to be used can be further reduced.

  In addition, when the mounting electrode such as the wiring board or the package and the bump electrode are joined with a conductive adhesive such as a fine particle paste, since the first surface has a flat portion, the area of the flat portion is reduced. If properly designed, the surface tension of the conductive adhesive can be used to accurately transfer the conductive adhesive only to the flat part to uniformly control the conductive adhesive amount of each bump electrode. Therefore, bonding can be performed with a high yield.

  In addition, there is no need to deposit or remove the power supply film for plating on the Si template for manufacturing the bump electrode, and the Si template can be used repeatedly with only a simple cleaning process. can get.

Next, embodiments of the present invention will be described with reference to the drawings.
In the following description, as an example of the first substrate and its conductive layer, a semiconductor chip (hereinafter referred to as an LSI chip) 20 and a pad electrode 21 formed on the LSI chip 20 are used, and the second substrate and its mounting. As an example of the electrode for use, description will be made using the wiring board 30 on which the LSI chip 20 is mounted and the mounting electrode 31 formed on the wiring board 30.

  1A and 1B are diagrams for explaining an embodiment of a bump electrode of the present invention, in which FIG. 1A is a schematic perspective view of the bump electrode 1, and FIG. 1B is taken along line AA ′ of FIG. (C) is a schematic cross-sectional view of a state in which the second surface 3 of the bump electrode 1 is bonded to the pad electrode 21 of the LSI chip 20, and (d) further illustrates the first surface 2. 3 is a schematic cross-sectional view of a state in which the wiring substrate 30 is bonded to a mounting electrode 31. FIG. Referring to FIG. 1, a bump electrode 1 of the present embodiment is formed by plating a first connection layer 4 formed by depositing, for example, gold, which is a first conductive material, and copper, which is a second conductive material, for example. And a second connection layer 6 formed by depositing, for example, gold, which is a third conductive material, by plating. Then, when the second surface 3 of the surface of the second connection layer 6 is connected to the pad electrode 21 of the LSI chip 20, a portion of the bump electrode 1 farthest from the surface of the LSI chip 20, that is, the tip portion 7 has a first surface 2 in which the surface shape of the first connection layer 4 is flat. Further, the first surface 2 is substantially parallel to the surface of the LSI chip 20. The side surface region of the bump electrode 1 between the first surface 2 and the second surface 3 is substantially covered with a gold plating film formed simultaneously with the first connection layer 4.

  In the present embodiment, the bump electrode 1 and the pad electrode 21 are connected by thermocompression bonding. In addition, a conductive adhesive 40 such as a fine particle paste is used for connection between the first surface 2 of the bump electrode 1 and the mounting electrode 31 formed on the wiring substrate 30.

  As described above, the bump electrode 1 of the present embodiment has a configuration in which the first connection layer 4 and the second connection layer 6 are formed of gold and the intermediate core portion 5 is formed of hard copper. Further, the first surface 2 which is the surface of the first connection layer 4 made of gold is a flat portion, and when the second surface 3 is connected to the pad electrode 21 of the LSI chip 20, the LSI chip 20 When the LSI chip 20 in which the bump electrode 1 is connected to the pad electrode 21 in advance is mounted on the wiring board 30, the thermocompression bonding technique is performed. Even when a weight is applied to the bump electrode 1 by using, for example, the core portion 5 made of copper harder than the gold of the first connection layer 4 is not easily crushed, the gap between the LSI chip 20 and the wiring board 30 is appropriately set. Kept. In addition, when the first surface 2 and the mounting electrode 31 are connected using a conductive adhesive 40 such as a fine particle paste, the first surface 2 is a flat portion, and thus the area of the flat portion. Is appropriately designed, the surface tension of the conductive adhesive 40 is used to accurately transfer the conductive adhesive 40 only to the flat portion, and the coating amount of the conductive adhesive 40 on each bump electrode 1. Can be controlled uniformly, and connection can be performed with a high yield.

Next, an outline of a method for manufacturing the bump electrode 1 of the above embodiment will be described.
In the bump electrode 1 of the above embodiment, a desired inverted pyramid shaped pit is formed on a low resistance Si substrate (the conductivity type may be either p or n), and a predetermined conductive material is plated in the pit, for example It is formed by depositing. 2 and 3 are diagrams for explaining a method of manufacturing the bump electrode 1. FIG. 2A is a plan view showing a state in which pits having a surface opening 53 and a bottom 54 are formed on a low-resistance Si substrate 51. FIGS. 2 (b) to 2 (e) and FIGS. 3 (a) and 3 (b) are cross-sectional views for each process showing a cross section taken along the line PP 'in FIG. 2 (a) in the main process. .

  First, for example, a low-resistance Si substrate 51 made of a Si single crystal having a plane orientation <100> and having a specific resistance of 1 Ω · cm or less is prepared, and the surface of the low-resistance Si substrate 51 is oxidized to form an oxide film 52. The oxide film 52 is opened, for example, in a square having a side length of Wa to form a surface opening 53. Further, the oxide film 52 is used as an etching mask and the surface opening 53 is made of low resistance Si with potassium hydroxide (KOH). The substrate 51 is anisotropically etched (FIG. 2B). At this time, the etching time is adjusted so that the etching depth D of the low-resistance Si substrate 51 satisfies 0.163 ≦ (D / Wa) ≦ 0.48. As a result, the bottom 54 of the pit becomes a square flat part having a side length Wb, and 0.32 ≦ (Wb / Wa) ≦ 0.77. Therefore, the ratio R = (S1 / S2)) of the area S2 of the bottom 54 to the area S1 of the opening 53 satisfies 0.1 ≦ R ≦ 0.6. The pit formation position on the low resistance Si substrate 51 is determined so as to correspond to the pad electrode 21 of the LSI chip 20. Specifically, patterning may be performed using, for example, a pad opening mask that exposes the pad electrode 21 by opening the protective insulating film 23 or, more preferably, a mask in which the opening of the pad opening mask is slightly reduced. The low resistance Si substrate 51 on which desired pits are formed is hereinafter referred to as “Si template 50”.

  Next, after applying a photoresist (hereinafter referred to as PR) 60 to the Si template 50, the pits are opened, and gold is first formed to a thickness of about 2 to 3 μm by electrolytic plating to form a first connection. It is set as the layer 4 (FIG.2 (c)).

  Next, the core portion 5 is formed on the first connection layer 4 by depositing, for example, copper having a hardness higher than that of gold so that the pits are almost filled by electrolytic plating (FIG. 2D).

  Next, after depositing gold on the core portion 5 to a thickness of 2 to 3 μm by electrolytic plating to form the second connection layer 6 (FIG. 2E), the PR 60 is removed.

  The bump electrode 1 is formed in the pit at a predetermined position of the Si template 50 through the above steps. A portion in contact with the bottom 54 of the first connection layer 4 becomes the flat first surface 2. Moreover, the cross-sectional shape is a substantially trapezoid as shown in the figure.

  As described above, since the Si template 50 in which desired pits are formed at predetermined positions of the low-resistance Si substrate 51 is used for manufacturing the bump electrode 1 of the present embodiment, the first connection layer 4 and the core portion 5 are used. In the electroplating for forming the second connection layer 6, the plating current can be supplied from the low-resistance Si substrate 51. For example, a film forming process such as a plating supply film such as a Cr film in Patent Document 1 is not performed at all. It is unnecessary. Further, since the Si template 50 after the bump electrode 1 is transferred to the LSI chip 20 is returned to the initial state, it can be used any number of times with only a simple cleaning process, and the cost can be reduced. .

  Next, the pad electrode 21 of the LSI chip 20 is aligned with the bump electrode 1 formed in the pit of the Si template 50 (FIG. 3A), and the corresponding pad electrode 21 is, for example, thermocompression bonded to the bump electrode 1 By transferring 1 to the LSI chip 20, the LSI chip 20 having the bump electrodes 1 on each pad electrode 21 is completed. The pad electrode 21 is typically aluminum (Al), an Al-based alloy obtained by adding copper silicon to Al, a copper-based alloy, or a material obtained by performing surface treatment on these and depositing gold or the like.

  In the description of the present embodiment, the second surface 3 of the bump electrode 1 is shown flat for the sake of clarity, but normally, for example, as shown in FIG. In many cases, the recess 6c is formed in the center. In such a case, the tangential plane in contact with the surface of the second connection layer 6 may be the second surface 3.

  Since the bump electrode 1 of the present embodiment is directly formed in the pits of the Si template 50 as described above, if the transfer is performed at 300 ° C. or less at which gold and silicon are not alloyed, the first connection layer 4 and the pits are formed. The bump electrode 1 is easily transferred to the LSI chip 20 by peeling off from the inner silicon surface easily. As a result, a flat first surface 2 is obtained at the tip 7 of the bump electrode 1.

  Thus, in order to mount the LSI chip 20 having the bump electrodes 1 bonded to the pad electrodes 21 on the desired wiring board 30, for example, the flat first surface of the tip 7 of each bump electrode 1 is used. 2 by applying a conductive adhesive 40 such as a fine particle paste by transfer or the like (FIG. 5A), aligning with each mounting electrode 31 of the wiring board 30, and heating and curing the conductive adhesive 40. Then, the LSI chip 20 and the wiring board 30 are connected (FIG. 5B).

  When the LSI chip 20 having the bump electrode 1 bonded to the pad electrode 21 is mounted on the wiring substrate 30, the first surface 2 of the bump electrode 1 and the mounting electrode 31 are bonded to the conductive adhesive 40 such as a fine particle paste. Also in the case of using and connecting, the first surface 2 is a flat portion. Therefore, if the area of the flat portion is appropriately designed, the flat portion can be obtained by utilizing the surface tension of the conductive adhesive 40. Therefore, it is possible to transfer the conductive adhesive 40 with high accuracy and uniformly control the application amount of the conductive adhesive 40 on each bump electrode 1, so that the connection can be performed with a high yield.

  In addition, this invention is not limited to description of the said embodiment, A various change is possible within the range of the summary. For example, in the above embodiment, copper is used as the hard material for forming the core portion 5, but other nickel (Ni) or Ni can be used as long as the material is harder than the material for forming the first connection layer 4. An alloy, a copper alloy, or the like can also be used. In addition to electroplating, these layers may be electroless plating or vapor deposition, and the method is not particularly limited. Further, the example in which the first surface 2 of the bump electrode 1 and the mounting electrode 31 are connected by the conductive adhesive 40 when mounting the LSI chip 20 on the wiring substrate 30 has been described. If the surface treatment is performed to form gold, copper, tin (Sn) or the like, a thermocompression bonding connection, a connection using a gold-tin alloy, a connection using a low melting point solder such as solder, or the like may be used. Even when a weight is applied to the bump electrode 1, the core portion 5 made of a material harder than the material forming the first connection layer 4 is less likely to be crushed, so that the gap between the LSI chip 20 and the wiring substrate 30 can be maintained appropriately. It is.

  Furthermore, in the above-described embodiment, the example in which a material harder than the material for forming the first connection layer 4 is used for the core portion 5 has been described. However, when the LSI chip 20 is mounted on the wiring substrate 30, a fine particle paste or the like is used. When the conductive adhesive 40 is used and the weight applied to the bump electrode 1 can be kept sufficiently low, a material having the same hardness as the material forming the first connection layer 4 such as gold is used as the material forming the core portion 5. However, the distance between the LSI chip 20 and the wiring board 30 is kept uniform.

  In the above-described embodiment, the bump electrode 1 has been described as an example of a truncated pyramid shape. However, a shape in which a prism having the same shape as the surface opening 53 is further added to the second surface side may be used. FIG. 6 is a cross-sectional view for each process for explaining the bump electrode manufacturing method of this modification. The planar shape of the pits of the Si template 50a for manufacturing the bump electrode of this modification is the same as that shown in FIG. 2A, and the cross-sectional view of FIG. 6 is also taken along the line PP 'in FIG. The cross section of the position along is shown. In the Si template 50a for manufacturing the bump electrode of this modified example, after opening the surface opening 53 in the oxide film 52, the low resistance Si substrate 51 is further etched by a predetermined depth d by a dry etching technique or the like. The point that the opening 53a having the size of the surface opening 53 is formed in the low resistance Si substrate 51 is different from the case of the Si template 50. Thereafter, a modified bump electrode can be manufactured in the same manner as the bump electrode 1 using the Si template 50. Since the height of the bump electrode of this modification is (d + D), it can be easily controlled by adjusting d, and the second surface 2 is secured while ensuring the area of the first surface 2 (= area S2 of the bottom 54). This is effective for reducing the area of the surface 3 (= area S1 of the surface opening 53) or increasing the bump electrode.

  Furthermore, although the LSI chip 20 and the wiring board 30 have been described as examples of the first board and the second board, respectively, the first board is, for example, a BGA package chip mounting board, a printed wiring board, or a ceramic board. The second substrate may be a ceramic substrate, a printed wiring substrate, a film substrate, a lead frame, or a semiconductor chip. That is, when a plurality of semiconductor chips are stacked, both the first substrate and the second substrate are semiconductor chips.

It is a figure for demonstrating one Embodiment of the bump electrode of this invention, (a) is a typical perspective view of a bump electrode, (b) is sectional drawing along the AA 'line of (a), ( (c) is a schematic cross-sectional view of a state in which the second surface of the bump electrode is bonded to the pad electrode of the LSI chip, and (d) is a state in which the first surface is further bonded to the mounting electrode of the wiring board. FIG. It is a figure for demonstrating the manufacturing method of a bump electrode, (a) is a top view in the state in which the pit which has the surface opening part 53 and the bottom part 54 was formed in the low resistance Si substrate 51, (b) thru | or (e). It is sectional drawing for every process which shows the cross section of the position along the PP 'line of (a) in a main process. It is a figure for demonstrating the manufacturing method of the bump electrode 1, (a) And (b) is sectional drawing for every process which shows the cross section of the position along the PP 'line of Fig.2 (a) in a main process. . It is sectional drawing of one Embodiment of the bump electrode of this invention. It is a figure for demonstrating the connection method of a LSI chip and a wiring board. It is a figure for demonstrating the modification of the bump electrode of this invention. It is a figure for demonstrating the outline | summary of the manufacturing method of the pyramid-shaped projection electrode disclosed by Unexamined-Japanese-Patent No. 11-97471.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Bump electrode 2 1st surface 3 2nd surface 4 1st connection layer 5 Core part 6 2nd connection layer 6c Concave part 7 Tip part 20 LSI chip 21 Pad electrode 23 Protective insulating film 30 Wiring board 31 Electrode for mounting 40 Conductivity Adhesive 50, 50a Si template 51 Low resistance Si substrate 52 Oxide film 53 Surface opening 53a Opening 54 Bottom 60 PR

Claims (19)

A bump electrode having a first surface and a second surface, wherein the second surface is connected to a conductive layer of a predetermined first substrate,
A first connection layer made of a first conductive material, and a core portion made of a second conductive material, the first connection layer being at least partially covered;
The bump electrode, wherein the first surface is formed on the first connection layer and has a flat portion, and the flat portion is located at a position farthest from the first substrate.   The bump electrode according to claim 1, wherein the hardness of the second conductive material is higher than the hardness of the first conductive material.   The bump electrode according to claim 1, wherein the flat portion is parallel to a surface of the first substrate.   The bump electrode according to any one of claims 1 to 3, wherein a surface in contact with the second surface and the first surface are parallel to each other.   The bump electrode according to claim 1, wherein an area of the first surface is smaller than an area of the second surface.   The bump electrode according to any one of claims 1 to 5, wherein a cross-sectional shape when passing through the first surface and the second surface and cutting along a plane perpendicular to each of the first surface and the second surface is substantially trapezoidal.   The bump electrode according to any one of claims 1 to 6, wherein a thickness of the first connection layer is in a range of 0.05 µm or more and 5 µm or less.   A second connection layer made of a third conductive material is further provided, a part of the core portion is covered with the second connection layer, and the second surface is formed on a surface of the second connection layer. Item 8. The bump electrode according to any one of Items 1 to 7. A pit forming step of providing a reverse trapezoidal pit having a bottom surface area smaller than an opening area on a silicon substrate;
Depositing a first conductive material in the pit to form a first connection layer; depositing a second conductive material on the first connection layer to form a core; and And depositing a third conductive material on the portion to form a second connection layer, wherein the first connection layer is formed in direct contact with the silicon substrate. Production method.   The bump electrode manufacturing method according to claim 9, wherein the bottom surface area is in a range of 10% to 60% of the opening area.   11. The bump electrode manufacturing method according to claim 9, wherein the silicon substrate has a specific resistance of 1 Ω · cm or less.   The bump electrode manufacturing method according to claim 9, wherein the hardness of the second conductive material is higher than the hardness of the first conductive material.   A bump electrode connection structure in which a first substrate comprising a plurality of bump electrodes according to any one of claims 1 to 8 is mounted on a second substrate via the bump electrodes, wherein the second substrate Has a mounting electrode corresponding to each position of the bump electrode, and the bump electrode corresponding to the mounting electrode is connected with a conductive adhesive.   A bump electrode connection structure in which a first substrate comprising a plurality of bump electrodes according to any one of claims 1 to 8 is mounted on a second substrate via the bump electrodes, wherein the second substrate Has a mounting electrode corresponding to each position of the bump electrode, and the bump electrode corresponding to the mounting electrode is connected by a low melting point metal brazing material.   A bump electrode connection structure in which a first substrate comprising a plurality of bump electrodes according to any one of claims 1 to 8 is mounted on a second substrate via the bump electrodes, wherein the second substrate Has a mounting electrode corresponding to each position of the bump electrode, and the bump electrode corresponding to the mounting electrode is connected by thermocompression bonding.   The bump electrode connection structure according to claim 13, wherein the first substrate is a semiconductor substrate.   The bump electrode connection structure according to claim 13, wherein the first substrate is a wiring substrate.   18. The bump electrode connection structure according to claim 13, wherein the second substrate is selected from a group including a semiconductor substrate, a resin substrate, and a ceramic substrate. The bump electrode connection structure according to claim 13, wherein the second substrate is a part of a semiconductor device.

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