JP2013004770A - Method for etching nitride semiconductor layer and method for manufacturing nitride semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for etching a nitride semiconductor layer in which no high-resistance damage layer is formed, and to provide a method for manufacturing a nitride semiconductor device having a low-resistance ohmic electrode using the same.SOLUTION: There is provided a method for etching a nitride semiconductor layer comprising the steps of: (a) injecting an impurity ion into a nitride semiconductor layer and forming an impurity region to a prescribed depth from the surface; heat-treating the impurity region; and (c) removing a prescribed region on a surface side of the impurity region by wet etching.

Description

  The present invention relates to a method for etching a nitride semiconductor layer and a method for manufacturing a heterojunction field effect transistor (hereinafter referred to as a heterojunction FET) using the same.

  A heterojunction FET made of a semiconductor containing nitride has a problem that the contact resistance of the source / drain electrodes is large.

  As a method for reducing the contact resistance, for example, Patent Document 1 discloses a method of performing an activation heat treatment by ion-implanting an n-type impurity into a semiconductor layer under the source / drain electrodes.

  Non-Patent Document 1 shows that the contact resistance is reduced by recess etching the region where the source / drain electrode is formed. In Patent Document 2, the source / drain electrode has a recess structure. The structure in which an n-type dopant is implanted under the source / drain electrodes is shown.

JP 2006-134935 A Japanese Patent No. 4120899

D. Buttari et al., Systematic Characterization of Cl2 Reactive Ion Etching for Improved Ohmics in AlGaN / GaN HEMTs, IEEE Electron Device Letters, vol.23, No.2, Februray 2002.

  However, according to the ion implantation method, a high resistance damage layer is formed in the semiconductor layer in the high energy ion implantation step, and the contact resistance cannot be reduced.

  In addition, when the source / drain electrode has a recess structure, nitride semiconductor materials such as GaN have high chemical stability and are difficult to wet-etch. Therefore, in general, dry etching using plasma is used to form a recess under the source / drain electrode. Etching is performed. However, in the dry etching method, a highly resistant damage layer is formed in the semiconductor layer, and the contact resistance cannot be reduced.

  Thus, it has been difficult to obtain a sufficiently low contact resistance by either method.

  SUMMARY OF THE INVENTION In view of the above-described problems, the present invention aims to provide a method for etching a nitride semiconductor layer that does not form a high-resistance damage layer, and a method for manufacturing a nitride semiconductor device that includes a low-resistance ohmic electrode using the same. To do.

  The method for etching a nitride semiconductor layer according to the present invention includes: (a) implanting impurity ions into the nitride semiconductor layer to form an impurity region from the surface to a predetermined depth; and (b) heat treating the impurity region. And (c) a step of removing a predetermined region on the surface side of the impurity region by wet etching.

  The method for manufacturing a nitride semiconductor device according to the present invention is a method for manufacturing a nitride semiconductor device using the method for etching a nitride semiconductor layer according to the present invention, and (a) etching the nitride semiconductor layer according to the present invention. Forming a nitride semiconductor layer having the impurity region from which a predetermined region on the surface side has been removed using a method; and (b) forming a source electrode and a drain electrode in the predetermined region.

  The method for etching a nitride semiconductor layer according to the present invention includes: (a) implanting impurity ions into the nitride semiconductor layer to form an impurity region from the surface to a predetermined depth; and (b) heat treating the impurity region. And (c) a step of removing a predetermined region on the surface side of the impurity region by wet etching, so that it can be formed as a low-resistance impurity region.

  Further, the method for manufacturing a nitride semiconductor device of the present invention includes: (a) using the nitride semiconductor layer etching method of the present invention, the nitride semiconductor layer having the impurity region from which the predetermined region on the surface side has been removed; And (b) forming a source electrode and a drain electrode in the predetermined region. Since the source electrode and the drain electrode are formed on the low-resistance impurity region, their contact resistance is reduced. Moreover, since the source electrode and the drain electrode are formed as recess electrodes, their contact resistance is reduced.

It is sectional drawing which shows the structure of the nitride semiconductor device which concerns on this invention. It is sectional drawing which shows the manufacturing process of the nitride semiconductor device which concerns on this invention. It is sectional drawing which shows the manufacturing process of the nitride semiconductor device which concerns on this invention. It is sectional drawing which shows the manufacturing process of the nitride semiconductor device which concerns on this invention. It is sectional drawing which shows the manufacturing process of the nitride semiconductor device which concerns on this invention. It is sectional drawing which shows the manufacturing process of the nitride semiconductor device which concerns on this invention. It is sectional drawing which shows the structure of the nitride semiconductor device which concerns on the modification of this invention. It is sectional drawing which shows the structure of the nitride semiconductor device which concerns on the modification of this invention. It is sectional drawing which shows the structure of the nitride semiconductor device which concerns on the modification of this invention. It is sectional drawing which shows the structure of the nitride semiconductor device which concerns on the modification of this invention. It is sectional drawing which shows the structure of the nitride semiconductor device which concerns on the modification of this invention.

(Embodiment 1)
<Configuration>
FIG. 1 is a cross-sectional view showing the structure of a heterojunction field effect transistor (hereinafter referred to as a heterojunction FET) which is an example of the nitride semiconductor device of the present invention.

  In this heterojunction FET, a buffer layer 20, a channel layer 30 that is an electron transit layer, and a barrier layer 40 that is an electron supply layer are sequentially formed as a nitride semiconductor layer on a semi-insulating substrate 10. In the recess structure continuously formed from the barrier layer 40 to the channel layer 30, a source electrode 70 and a drain electrode 80 are formed. Further, n-type impurity regions 60 are formed under the source electrode 70 and the drain electrode 80, respectively.

  A gate electrode 90 is formed on the barrier layer 40 between the source electrode 70 and the drain electrode 80. An element isolation region 50 is formed from the barrier layer 40 outside the transistor formation region to the channel layer 30.

  In this heterojunction FET, the n-type impurity region 60 is formed as a low resistance region, and the source / drain electrodes 70 and 80 are formed as recess electrodes, so that the contact resistance of the source / drain electrodes 70 and 80 is reduced. .

<Operation>
A manufacturing process of the heterojunction FET shown in FIG. 1 will be described with reference to FIGS.

  First, an epitaxial growth method such as MOCVD or MBE is applied on the SiC semi-insulating substrate 10 to epitaxially grow the buffer layer 20, the channel layer 30 made of GaN, and the barrier layer 40 made of AlGaN in order from the bottom.

  In the case of producing a GaN layer (channel layer 30) by MOCVD, trimethylgallium (TMG) as a gallium source gas and nitrogen source in addition to carrier gas hydrogen or nitrogen in an environment heated to 1000 ° C. or higher. Crystal growth is performed using ammonia as a gas. When an AlGaN layer (barrier layer 40) is formed by MOCVD, trimethylaluminum (TMA) is added as an aluminum source gas in addition to TMG and ammonia.

Subsequently, a surface protective layer 200 made of an oxide film or a nitride film is formed on the barrier layer 40. Then, a resist mask 210 is selectively formed on the surface protective layer 200, and, for example, Si ions are implanted as an n-type impurity from the opening of the resist mask 210. The implantation dose is 1 × 10 ¹³ to 1 × 10 ¹⁷ cm ⁻² and the implantation energy is 10 to 1000 keV. Thereby, an n-type impurity region 220 is selectively formed from the surface protective layer 200 to the barrier layer 40 and further to a part of the channel layer 30 (FIG. 2).

  After removing the resist mask 210, a heat treatment is performed to activate the implanted ions in the n-type impurity region 220, and the regions other than the surface side are recovered from the damage due to the ion implantation. Thus, the n-type impurity region 220 is divided into a damaged region 230 and an n-type impurity region 60 recovered from damage caused by ion implantation. Thereafter, the surface protective layer 200 is removed (FIG. 3).

  Subsequently, the damaged region 230 is removed by wet etching (FIG. 4). In general, nitride semiconductors such as GaN and AlGaN are difficult to wet etch because of their high chemical stability. However, the applicant has found that the damaged region 230 can be selectively wet-etched by adjusting the impurity implantation amount, implantation depth, and heat treatment conditions.

For wet etching of the damaged region 230, an acidic solution such as sulfuric acid, nitric acid or hydrochloric acid, a mixed solution thereof, a mixed solution of these and hydrogen peroxide solution, or an alkaline solution such as Na ₄ OH or KOH is used. it can. For example, a semiconductor crystal can be obtained by using a mixed solution of sulfuric acid and hydrogen peroxide solution in a state where damage is left after Si is implanted at an implantation dose amount of 1 × 10 ¹⁵ cm ⁻² and an implantation energy of 300 keV and heat treatment is performed. A region having an implantation depth of about 400 nm into which Si is introduced at a concentration of approximately 1 × 10 ¹⁷ cm ⁻³ or more can be wet etched. Here, the etching depth can be adjusted by the heat treatment conditions after ion implantation.

  In the n-type impurity ion implantation process described above, by performing ion implantation while appropriately changing the implantation energy, the n-type impurity region 220 having a doping concentration distribution that changes stepwise or continuously in the depth direction is formed. . In the wet etching process, it is possible to perform etching at a desired depth by using the difference in doping concentration.

  In the above description, heat treatment is performed after ion implantation and before wet etching to activate Si ions and recover damage. However, this heat treatment step may be performed after wet etching. Alternatively, high-temperature heat treatment may be performed before and after wet etching to activate the implanted Si ions.

  In the wet etching process, the damage region (damage region 230) of the semiconductor crystal generated during ion implantation and the impurity implantation region (damage region 230) in which the introduced impurity is not ionized and has a high resistance are removed. Only the resistive n-type impurity region 60 is left.

  In addition, since this process does not require patterning by a lithography process for alignment, the manufacturing process is simplified.

  Subsequently, a source electrode 70 and a drain electrode 80 made of, for example, Ti / Al are deposited using a vapor deposition method or a sputtering method, and formed by a lift-off method or the like (FIG. 5). Thereafter, in order to reduce the contact resistance between the source electrode 70 and the drain electrode 80, for example, an annealing process may be performed at a temperature of about 600 ° C. in a nitrogen atmosphere.

  Since the source electrode 70 and the drain electrode 80 are thus formed on the low resistance n-type impurity region 60, the contact resistance is reduced. Further, since the source electrode 70 and the drain electrode 80 are in contact with a clean semiconductor surface, the contact resistance is reduced. In addition, the contact resistance is reduced because the tunnel current increases due to a decrease in the thickness of the barrier layer 40 under the source electrode 70 and the drain electrode 80.

  FIG. 5 shows a state in which the source electrode 70 and the drain electrode 80 are substantially in contact with the inner wall of the recess structure of the nitride semiconductor layer (the channel layer 30 and the barrier layer 40). However, the source electrode 70 and the drain electrode 80 may be formed so that the portion exposed from the recess structure is larger than the recess width as shown in FIG. 7, or the whole is formed smaller than the recess width as shown in FIG. May be.

  Next, from the channel layer 30 outside the region for manufacturing the transistor to the barrier layer 40, for example, using the resist pattern 240 as a mask, ions of Zn, Ar, Fe, etc. are ion-implanted to form a high-resistance element isolation region 50 (FIG. 6). Although FIG. 6 shows the element isolation region 50 formed by ion implantation, element isolation may be performed by etching.

  Next, for example, Ni / Au is deposited using an evaporation method or a sputtering method, and a gate electrode 90 is formed between the source electrode 70 and the drain electrode 80 by a lift-off method or the like.

  By the above method, the heterojunction FET having the structure shown in FIG. 1 can be manufactured. In the above description, only the minimum necessary elements that operate as a transistor are mentioned, but finally, they are used as a device through a process of forming wirings, via holes, surface protective films, and the like.

<Modification>
Although typical conditions have been described above, the order of forming the source electrode 70, the drain electrode 80, the gate electrode 90, and the element isolation region 50 may be changed. For example, the element isolation region 50 may be formed before the source electrode 70 and the drain electrode 80 are formed.

  Further, as the semi-insulating substrate 10, Si, sapphire, GaN or the like may be used instead of SiC.

A nitride semiconductor represented by In _x1 Al _y1 Ga _1-x1-y1 N (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1, 0 ≦ x1 + y1 ≦ 1) instead of using GaN as the channel layer 30; A nitride semiconductor represented by In _x2 Al _y2 Ga _{1 -x2-y2} N (0 ≦ x2 ≦ 1, 0 ≦ y2 ≦ 1, 0 ≦ x2 + y2 ≦ 1) may be used as the barrier layer 40.

Further, as shown in FIG. 9, In _x3 Al _y3 Ga _1-x3-y3 N (0 ≦ x3 ≦ 1, 0 ≦ y3 ≦ 1, 0 ≦ x3 + y3 ≦ 1) formed by epitaxial growth on the barrier layer 40. A cap layer 100 made of a nitride semiconductor represented by The cap layer 100 may have a multilayer structure represented by different compositions.

Further, n-type or p-type impurities may be introduced into at least a part of the channel layer 30, the barrier layer 40, and the cap layer 100. This introduction method may be an ion implantation method or a source gas during epitaxial growth by MOCVD. Alternatively, silane (SiH ₄ ) may be used as the n-type dopant, and Cp ₂ Mg (cyclopentadiethyl magnesium) may be used as the p-type dopant.

  The source / drain electrodes 70 and 80 are composed of, for example, Si, Ge, Ti, Al, Nb, Hf, Zr, Sr, Ni, Ta, Au, Mo, W, or these instead of Ti / Al. A multilayer film or an alloy containing these may be formed by vapor deposition or sputtering.

Further, the gate electrode 90 is replaced with Ni / Au, for example, a metal such as Ti, Al, Pt, Au, Ni, Pd, or a silicide such as IrSi, PtSi, or NiSi ₂ , or a nitride metal such as TiN or WN, Or you may form the multilayer film comprised from these, or the alloy containing these using a vapor deposition method or a sputtering method.

  Further, the shape does not have to be a square cross section as shown in FIG. For example, as shown in FIG. 10, a gate electrode 91 having a T-type structure in which a region in contact with the barrier layer 40 is reduced may be used, or a gate electrode having a Y-type structure may be used. The gate electrode 91 having such a structure can reduce the gate resistance while maintaining an area in contact with the barrier layer 40 as compared with the gate electrode 90 having a normal shape (see FIG. 1).

  In FIG. 1, the n-type impurity region 60 is formed from the barrier layer 40 to the channel layer 30, but the formation region of the n-type impurity region 60 is not necessarily limited to this region. For example, as shown in FIG. 11, the n-type impurity region 60 may be formed only in the barrier layer 40, or may be formed deeper from the barrier layer 40 to the channel layer 30 than shown in FIG. In any case, if the n-type impurity region 60 is formed in at least a part of the semiconductor layer below the source electrode 70 and the drain electrode 80, the contact resistance can be reduced.

<Effect>
The nitride semiconductor layer etching method of this embodiment includes (a) a step of implanting impurity ions into a nitride semiconductor layer to form an impurity region (n-type impurity region 220) from the surface to a predetermined depth; b) a step of heat-treating the n-type impurity region 220; and (c) a step of removing a predetermined region (damage region 230) on the surface side of the n-type impurity region 220 by wet etching. It is possible to leave the low-resistance n-type impurity region 60 by removing only the damaged region 230 without damaging the n-type impurity region 220.

  In the step (a), the n-type impurity region 220 is formed by decreasing the impurity concentration stepwise or continuously in the depth direction, so that the subsequent wet etching step is based on the difference in impurity concentration. Only the damaged region 230 can be selectively removed.

  The method for manufacturing a nitride semiconductor device according to the present embodiment includes (a) an impurity region (a damaged region 230) from which a predetermined region on the surface side (damage region 230) has been removed by using the nitride semiconductor layer etching method according to the present embodiment. forming a nitride semiconductor layer having an n-type impurity region 60), and (b) forming a source electrode 70 and a drain electrode 80 in a region from which the damaged region 230 has been removed. Since the source electrode 70 and the drain electrode 80 are formed on the low-resistance n-type impurity region 60, these contact resistances can be reduced. Further, since the source electrode 70 and the drain electrode 80 are formed as recess electrodes in the region from which the damaged region 230 is removed, the contact resistance is reduced.

  10 semi-insulating substrate, 20 buffer layer, 30 channel layer, 40 barrier layer, 50 element isolation region, 60, 220 n-type impurity region, 70 source electrode, 80 drain electrode, 90, 91 gate electrode, 100 cap layer, 200 Surface protective layer, 210 resist pattern, 230 damage area.

Claims (3)

(A) implanting impurity ions into the nitride semiconductor layer and forming an impurity region from the surface to a predetermined depth;
(B) heat-treating the impurity region;
(C) a step of removing a predetermined region on the surface side of the impurity region by wet etching,
A method for etching a nitride semiconductor layer. The step (a) is a step of forming the impurity region by decreasing the impurity concentration stepwise or continuously in the depth direction.
The method for etching a nitride semiconductor layer according to claim 1. A method for manufacturing a nitride semiconductor device using the method for etching a nitride semiconductor layer according to claim 1 or 2,
(A) using the method for etching a nitride semiconductor layer according to claim 1 or 2, forming a nitride semiconductor layer having the impurity region from which a predetermined region on the surface side has been removed;
(B) forming a source electrode and a drain electrode in the predetermined region,
A method for manufacturing a nitride semiconductor device.

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