JP2010135399A - Hetero junction field effect transistor and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a hetero junction field effect transistor which reduces contact resistance between an n+ layer region of a source electrode and a drain electrode and a 2DEG channel. <P>SOLUTION: The hetero junction field effect transistor includes an electron traveling layer formed on a substrate, an electron supply layer formed on the electron traveling layer, and a trench provided on the electron supply layer corresponding to each of a source electrode and a drain electrode. The bottom surface of the trench is away from a hetero-junction which is the interface between the electron traveling layer and the electron supply layer by only a predetermined distance. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device, in particular, a heterojunction field effect transistor (HEMT) and a method for manufacturing the same.

  In GaN-based heterojunction field effect transistors, n + layers are selectively formed by ion implantation of dopants typified by Si into semiconductors (such as AlGaN / GaN) under ohmic electrodes in order to reduce on-resistance and access resistance. It has been tried to do. Hereinafter, the n-type conductive impurity diffusion layer is simply referred to as “n + layer” or “n + conductive layer” without being limited to ion implantation.

  FIG. 11 is a cross-sectional view showing an example of the structure of a heterojunction field effect transistor. FIG. 11 shows the case of an AlGaN / GaN heterojunction field effect transistor.

  As shown in FIG. 11, a GaN layer 102 serving as an electron transit layer and an AlGaN layer 104 serving as an electron supply layer are sequentially stacked on a buffer layer 100 serving as a substrate. On the upper surface of the AlGaN layer 104, a gate electrode 116, and a source electrode 112 and a drain electrode 114, which are ohmic electrodes, are formed. An implanted n + layer 106 formed by ion implantation is provided in the vicinity of the upper surface of the GaN layer 102 in each region of the source electrode 112 and the drain electrode 114. A 2DEG (two Dimensional Electron Gas) channel 105 is formed in the vicinity of the upper surface of the GaN layer 102.

  As shown in FIG. 11, in the GaN-based heterojunction field effect transistor, a dopant represented by Si is ion-implanted into a semiconductor (such as AlGaN / GaN) under an ohmic electrode in order to reduce on-resistance and access resistance. Attempts have been made to selectively form n + layers.

Patent Document 1 discloses an example of a method for forming an n + layer.
JP 2006-86354 A

  However, in the region surrounded by the ellipse shown in FIG. 11, the connection resistance between the formed n + layer and 2DEG is high, and as a result, there is a problem that the access resistance of the element cannot be sufficiently reduced. Etc. revealed. This will be described in detail in [Best Mode for Carrying Out the Invention]. The problem is that when the n + layer is formed by ion implantation, the crystal lattice arrangement at the semiconductor heterointerface is damaged by the ions implanted therein, and the carrier concentration of the 2DEG channel at the heterointerface is significantly reduced. It is believed that there is.

  On the other hand, a method of selectively forming an n + layer by a diffusion technique is also known, regardless of ion implantation. In the method of forming an n + layer by introducing a dopant into the sample by diffusion, the crystal lattice arrangement at the semiconductor heterointerface has the merit of being hardly affected by the diffused ions, and the connection between the formed n + layer and 2DEG is advantageous. Resistance is expected to be almost negligible. However, the diffusion coefficient of various dopants in a nitride semiconductor represented by GaN is smaller than that in silicon or GaAs, and the dopant cannot be diffused so deeply into the sample.

  An example of a method for taking measures against this defect is disclosed in Patent Document 1. The method disclosed in that document will be briefly described with reference to FIGS.

  A sample in which a GaN layer 102 and an AlGaN layer 104 are sequentially stacked on a substrate 101 is prepared. A trench structure that reaches a position deeper than the 2DEG channel 105 in the semiconductor heterojunction is formed in the sample, and a diffusion source such as a polysilicon film (or an amorphous silicon film) 120 is deposited in the trench.

  Subsequently, diffusion annealing is performed to diffuse the dopant from the polysilicon film 120, thereby forming an n + layer 122 as shown in FIG. Thereafter, the source electrode 132 and the drain electrode 134 are respectively formed in the trench portions of the source region 124 and the drain region 126 shown in FIG. 12 (FIG. 13). At that time, the gate electrode 136 may be simultaneously formed on the AlGaN layer 104. According to this method, the slow diffusion of the dopant in the nitride semiconductor can be technically covered.

  However, the inventors of the present invention have clarified through experiments that the above method of forming an n + layer by diffusion after digging a trench has a drawback. The disadvantage is that when a trench structure that reaches a position deeper than the 2DEG channel in the semiconductor heterojunction is formed by using a method such as dry etching, the vicinity of the trench end of the semiconductor heterojunction interface (including the trench end, From there, the crystal arrangement in the region of at least several hundred mm is disturbed, and at the site where the crystal arrangement is disturbed, the carrier of the 2DEG channel is depleted and the connection resistance between the formed n + layer and 2DEG is as expected. Is difficult to decline. 1Å = 0.1 nm.

  In this case, in order to reduce the connection resistance, it is necessary to make the distance in which the dopant diffuses in the depth direction larger than the distance of the damaged heterointerface, and increase the diffusion annealing temperature or lengthen the annealing time. It will be necessary to change the process. This clearly has a disadvantage in manufacturing the device with good controllability and in mass production.

  The present invention has been made to solve the above-described problems of the technology, and provides a heterojunction field effect transistor with reduced contact resistance between the n + layer region of the source electrode and the drain electrode and the 2DEG channel. The purpose is to do.

In order to achieve the above object, a heterojunction field effect transistor of the present invention provides:
An electron transit layer provided on the substrate;
An electron supply layer provided on the electron transit layer;
A trench provided in the electron supply layer corresponding to each of the source electrode and the drain electrode,
The bottom surface of the trench is configured to be separated from the heterojunction that is an interface between the electron transit layer and the electron supply layer by a predetermined distance.

In addition, the method of manufacturing the heterojunction field effect transistor of the present invention includes:
An electron transit layer and an electron supply layer are sequentially formed on the substrate,
Forming a trench whose bottom surface is located at a predetermined distance from the top surface of the electron transit layer in the electron supply layer in a region corresponding to each of the source electrode and the drain electrode;
Forming a diffusion source in the trench for diffusing impurities from at least the bottom surface of the trench;
A heat treatment for diffusing the impurities from the diffusion source until reaching a heterojunction that is an interface between the electron transit layer and the electron supply layer is performed.

  According to the present invention, the contact resistance between the n + layer regions of the source electrode and the drain electrode and the 2DEG channel at the heterojunction can be reduced.

An AlGaN / GaN heterojunction structure is the most typical multilayer epitaxial film made of a GaN-based material for producing the heterojunction field effect transistor (HEMT) of the present invention. In this structure, the AlGaN / GaN hetero interface has a high sheet charge density of 10 ¹³ cm ^-2 units, approximately 5 times that of the corresponding GaAs-based AlGaAs / GaAs heterojunction interface, due to the polarization effect characteristic of nitride semiconductor materials. An Ns carrier is formed, and an HEMT device using this carrier has excellent characteristics such as a high current value and a high output power.

Various dopant species have been reported to selectively form an n + conductive layer by ion implantation into the above HEMT structure, but ²⁸ Si is the most effective. The thickness of the AlGaN layer is usually 15 to 45 nm, and the Al composition is usually 0.15 to 0.20. When ²⁸ Si is ion-implanted into an AlGaN / GaN-HEMT structure having this profile, through implantation in which ions are implanted via a through film is usually used. As the implantation conditions, acceleration energy of 30 to 120 keV and a dose of 1 × 10 ^{14 to} 3 × 10 ¹⁵ cm ⁻² are normal values applied to the device. After ion implantation, activation annealing at about 1200 ° C. is performed to activate the doped ions.

A nitride film SiN with a thickness of 80 nm is deposited as a through film on Al _0.15 Ga _0.85 N (45 nm thickness) / GaN heterojunction epitaxy, and ²⁸ Si ions are implanted with an acceleration energy of 100 keV and a dose of 1 × 10 ¹⁵ cm ^-2 The problem when the n + layer is formed by ion implantation will be described using an example of activation annealing at 1200 ° C. for 3 minutes as an example.

  TiAlNbAu metallized ohmic electrodes were formed on this structure, and the electrical characteristics were measured by hole measurement or TLM (Transmission Line Model) method. As a result, the contact resistance in the n + layer region is Rc = 0.5Ωmm, and the sheet resistance is 50Ω / □, but the problem is the connection resistance between the n + layer region and 2DEG. It turned out to be bigger. This connection resistance is added as a contact resistance, and increases the access resistance and on-resistance of the device.

  As described in the section of the problem, there is also known a method of selectively forming an n + layer by a diffusion technique without using ion implantation. An example of such a method is disclosed in Patent Document 1, but as described above, there is a drawback in the method of forming an n + layer by a diffusion technique after digging a trench. The heterojunction field effect transistor of this embodiment will be described below. The same code | symbol is attached | subjected about the same structure.

(First embodiment)
A method of manufacturing the heterojunction field effect transistor of this embodiment will be described. FIG. 1 is a cross-sectional view showing the manufacturing process of the heterojunction field effect transistor of this embodiment, and FIG. 2 is a cross-sectional view showing the heterojunction field effect transistor after manufacture.

  As shown in FIG. 1, a sample in which a GaN layer 102 and an AlGaN layer 104 are sequentially laminated on a substrate 101 is prepared. Subsequently, a trench is formed in the source region 14 and the drain region 16 that is shallow so as not to reach the 2DEG channel 105 in the semiconductor heterojunction and is close to the channel. The distance between the bottom of the trench and the 2DEG channel 105 is preferably 50 mm or more and less than 300 mm in consideration of diffusion by subsequent heat treatment. A polysilicon film 120 is deposited in the trench as a diffusion source. The diffusion source is not limited to the polysilicon film 120, and may be an amorphous silicon film or another film. The same applies to the second to fifth embodiments described below.

  After the polysilicon film 120 is formed, diffusion annealing is performed to diffuse the dopant from the polysilicon film 120 into the AlGaN layer 104 and the GaN layer 102 as shown in FIG. The thickness of the n + layer 12 is desirably 100 mm or more corresponding to the distance (50 mm or more and less than 300 mm) between the bottom surface of the trench and the 2DEG channel 105. In addition, considering the case of several hundreds of meters as described in the assignment section, it is only necessary to have 1,000. Thereafter, as shown in FIG. 2, the ohmic electrode source electrode 22 and the drain electrode 24 are formed in the trench portion, and the gate electrode 26 is formed on the AlGaN layer 104.

  The structure of the heterojunction field effect transistor of this embodiment will be described with reference to FIG. As shown in FIG. 2, in the heterojunction field effect transistor of this embodiment, the bottom surface of the trench is separated from the top surface of the GaN layer 102 by a predetermined distance. The n + layer 12 formed by the diffusion of the dopant from the diffusion source reaches the 2DEG channel 105 and the GaN layer 102.

  In the heterojunction field effect transistor of this embodiment, even when the trench structure is formed by using a method such as dry etching, the crystal arrangement immediately below the trench bottom surface of the semiconductor heterojunction interface is not disturbed. Therefore, the carrier density of the 2DEG channel is maintained even after the dopant diffusion annealing, and the connection resistance between the formed n + layer and the 2DEG channel is almost negligible. In the present embodiment, the connection resistance between the n + layer region and the 2DEG channel can be reduced by improving and utilizing the diffusion technique.

(Second Embodiment)
A method of manufacturing the heterojunction field effect transistor of this embodiment will be described. FIG. 3 is a cross-sectional view showing the manufacturing process of the heterojunction field effect transistor of this embodiment, and FIG. 4 is a cross-sectional view showing the heterojunction field effect transistor after manufacture.

  After forming a trench in the sample in the same manner as in the first embodiment, as shown in FIG. 3, silicon is formed on the top surface of the AlGaN layer 104, the side surface of the trench, and the portion of the bottom surface of the trench excluding a part. A diffusion stopper layer 20 such as an oxide film or a silicon nitride film is formed. The bottom surface of the trench is the AlGaN layer 104, as long as at least a part thereof is exposed, and the entire bottom surface may be exposed. The diffusion stopper layer 20 is a film that prevents dopant diffusion. As shown in FIG. 3, a polysilicon film 120 serving as a diffusion source is deposited in the trench portion, and an n + layer 18 is formed on the sample by diffusion annealing. During the diffusion annealing, the dopant is not diffused into the AlGaN layer 104 by the diffusion stopper layer 20 but diffuses into the GaN layer 102 vertically below the main surface of the substrate. Thereafter, as shown in FIG. 4, the ohmic electrode source electrode 23 and the drain electrode 25 are formed in the trench portion, and the gate electrode 27 is formed on the AlGaN layer 104.

  The structure of the heterojunction field effect transistor of this embodiment will be described with reference to FIG. As shown in FIG. 4, in the heterojunction field effect transistor of this embodiment, the bottom surface of the trench is separated from the top surface of the GaN layer 102 by a predetermined distance. The n + layer 18 formed by the diffusion of the dopant from the diffusion source reaches the 2DEG channel 105 and the GaN layer 102.

  In the heterojunction field effect transistor of this embodiment, even when the trench structure is formed by using a method such as dry etching, the crystal arrangement immediately below the trench bottom surface of the semiconductor heterojunction interface is not disturbed. For this reason, the carrier density of the 2DEG channel is maintained even after dopant diffusion annealing, and the connection resistance between the formed n + layer and the 2DEG channel is almost negligible, as in the first embodiment.

  Further, in the present embodiment, since the effect of dopant diffusion in the trench sidewall direction can be suppressed as much as possible, the short channel effect that occurs as the device is highly integrated or miniaturized can be suppressed.

(Third embodiment)
A method of manufacturing the heterojunction field effect transistor of this embodiment will be described. 5 and 6 are cross-sectional views showing the manufacturing process of the heterojunction field effect transistor of this embodiment, and FIG. 7 is a cross-sectional view showing the heterojunction field effect transistor after manufacture.

  After the trench is formed in the sample in the same manner as in the first embodiment, as shown in FIG. 5, ion implantation is performed on the source region 14 and the drain region 16 where the n + conductive layer is to be formed. An implanted n + layer 30 is formed by performing annealing. Subsequently, in the plane parallel to the main surface of the substrate, the pattern is wider than the pattern of the implantation n + layer 30 and is shallow so as not to reach the 2DEG channel 105 in the semiconductor heterojunction, as in the first embodiment. A trench dug up to near is formed. The distance between the bottom of the trench and the 2DEG channel 105 is preferably 50 mm or more and less than 300 mm. Then, a polysilicon film 120 serving as a diffusion source is deposited in the trench (FIG. 6).

  After the polysilicon film 120 is formed, diffusion annealing is performed to diffuse the dopant from the polysilicon film 120 into the AlGaN layer 104 and the GaN layer 102 as shown in FIG. Thereafter, as shown in FIG. 7, the ohmic electrode source electrode 22 and the drain electrode 24 are formed in the trench portion, and the gate electrode 26 is formed on the AlGaN layer 104.

  The structure of the heterojunction field effect transistor of this embodiment will be described with reference to FIG. As shown in FIG. 7, in the heterojunction field effect transistor of this embodiment, the bottom surface of the trench is separated from the top surface of the GaN layer 102 by a predetermined distance. The n + layer 12 formed by the diffusion of the dopant from the diffusion source reaches the 2DEG channel 105 and the GaN layer 102.

  In the heterojunction field effect transistor of this embodiment, even when the trench structure is formed by using a method such as dry etching, the crystal arrangement immediately below the trench bottom surface of the semiconductor heterojunction interface is not disturbed. For this reason, the carrier density of the 2DEG channel is maintained even after dopant diffusion annealing, and the connection resistance between the formed n + layer and the 2DEG channel is almost negligible, as in the first embodiment.

  Further, in the present embodiment, there is an advantage that the n + layer can be formed deeply by ion implantation, and it becomes easy to form an electrode such as a vertical device.

(Fourth embodiment)
A method of manufacturing the heterojunction field effect transistor of this embodiment will be described. 5, 8 and 9 are cross-sectional views showing the manufacturing procedure of the heterojunction field effect transistor of this embodiment.

  In the same manner as described in the third embodiment with reference to FIG. 5, the implantation n + layer 30 is formed by performing ion implantation and activation annealing on the portion where the n + conductive layer is formed in the sample. Subsequently, a trench is formed in a pattern wider than the pattern of the implanted n + layer 30 when viewed from vertically above the main surface of the substrate, as in the first embodiment.

  After the trench is formed in the sample, as shown in FIG. 8, diffusion of a silicon oxide film, a silicon nitride film, or the like on the top surface of the AlGaN layer 104, the side surface of the trench, and the portion other than the bottom surface of the trench. A stopper layer 20 is formed. The bottom surface of the trench is the AlGaN layer 104, as long as at least a part thereof is exposed, and the entire bottom surface may be exposed.

  Thereafter, a polysilicon film 120 serving as a diffusion source is deposited in the trench portion, and an n + layer 18 is formed on the sample by diffusion annealing. During the diffusion annealing, the dopant is not diffused into the AlGaN layer 104 by the diffusion stopper layer 20 but diffuses into the GaN layer 102 perpendicular to the main surface of the substrate. Further, as shown in FIG. 9, the source electrode 23 and the drain electrode 25 that are ohmic electrodes are formed in the trench portion, and the gate electrode 27 is formed on the AlGaN layer 104.

  The structure of the heterojunction field effect transistor of this embodiment will be described with reference to FIG. As shown in FIG. 9, in the heterojunction field effect transistor of this embodiment, the bottom surface of the trench is separated from the top surface of the GaN layer 102 by a predetermined distance. The n + layer 18 formed by the diffusion of the dopant from the diffusion source reaches the 2DEG channel 105 and the GaN layer 102.

  In the heterojunction field effect transistor of this embodiment, even when the trench structure is formed by using a method such as dry etching, the crystal arrangement immediately below the trench bottom surface of the semiconductor heterojunction interface is not disturbed. For this reason, the carrier density of the 2DEG channel is maintained even after dopant diffusion annealing, and the connection resistance between the formed n + layer and the 2DEG channel is almost negligible, as in the first embodiment.

  Further, in the present embodiment, since the effect of dopant diffusion in the trench sidewall direction can be suppressed as much as possible, the short channel effect that occurs as the device is highly integrated or miniaturized can be suppressed. Furthermore, in this embodiment, there is an advantage that the n + layer can be formed deeply by ion implantation, and the effect is exhibited in the formation of an electrode such as a vertical device.

(Fifth embodiment)
This embodiment further improves the heterojunction field effect transistor described in the first to fourth embodiments. Before describing the configuration of the present embodiment, the contact resistance between the metal electrode for ohmic contact and the semiconductor interface will be described.

Generally, the contact resistivity between the metal electrode for ohmic contact and the semiconductor interface is determined by the following three parameters.
(A) Schottky barrier height φ _B
(B) Impurity (dopant) concentration N _{d of} an electrically active donor or acceptor in the semiconductor surface layer
(C) Amount of contaminants such as a natural oxide film on the surface of the semiconductor sample When the surface of the nitride semiconductor as the sample is kept clean (no oxide film or the like), the Schottky barrier height φ _B As a parameter, the dopant concentration dependence of the ohmic contact resistivity ρ _c can be estimated. Usually, in a metal-semiconductor junction, thermionic emission process where electrons cross the barrier determines its current-voltage characteristics. However, when the dopant concentration is 10 ¹⁹ cm ⁻³ or more, the distance between impurity atoms is short, so the electron distribution is degenerated, the depletion layer due to the Schottky barrier is narrowed, and conduction by the field emission tunneling mechanism becomes dominant. The contact resistivity ρ _c is dependent on the impurity concentration N _d and the Schottky barrier height φ _B as shown in the following equation (1).

In equation (1), ε _s is the dielectric constant of the semiconductor, m ^* is the effective mass of electrons in the semiconductor, q is the charge of the electrons, h is the Planck constant, and A is the proportionality coefficient.

When a conductive layer is selectively formed on a nitride-based semiconductor by diffusion, the diffusion rate of ²⁸ Si and other dopants is slow, so there is an extremely large amount of dopant on the sample surface, and the dopant concentration is natural. 10 ¹⁹ cm ^-3 or more, easily reach 10 ²¹ cm ^-3 or more. Therefore, the method of forming an n + layer by diffusion and forming an ohmic electrode thereon has the advantage that a very low value can be easily achieved for contact resistance according to equation (1). For semiconductor device processes, non-alloy ohmic junctions without heat treatment are desirable, but this can be realized in principle by forming the n + layer using the diffusion in this case.

  The configuration of the heterojunction field effect transistor of this embodiment will be described. Although this embodiment can be applied to any of the first to fourth embodiments, here, a case where it is applied to the first embodiment will be described. FIG. 10 is a cross-sectional view showing a configuration example of the heterojunction field effect transistor of this embodiment.

In the first embodiment, the source electrode 32 and the drain electrode 34 are formed by leaving a part or all of Si of the diffusion source after being used for diffusion, forming an ohmic metal material thereon, and performing heat treatment. An ohmic electrode 38 is formed on the substrate (FIG. 10). The ohmic electrode 38 shown in FIG. 10 has a structure in which a TiSi ₂ film, a Ti film, and an Au film are sequentially stacked on the polysilicon film 120. A TiSi ₂ film serving as a silicide electrode is formed on the lowermost layer portion of the ohmic electrode 38. With such a structure, the ohmic electrode 38 having a stable contact resistance value can be produced.

An ohmic electrode is applied to a sample in which Si is diffused as an impurity to a density close to (or higher than) the solid solution limit of the semiconductor surface, or a sample in which Si that becomes the diffusion source after diffusion is left on the surface. If formed, excess Si and ohmic metal (M) react to form silicide M _x Si _y easily.

Examples of the metal that easily forms silicide include molybdenum (Mo), tungsten (W), titanium (Ti), niobium (Nb), nickel (Ni), platinum (Pt), and aluminum (Al). . Empirically, the Schottky barrier height φ ′ _Bn between the n-type semiconductor and the silicide M _x Si _y is generally not much different from the Schottky barrier height φ _Bn between the n-type semiconductor and the original corresponding metal M. (SM Sze and Kwok K. Ng: Physics of Semiconductor Devices, (Third Edition), Wiley-Interscience, pp.179-180, 2006.). Since a low resistance is desirable for the ohmic electrode, silicidation of the ohmic electrode increases the resistance of the electrode and seems to have no merit at first glance.

  However, when the ohmic metal is silicided (if the ohmic metal has a laminated structure of various metals, the lowermost metal is mainly silicided), the ohmic metal reacts with the oxide film (or nitride film). In addition to preventing oxidation by reacting with oxygen, the stability of the purity of the material, stability in the process (high temperature resistance, chemical resistance, There are advantages in that it does not occur.

  In the present embodiment, an ohmic electrode having a stable contact resistance value can be produced by utilizing silicidation of the ohmic electrode.

  In the following, in the Examples, the manufacturing process corresponding to each of the above embodiments and the electrical characteristics of the device after manufacture will be described. Here, the case of single-hetero is explained in detail as the HEMT structure, but the structure and process can be designed in the same manner as in the case of single-hetero in the case of double-hetero. The detailed explanation is omitted.

  A method of manufacturing a heterojunction field effect transistor according to an example corresponding to the first embodiment will be described with reference to FIGS.

  An i-AlGaN (45 nm thickness) / i-GaN heterojunction epitaxial film was grown on a 3-inch Si substrate by MOCVD (Metal Organic Chemical Vapor Deposition). In order to form alignment marks in subsequent steps, this sample was patterned with a resist, and then a mesa step was formed on the sample surface by dry etching.

After patterning with a resist, a trench having a depth of 35 nm was formed by dry etching with an etching gas BCl ₃ and Cl ₂ from the resist opening. As a result, the distance from the bottom of the trench to the AlGaN / GaN heterojunction is 10 nm.

  Furthermore, 30 nm of amorphous silicon was deposited on the trench surface by evaporation using a lift-off method. By performing diffusion annealing at 950 ° C. for 6 hours as it is, Si was doped into the trench surface by diffusion (FIG. 1). When amorphous silicon is heated to 950 ° C., it instantly changes to polysilicon, which is polycrystalline Si. Since Si as a dopant diffuses to a depth of 30 nm or more by the above-described diffusion annealing, the AlGaN / GaN heterojunction and the selective conductive layer are connected. After the diffusion annealing, the polysilicon was removed with hydrofluoric acid to which hydrogen peroxide was added.

Next, after patterning the sample with a resist, surface treatment was performed with hydrochloric acid, and ohmic metal Ti / Al / Nb / Au was evaporated. Thereafter, the sample was lifted off and subsequently alloyed by RTA (Rapid Thermal Annealing) at 850 ° C. for 30 seconds. With this alloy, it is considered that silicide (TiSi ₂ ) is formed at the junction with the semiconductor in the lowermost layer metal of the ohmic electrode. This silicide brings about stabilization of the ohmic contact resistance value.

Further, patterning with resist on the sample and implanting ¹⁴ N ions (first implantation conditions: 100 keV, 1E14 cm ^-2 , second implantation conditions: 20 keV, 1E14 cm ^-2 two-stage implantation) to form isolation did. A gate electrode was formed by the lift-off method (FIG. 2), and the characteristics of the sample were evaluated by hole measurement and electrical measurement using a TLM pattern.

  The contact resistance in the n + layer region was Rc = 0.1Ωmm, and the sheet resistance was about 100Ω / □. The connection resistance between the n + layer region and 2DEG, which was a problem in the past, was 0.01Ωmm, which was a negligible level.

  A method of manufacturing a heterojunction field effect transistor according to an example corresponding to the second embodiment will be described with reference to FIGS.

  An i-AlGaN (45 nm thickness) / i-GaN heterojunction epitaxial film was grown on a 3-inch Si substrate by MOCVD. In order to form alignment marks in subsequent steps, this sample was patterned with a resist, and then a mesa step was formed on the sample surface by dry etching.

After patterning with a resist, a trench having a depth of 35 nm was formed by dry etching with an etching gas BCl ₃ and Cl ₂ from the resist opening. As a result, the distance from the bottom of the trench to the AlGaN / GaN heterojunction is 10 nm.

Using a lift-off method, 40 nm of SiO ₂ was deposited as a diffusion stopper layer on the portion excluding the bottom of the trench.

  Furthermore, 30 nm of amorphous Si was deposited on the trench surface by evaporation using the lift-off method. By performing diffusion annealing at 950 ° C. for 6 hours as it is, Si was doped into the trench surface by diffusion (FIG. 3). When the temperature of amorphous Si rises to 950 ° C, it instantly changes to polysilicon, which is polycrystalline Si. Since Si as a dopant diffuses to a depth of 30 nm or more by the above-described diffusion annealing, the AlGaN / GaN heterojunction and the selective conductive layer are connected. In the case of the present embodiment, since the diffusion stopper layer is deposited on the trench side wall, the diffusion mainly proceeds only below the sample. Although the edge portion also spreads in the lateral direction, it is negligible as fringing. After the diffusion annealing, the polysilicon was removed with hydrofluoric acid to which hydrogen peroxide was added.

Next, after patterning the sample with a resist, surface treatment was performed with hydrochloric acid, and ohmic metal Ti / Al / Nb / Au was evaporated. Thereafter, the sample was lifted off, and subsequently alloyed by RTA at 850 ° C. for 30 seconds. With this alloy, it is considered that silicide (TiSi ₂ ) is formed at the junction with the semiconductor in the lowermost layer metal of the ohmic electrode. This silicide brings about stabilization of the ohmic contact resistance value.

Furthermore, patterning with resist on the sample and implanting ¹⁴ N ions (first implantation conditions: 100 keV, 1E14 cm ^-2 , second implantation conditions: 20 keV, 1E14 cm ^-2 two-stage implantation) to form isolation did. A gate electrode was formed by a lift-off method (FIG. 4), and the characteristics of the sample were evaluated by hole measurement or electrical measurement using a TLM pattern.

  The contact resistance in the n + layer region was Rc = 0.1Ωmm, and the sheet resistance was about 100Ω / □. The connection resistance between the n + layer region and 2DEG, which was a problem in the past, was 0.01Ωmm, which was a negligible level.

  A method of manufacturing a heterojunction field effect transistor according to an example corresponding to the third embodiment will be described with reference to FIGS.

  An i-AlGaN (45 nm thickness) / i-GaN heterojunction epitaxial film was grown on a 3-inch Si substrate by MOCVD. In order to form alignment marks in subsequent steps, this sample was patterned with a resist, and then a mesa step was formed on the sample surface by dry etching.

After organic cleaning of the sample, a 30 nm nitride film SiN was deposited as a through film, and an n ⁺ layer was selectively formed by ion implantation in the trench portion to be formed in a later process, and patterned with a resist. Thereafter, ion implantation of ²⁸ Si (acceleration energy 80 keV, dose amount 3.0E15 cm ⁻² ) was performed. Thereafter, the through film was removed with hydrofluoric acid.

In this state, since the implanted dopant ²⁸ Si is not activated, it is necessary to perform activation annealing. First, in order to form an annealing protective film, after removing the resist of the sample, the silicon oxynitride film Si ₂ O _x N _y (x, y is approximately 0 <x ≦ 1.0 on the top surface, back surface, and side wall of the sample. , 1 <y <4) was deposited by plasma CVD method for 1200Å.

  Next, activation annealing (holding time: for example, 5 minutes) was applied to the sample in a nitrogen atmosphere at a temperature of 1200 ° C. Next, in order to remove the protective film, the sample was immersed in concentrated hydrofluoric acid and then washed with water (FIG. 5).

After patterning with a resist so that the ion-implanted portion was opened, a trench having a depth of 35 nm was formed by dry etching with the etching gases BCl ₃ and Cl ₂ from the resist opening. As a result, the distance from the bottom of the trench to the AlGaN / GaN heterojunction is 10 nm. Using a lift-off method, 40 nm of SiO ₂ was deposited as a diffusion stopper layer on the portion excluding the bottom of the trench.

Furthermore, 30 nm of amorphous Si was deposited on the trench surface by evaporation using the lift-off method. By performing diffusion annealing at 950 ° C. for 6 hours as it is, Si was doped into the trench surface by diffusion (FIG. 6). When the temperature of amorphous Si rises to 950 ° C, it instantly changes to polysilicon, which is polycrystalline Si. Since Si as a dopant diffuses to a depth of 30 nm or more by the above-described diffusion annealing, the AlGaN / GaN heterojunction and the selective conductive layer are connected. In the case of the present embodiment, since the diffusion stopper layer is deposited on the trench side wall, the diffusion mainly proceeds only below the sample. Although the edge portion also spreads in the lateral direction, it is negligible as fringing. After diffusion annealing, SiO ₂ and polysilicon were removed with hydrofluoric acid to which hydrogen peroxide was added.

Next, after patterning the sample with a resist, surface treatment was performed with hydrochloric acid, and ohmic metal Ti / Al / Nb / Au was evaporated. Thereafter, the sample was lifted off, and subsequently alloyed by RTA at 850 ° C. for 30 seconds. With this alloy, it is considered that silicide (TiSi ₂ ) is formed at the junction with the semiconductor in the lowermost layer metal of the ohmic electrode. This silicide brings about stabilization of the ohmic contact resistance value.

Furthermore, patterning with resist on the sample and implanting ¹⁴ N ions (first implantation conditions: 100 keV, 1E14 cm ^-2 , second implantation conditions: 20 keV, 1E14 cm ^-2 two-stage implantation) to form isolation did. A gate electrode was formed by the lift-off method (FIG. 7), and the characteristics of the sample were evaluated by hole measurement or electrical measurement using a TLM pattern.

  The contact resistance in the n + layer region was Rc = 0.1Ωmm, and the sheet resistance was 78Ω / □. The connection resistance between the n + layer region and 2DEG, which was a problem in the past, was 0.01Ωmm, which was a negligible level.

  A method for manufacturing a heterojunction field effect transistor according to an example corresponding to the fourth embodiment will be described with reference to FIGS. 5, 8, and 9.

  An i-AlGaN (45 nm thickness) / i-GaN heterojunction epitaxial film was grown on a 3-inch Si substrate by MOCVD. In order to form alignment marks in subsequent steps, this sample was patterned with a resist, and then a mesa step was formed on the sample surface by dry etching.

After organic cleaning of the sample, a 30 nm nitride film SiN is deposited as a through film, and after patterning the sample with a resist to selectively form an n + layer by ion implantation in a trench portion to be formed in a later process , ²⁸ Si ion implantation (acceleration energy 80 keV, dose amount 3.0E15 cm ⁻² ). Thereafter, the through film was removed with hydrofluoric acid.

In this state, since the implanted dopant ²⁸ Si is not activated, it is necessary to perform activation annealing. First, in order to form an annealing protective film, the sample resist is removed, and then the silicon oxynitride film Si ₂ O _x N _y (x, y is approximately 0 <x ≦ 1.0 on the top surface, back surface, and side wall of the sample. , 1 <y <4) was deposited by plasma CVD method for 1200Å.

  Next, activation annealing (holding time: for example, 5 minutes) was applied to the sample in a nitrogen atmosphere at a temperature of 1200 ° C. Next, in order to remove the protective film, the sample was immersed in concentrated hydrofluoric acid and then washed with water (FIG. 5).

After patterning with a resist so that the ion-implanted portion was opened, a trench having a depth of 35 nm was formed by dry etching with the etching gases BCl ₃ and Cl ₂ from the resist opening. As a result, the distance from the bottom of the trench to the AlGaN / GaN heterojunction is 10 nm.

Furthermore, 30 nm of amorphous silicon was deposited on the trench surface by evaporation using a lift-off method. By performing diffusion annealing at 950 ° C. for 6 hours as it is, Si was doped into the trench surface by diffusion (FIG. 8). When amorphous silicon is heated to 950 ° C., it instantly changes to polysilicon, which is polycrystalline Si. Since Si as a dopant diffuses to a depth of 30 nm or more by the above-described diffusion annealing, the AlGaN / GaN heterojunction and the selective conductive layer are connected. In the case of the present embodiment, since the diffusion stopper layer is deposited on the trench side wall, the diffusion mainly proceeds only below the sample. Although the edge portion also spreads in the lateral direction, it is negligible as fringing. After diffusion annealing, SiO ₂ and polysilicon were removed with hydrofluoric acid to which hydrogen peroxide was added.

Next, after patterning the sample with a resist, surface treatment was performed with hydrochloric acid, and ohmic metal Ti / Al / Nb / Au was evaporated. Thereafter, the sample was lifted off, and subsequently alloyed by RTA at 850 ° C. for 30 seconds. With this alloy, it is considered that silicide (TiSi ₂ ) is formed at the junction with the semiconductor in the lowermost layer metal of the ohmic electrode. This silicide brings about stabilization of the ohmic contact resistance value.

Further, patterning with resist on the sample and implanting ¹⁴ N ions (first implantation conditions: 100 keV, 1E14 cm ^-2 , second implantation conditions: 20 keV, 1E14 cm ^-2 two-stage implantation) to form isolation did. A gate electrode was formed by the lift-off method (FIG. 9), and the characteristics of the sample were evaluated by hole measurement or electrical measurement using a TLM pattern.

  The contact resistance in the n + layer region was Rc = 0.1Ωmm, and the sheet resistance was 78Ω / □. The connection resistance between the n + layer region and 2DEG, which was a problem in the past, was 0.01Ωmm, which was a negligible level.

  A method of manufacturing a heterojunction field effect transistor according to an example corresponding to the fifth embodiment will be described with reference to FIGS.

  An i-AlGaN (45 nm thickness) / i-GaN heterojunction epitaxial film was grown on a 3-inch Si substrate by MOCVD. In order to form alignment marks in subsequent steps, this sample was patterned with a resist, and then a mesa step was formed on the sample surface by dry etching.

After patterning with a resist, a trench having a depth of 35 nm was formed by dry etching with an etching gas BCl ₃ and Cl ₂ from the resist opening. As a result, the distance from the bottom of the trench to the AlGaN / GaN heterojunction is 10 nm.

  Furthermore, 10 nm of amorphous Si was deposited on the trench surface by evaporation using the lift-off method. By performing diffusion annealing at 950 ° C. for 6 hours as it is, Si was doped into the trench surface by diffusion (FIG. 1). When the temperature of amorphous Si rises to 950 ° C, it instantly changes to polysilicon, which is polycrystalline Si. Since Si as a dopant diffuses to a depth of 30 nm or more by the above-described diffusion annealing, the AlGaN / GaN heterojunction and the selective conductive layer are connected. In the case of this example, the polysilicon was left after the diffusion annealing.

Next, after patterning the sample with a resist, surface treatment was performed with hydrochloric acid, and ohmic metal Ti / Au was further deposited. Thereafter, the sample was lifted off, and subsequently alloyed by RTA at 850 ° C. for 30 seconds. With this alloy, it is considered that silicide (TiSi ₂ ) is formed at the junction with polysilicon in the lowermost layer metal of the ohmic electrode. This silicide has an advantage of stabilizing the ohmic contact resistance value.

Furthermore, patterning with resist on the sample and implanting ¹⁴ N ions (first implantation conditions: 100 keV, 1E14 cm ^-2 , second implantation conditions: 20 keV, 1E14 cm ^-2 two-stage implantation) to form isolation did. A gate electrode was formed by a lift-off method (FIG. 10), and the characteristics of the sample were evaluated by hole measurement or electrical measurement using a TLM pattern.

  The contact resistance in the n + layer region was Rc = 0.15Ωmm, and the sheet resistance was about 100Ω / □. The connection resistance between the n + layer region and 2DEG, which was a problem in the past, was 0.01Ωmm, which was a negligible level.

  In the above, the case of using TiAu as the ohmic metal has been described, but the same effect can be obtained by using Mo, W, Nb, Ni, Pt, Al, etc. in addition to Ti as the lowermost metal layer. .

Furthermore, as an example of M ₂ = Au as the metal or multi-metal laminated film (M ₂ ) deposited on the upper layer of these metals (M ₁ ), as an example of M ₂ for M ₁ = Ti, For example, all combinations used as ohmic metals such as Pt / Au, Al / Mo / Au, and Al / Nb / Au are all effective.

In the above, amorphous Si (changed to polysilicon after diffusion annealing) was deposited as a diffusion source by vapor deposition. However, if it is desired to reduce the resistance of the polysilicon portion, n + -poly Si doped with phosphorus (P) is used. A method of depositing (or n ⁺ -amorphous Si) by CVD is effective. In this case, it is difficult to apply pattern formation by the lift-off method as described above in order to define the diffusion pattern. However, for example, using a previously formed silicon nitride film or silicon oxide film pattern as a mask, the above-described phosphorus (P) -doped n + -poly Si is deposited by CVD, and the mask is used as a diffusion source. It is possible to take a method of diffusing from the opening.

  In the manufacturing process, it has been described that the heat treatment is required corresponding to the impurity diffusion step. However, a plurality of heat treatments may be performed together. In this case, the number of heat treatment steps can be suppressed.

  The present invention provides a technique indispensable for reducing the access resistance or on-resistance of a GaN-based heterojunction field effect transistor, and greatly contributes to the development of GaN devices for future communication and power control applications.

It is sectional drawing which shows the manufacturing process of the heterojunction field effect transistor of 1st Embodiment. It is sectional drawing which shows one structural example of the heterojunction field effect transistor of 1st Embodiment. It is sectional drawing which shows the manufacturing process of the heterojunction field effect transistor of 2nd Embodiment. It is sectional drawing which shows one structural example of the heterojunction field effect transistor of 2nd Embodiment. It is sectional drawing which shows the manufacturing process of the heterojunction field effect transistor of 3rd Embodiment. It is sectional drawing which shows the manufacturing process of the heterojunction field effect transistor of 3rd Embodiment. It is sectional drawing which shows the example of 1 structure of the heterojunction field effect transistor of 3rd Embodiment. It is sectional drawing which shows the manufacturing process of the heterojunction field effect transistor of 4th Embodiment. It is sectional drawing which shows the example of 1 structure of the heterojunction field effect transistor of 4th Embodiment. It is sectional drawing which shows the example of 1 structure of the heterojunction field effect transistor of 5th Embodiment. It is sectional drawing which shows the example of 1 structure of a heterojunction field effect transistor. It is sectional drawing for demonstrating an example of the method using a diffusion technique. It is sectional drawing which shows the structural example of the heterojunction field effect transistor produced by the method demonstrated in FIG.

Explanation of symbols

101 substrate 102 GaN layer 104 AlGaN layer 105 2 DEG channel 120 polysilicon film 12, 18 n + layer 22, 23 source electrode 24, 25 drain electrode 26 gate electrode 30 implanted n + layer

Claims (11)

An electron transit layer provided on the substrate;
An electron supply layer provided on the electron transit layer;
A trench provided in the electron supply layer corresponding to each of the source electrode and the drain electrode,
A heterojunction field effect transistor, wherein a bottom surface of the trench is separated from a heterojunction that is an interface between the electron transit layer and the electron supply layer by a predetermined distance.   The heterojunction field effect transistor according to claim 1, wherein the distance between the bottom surface of the trench and the heterojunction is in the range of 5 nm to 30 nm.   The heterojunction field effect transistor according to claim 1, further comprising a first diffusion layer in contact with a bottom surface of the trench.   The heterojunction field effect transistor according to claim 3, further comprising a first diffusion layer in contact with a bottom surface and a side surface of the trench.   The heterojunction field effect transistor according to claim 3 or 4, wherein a thickness of the first diffusion layer is 10 nm or more and less than 100 nm from the trench.   A second diffusion layer having a thickness in the direction from the bottom surface of the trench toward the substrate is larger than that of the first diffusion layer, and a pattern area on a plane parallel to the upper surface of the substrate is smaller than that of the diffusion layer. The heterojunction field effect transistor according to any one of claims 3 to 5. A diffusion source containing silicon and forming the first diffusion layer is provided in contact with a bottom surface of the trench, and a metal material is provided on the diffusion source;
The heterojunction field effect transistor according to any one of claims 3 to 6, wherein the source electrode and the drain electrode are ohmic electrodes including the metal material and a silicide electrode made of silicon. An electron transit layer and an electron supply layer are sequentially formed on the substrate,
Forming a trench whose bottom surface is located at a predetermined distance from the top surface of the electron transit layer in the electron supply layer in a region corresponding to each of the source electrode and the drain electrode;
Forming a diffusion source in the trench for diffusing impurities from at least the bottom surface of the trench;
A method of manufacturing a heterojunction field effect transistor, wherein heat treatment is performed to diffuse the impurities from the diffusion source until reaching a heterojunction that is an interface between the electron transit layer and the electron supply layer.   The method of manufacturing a heterojunction field effect transistor according to claim 8, wherein the predetermined distance is in the range of 5 nm to 30 nm. After sequentially forming the electron transit layer and the electron supply layer on the substrate, and before forming the trench, the source electrode and the drain are formed in an area smaller than the cross section of the trench in a plane parallel to the upper surface of the substrate. Impurities are introduced by ion implantation to a depth that reaches the electron transit layer in a region corresponding to each of the electrodes,
The method for manufacturing a heterojunction field effect transistor according to claim 8 or 9, wherein a heat treatment for diffusing impurities introduced by the ion implantation is performed. The diffusion source comprises silicon;
Forming a metal material on at least a portion of the diffusion source in the trench;
11. The method of manufacturing a heterojunction field effect transistor according to claim 8, wherein a heat treatment is performed to form an ohmic electrode including a silicide electrode made of the metal material and the silicon as the source electrode and the drain electrode. .

Images