JP6541879B2 - Heterojunction field effect transistor and method of manufacturing the same - Google Patents

Description

  The present invention relates to a heterojunction field effect transistor made of a semiconductor containing nitride (nitride semiconductor) and a method of manufacturing the same.

  In a heterojunction field effect transistor made of a nitride semiconductor, the nitride semiconductor basically exhibits an n-type characteristic due to the influence of impurity levels formed at the time of epitaxial growth. Therefore, unless a countermeasure is taken, drain leak current (also called "buffer leak current") is generated through the bulk crystal. Therefore, for the purpose of suppressing the buffer leak current, it is generally practiced to intentionally introduce an acceptor-type impurity that compensates for the donor-type impurity into the buffer layer (for example, Patent Documents 1 and 2 below). At this time, for example, Fe, C, Zn, Mg or the like is used as the acceptor type impurity to be introduced.

JP, 2013-197357, A JP 2007-251144 A

  In the heterojunction field effect transistor made of a nitride semiconductor, the acceptor type is added when the conventional method of uniformly adding (doping) acceptor type impurities into the buffer layer in order to suppress the buffer leak current. It is necessary to increase the concentration of impurities until the buffer leak current disappears. However, the donor-type impurity levels formed at the time of epitaxial growth of the buffer layer are high concentration at the interface between the buffer layer and the substrate or at the interface formed when the conditions are changed during epitaxial growth (referred to as "growth interrupted interface"). Tend to segregate. Therefore, even if the bulk concentration is doped with an acceptor type impurity sufficient to compensate for the donor type impurity, the donor type impurity segregated at the interface can not be completely compensated, and the buffer leak current is sufficiently eliminated. I can not do it.

  Further, unnecessary acceptor type impurities form a level in the semiconductor. Therefore, if the doping concentration of the acceptor-type impurity is increased silently for the purpose of eliminating the buffer leak current, the electrons are trapped at the level formed by the acceptor-type impurity to induce current collapse, resulting in high frequency characteristics. Another problem arises of deterioration.

  The present invention has been made to solve the above problems, and it is an object of the present invention to provide a heterojunction field effect transistor capable of effectively suppressing the occurrence of buffer leak current and current collapse, and a method of manufacturing the same. I assume.

The heterojunction field effect transistor according to the present invention comprises a nitride semiconductor substrate (1), an electron supply layer (4) formed on the nitride semiconductor substrate (1), and the electron supply layer (4). And an epitaxial growth layer (2, 3, 4) made of a nitride semiconductor including the lower channel layer (3), and a drain electrode (7) and a source electrode (8) formed on the electron supply layer (4). And the electron supply layer (4), in a region between the drain electrode (7) and the source electrode (8), spaced from the drain electrode (7) and the source electrode (8). A donor-type impurity concentration Nd1 and an acceptor-type impurity concentration Na1 at the interface between the nitride semiconductor substrate (1) and the epitaxial growth layer (2, 3, 4); A donor type impurity concentration Nd2 and an acceptor type impurity in the epitaxial growth layer (2, 3, 4) Objects concentration Na2 and is pre-Symbol drain electrode (7) and only in the lower region of the source electrode ^{(8), 1.6 × 10 19} cm -3 ≧ Na1-Nd1 ≧ 0, Nd1 / 10 ≧ Nd2, Na1 The relationship of / 10 ≧ Na2 is satisfied.

  According to the present invention, the acceptor-type impurity having a sufficient concentration is introduced into the interface between the nitride semiconductor substrate and the epitaxial growth layer, so that the buffer leak current through the segregated portion of the donor-type impurity in the interface is suppressed. Can. Further, by locally introducing the acceptor type impurity into the interface between the nitride semiconductor substrate and the epitaxial growth layer, it is possible to prevent the introduction of unnecessary acceptor type impurity and to prevent an increase in current collapse. .

FIG. 1 is a view showing a structure of a heterojunction field effect transistor according to a first embodiment. It is a figure which shows an example of impurity concentration distribution with respect to the depth direction of the epitaxial growth layer in the conventional heterojunction field effect transistor. It is a figure which shows the relationship between the difference of C-Si peak concentration, and buffer leak current. FIG. 7 is a diagram showing an example of impurity concentration distribution in the depth direction of the epitaxial growth layer in the heterojunction field effect transistor according to the first embodiment. FIG. 7 is a drawing for explaining the manufacturing method of the heterojunction field effect transistor according to the first embodiment. FIG. 7 is a drawing for explaining the manufacturing method of the heterojunction field effect transistor according to the first embodiment. FIG. 7 is a drawing for explaining the manufacturing method of the heterojunction field effect transistor according to the first embodiment. FIG. 7 is a drawing for explaining the manufacturing method of the heterojunction field effect transistor according to the first embodiment. FIG. 7 is a drawing for explaining the manufacturing method of the heterojunction field effect transistor according to the first embodiment. FIG. 7 is a view showing a modified example of the heterojunction field effect transistor according to the first embodiment. FIG. 7 is a view showing a modified example of the heterojunction field effect transistor according to the first embodiment. FIG. 7 is a view showing a modified example of the heterojunction field effect transistor according to the first embodiment. FIG. 7 is a view showing a structure of a heterojunction field effect transistor according to a second embodiment.

Embodiment 1
FIG. 1 is a cross-sectional view showing an example of the configuration of the heterojunction field effect transistor according to the first embodiment of the present invention. The heterojunction field effect transistor is formed using a semi-insulating nitride semiconductor substrate 1 (hereinafter simply referred to as a "nitride semiconductor substrate") made of semi-insulating GaN. A buffer layer 2 made of GaN is formed on the nitride semiconductor substrate 1, and a channel layer 3 made of GaN is also formed on the buffer layer 2. On the channel layer 3, an electron supply layer 4 made of Al _0.17 Ga _0.83 N is formed with a thickness of 32 nm.

  Polarization charges generated by spontaneous polarization and piezoelectric polarization in the vicinity of the interface between the electron supply layer 4 and the channel layer 3 (specifically, a portion at a certain depth from the interface with the electron supply layer 4 in the channel layer 3) And a two-dimensional electron gas 11 is induced.

Here, the mixed crystal ratio of Al in the electron supply layer 4 is 0.17, and the thickness of the electron supply layer 4 is 32 nm, but the composition and thickness of the electron supply layer 4 are not limited thereto, and finally the transistor It may be adjusted according to the specifications required as For example, in the above configuration, a two-dimensional electron gas 11 of about 6.2 × 10 ¹² cm ⁻² is induced in the vicinity of the interface between the electron supply layer 4 and the channel layer 3. For example, the Al mixed crystal ratio of the electron supply layer 4 may be reduced, the thickness may be reduced, or both may be performed. Conversely, when it is desired to adjust the sheet carrier concentration of the two-dimensional electron gas 11 higher, the Al mixed crystal ratio of the electron supply layer 4 may be increased, the thickness may be increased, or both may be performed.

  Hereinafter, the nitride semiconductor layer including the buffer layer 2, the channel layer 3 and the electron supply layer 4 is generically referred to as an “epitaxial growth layer”. That is, the epitaxial growth layer includes the electron supply layer 4 as the uppermost layer, the channel layer 3 under the electron supply layer 4, and the buffer layer 2 located between the nitride semiconductor substrate 1 and the channel layer 3. It is a laminated structure containing. For example, the interface between the nitride semiconductor substrate 1 and the epitaxial growth layer indicates the interface between the nitride semiconductor substrate 1 and the buffer layer 2. However, as described later, the buffer layer 2 may not be provided in the epitaxial growth layer. In that case, since the channel layer 3 is provided in contact with the nitride semiconductor substrate 1, the interface between the nitride semiconductor substrate 1 and the epitaxial growth layer becomes the interface between the nitride semiconductor substrate 1 and the channel layer 3.

  On the top surface of the electron supply layer 4 which is the uppermost layer of the epitaxial growth layer, there are formed a drain electrode 7 and a source electrode 8 formed of a laminated film of Ti and Al (hereinafter referred to as "Ti / Al film"), and Ni and Au. A gate electrode 9 made of a laminated film (hereinafter referred to as "Ni / Au film") is disposed. The drain electrode 7 and the source electrode 8 are provided separately from each other, and the gate electrode 9 is provided separately from the drain electrode 7 and the source electrode 8 in the region between them.

The drain electrode 7 and the source electrode 8 may be made of materials other than the Ti / Al film as long as ohmic contact with the epitaxial growth layer can be obtained. For example, Ti, Al, Nb, Hf, Zr, Sr, Ni It may be a metal such as Ta, Au, Pt, Mo, W, or a multilayer film composed of two or more of them. The material of the gate electrode 9 may also be a film other than the Ni / Au film, and for example, Ti, Al, Cu, Cr, Mo, W, Pt, Au, metals such as Au, Ni, Pd, IrSi, PtSi, NiSi ₂ Or a nitride film such as TiN or WN, or a multilayer film combining them.

  In portions under the drain electrode 7 and the source electrode 8 in the epitaxial growth layer, n-type impurity implanted regions 5 and 6 to which an n-type impurity is added are formed at least in the electron supply layer 4. The upper portions of the n-type impurity implanted regions 5 and 6 reach the upper surface of the electron supply layer 4, the depth thereof is larger than the thickness of the electron supply layer 4, and the lower portion reaches the channel layer 3. Here, Si is used as the n-type impurity added to the n-type impurity implanted regions 5 and 6. However, the n-type impurity added to the n-type impurity-implanted regions 5 and 6 is not limited to Si, and other materials (O, Ge, N vacancies, etc.) that form n-type impurity levels in the nitride semiconductor It may be

  The upper surface of the electron supply layer 4 is covered with a surface protective film 10 except for the portions where the drain electrode 7, the source electrode 8 and the gate electrode 9 are formed. Here, the surface protective film 10 is formed of ECR (Electron Cyclotron Resonance) -SiN, and the thickness thereof is 80 nm.

Interface impurities exist at the interface between the nitride semiconductor substrate 1 and the epitaxial growth layer, that is, at the interface between the nitride semiconductor substrate 1 and the buffer layer 2. Of the interface impurities, only acceptor type impurities 12 (hereinafter referred to as "interface acceptor type impurities") are shown in FIG. Here, the peak concentration of the interface acceptor type impurity 12 is 1 × 10 ¹⁹ cm ⁻³ .

  FIG. 2 is a view schematically showing the results of measurement of the distribution of impurity concentration in the conventional heterojunction field effect transistor by secondary ion mass spectrometry (SIMS). FIG. 2 shows the concentration distribution of Si which is a donor type impurity and C which is an acceptor type impurity. The horizontal axis represents the depth from the upper surface of the epitaxial growth layer, and the vertical axis represents the concentration.

  In FIG. 2, it can be seen that Si and C are segregated and aggregated at the interface between the substrate and the epitaxial growth layer (at a depth of about 1.4 μm). At the interface shown in FIG. 2, the peak concentration of the donor-type impurity (Si) is about two orders of magnitude larger than the peak concentration of the acceptor-type impurity (C). In this case, buffer leak current at the interface is induced. FIG. 3 shows the relationship between the difference in peak concentration between C and Si and the magnitude of the buffer leak current. It can be seen that when the peak concentration of Si becomes larger than the peak concentration of C, the buffer leak current increases.

  The aggregation of the impurities is considered to be the result of taking in the impurities derived from atmospheric transportation until the substrate is introduced into the epitaxial growth furnace, and the impurities derived from the atmosphere when growing the epitaxial growth layer. Therefore, the concentration distribution of each impurity changes by changing the conditions for cleaning the substrate and the conditions for epitaxial growth.

  FIG. 4 is a view schematically showing the results of measurement of the impurity concentration distribution in the heterojunction field effect transistor according to the first embodiment by SIMS. Also in FIG. 4, Si and C are segregated and aggregated at the interface between the nitride semiconductor substrate and the epitaxial growth layer (at a depth of about 1.2 μm), but unlike FIG. The peak concentration of the impurity (C) is about one digit larger than the peak concentration of the donor type impurity (Si).

  The difference between the peak concentration of the acceptor-type impurity and the peak concentration of the donor-type impurity may be less than one digit, as long as the acceptor-type impurity is introduced more than the donor-type impurity. That is, assuming that the donor-type impurity concentration at the interface between nitride semiconductor substrate 1 and the epitaxial growth layer (the interface between nitride semiconductor substrate 1 and buffer layer 2) is Nd1 and the acceptor-type impurity concentration Na1 at the same interface, then Na1 Nd Nd1. It suffices to satisfy the relationship (that is, the relationship of Na1−Nd1 ≧ 0).

Further, as shown in FIG. 3, the leak current can be suppressed if Na1 is increased to increase the value of Na1-Nd1, but if Na1 becomes extremely large, an increase in current collapse can not be avoided. As a result of the present inventors repeating studies on the dependence of Na1-Nd1 on current collapse, it is found that the characteristic degradation due to current collapse becomes unacceptable when Na1-Nd1> 1.6 × 10 ¹⁹ cm ⁻³ is satisfied. I understand. That is, from the viewpoint of current collapse suppression, Na1 and Nd1 may be set to satisfy the relationship of 1.6 × 10 ¹⁹ cm ⁻³ NaNa 1 −Nd 1.

  Here, since the donor type impurity and the acceptor type impurity are segregated and aggregated at the interface between the nitride semiconductor substrate 1 and the epitaxial growth layer, the concentration of the donor type impurity and the acceptor type impurity at the interface is the epitaxial growth layer Are more than an order of magnitude higher than their concentrations in That is, when the donor-type impurity concentration and the acceptor-type impurity concentration in the epitaxial growth layer are Nd2 and Na2, respectively, Nd1 / 10 ≧ Nd2 and Na1 / 10 ≧ Na2 hold.

The absolute value of the acceptor-type impurity concentration does not have a large meaning because whether the relationship Na1 ≧ Nd1 is satisfied also depends on the concentration of the donor-type impurity. For example, the peak concentration of the acceptor-type impurity is 2 × It is good to add an acceptor type impurity so that it may be 10 ^{< 18} > cm ^<-3 >. However, if the relationship between the impurity concentrations is defined only by the peak concentration of the bulk, the amount of acceptor-type impurities and the amount of donor-type impurities in the vicinity of the interface are reversed when there is a distribution in the film thickness direction. Is also conceivable. Therefore, it is desirable that the acceptor type impurity be added in the same amount or more as the donor type impurity at the sheet concentration.

  Further, as shown in FIG. 4, the concentration of the acceptor-type impurity (C) is larger than the concentration of the donor-type impurity (Si) even in a region shallower than the interface between the nitride semiconductor substrate 1 and the epitaxial growth layer. There is. Therefore, assuming that the donor-type impurity concentration at the interface between the buffer layer 2 and the channel layer 3 is Nd3 and the acceptor-type impurity concentration is Na3, the relationship of Na3 ≧ Nd3 is established.

In FIG. 4, the concentration of C is locally increased in the vicinity of a depth of 0.8 μm to 1.2 μm, and the concentration of C has a terrace-like distribution in that region. This is because the buffer layer 2 was intentionally doped with C by 3 × 10 ¹⁶ cm ⁻³ . In the GaN-based crystal, N vacancies introduced as crystal defects are present, and the N vacancies function as donor-type impurities, and therefore exhibit characteristics closer to n-type if intentional doping is not performed. Therefore, C is intentionally introduced as a low concentration acceptor type impurity in order to compensate the donor type impurity. In particular, in the present invention, in order to compensate the impurity aggregation at the interface between the substrate and the epitaxial growth layer, the acceptor type impurity is locally doped at the peak concentration exceeding the concentration of the donor type impurity. This is different from the prior art (for example, Patent Documents 1 and 2).

  According to the heterojunction field effect transistor of the present embodiment, a buffer caused by a donor-type impurity aggregated at the interface between the nitride semiconductor substrate 1 and the epitaxial growth layer due to an acceptor-type impurity introduced at a high concentration Leakage current can be suppressed. Furthermore, the region in which the acceptor type impurity is introduced at a high concentration is limited to the vicinity of the interface with the epitaxial growth layer (the region with a depth of 0.8 μm to 1.2 μm in FIG. 4). It is possible to prevent the acceptor type impurity concentration from becoming higher than necessary, and to suppress the occurrence of current collapse. Therefore, it is possible to improve the electrical characteristics of the heterojunction field effect transistor made of a nitride semiconductor.

  5 to 9 are views for explaining a method of manufacturing the heterojunction field effect transistor shown in FIG. In these figures, the same or corresponding elements as those shown in FIG. 1 are denoted by the same reference numerals.

First, nitride semiconductor substrate 1 is placed in an epitaxial growth apparatus, and GaN is grown on nitride semiconductor substrate 1 using epitaxial growth methods such as MOCVD (Metal Organic Chemical Vapor Deposition) and MBE (Molecular Beam Epitaxy). Buffer layer 2 is formed. At this time, the growth conditions of buffer layer 2 such that the amount of acceptor type impurities is larger than that of donor type impurities at the interface between nitride semiconductor substrate 1 and buffer layer 2 (the interface between nitride semiconductor substrate 1 and epitaxial growth layer). Adjust the Subsequently, the channel layer 3 made of GaN is epitaxially grown on the buffer layer 2. At this time, the growth condition of the channel layer 3 is adjusted so that the acceptor type impurity is more than the donor type impurity at the interface between the buffer layer 2 and the channel layer 3. Further, the electron supply layer 4 made of Al _0.17 Ga _0.83 N is epitaxially grown on the channel layer 3. As a result, as shown in FIG. 5, an epitaxial growth layer including buffer layer 2, channel layer 3 and electron supply layer 4 is formed.

The nitride semiconductor substrate 1 on which the buffer layer 2, the channel layer 3 and the electron supply layer 4 are formed is taken out from the epitaxial growth apparatus. Then, a resist mask 14 having an opening in the formation region of the drain electrode 7 and the source electrode 8 is formed on the electron supply layer 4 using a photolithography technique. Then, by ion implantation using the resist mask 14 as a mask, an n-type impurity such as Si is used as an epitaxial growth layer under the conditions of an implantation dose of 1 × 10 ¹³ to 1 × 10 ¹⁷ cm ⁻² and an implantation energy of 10 to 1000 keV. Introduce. Thereby, n-type impurity implanted regions 5 and 6 are formed as shown in FIG.

  After the resist mask 14 is removed, a metal such as Ti, Al, Nb, Hf, Zr, Sr, Ni, Ta, Au, Mo, W, or two or more thereof is used, for example, by vapor deposition or sputtering. A multilayer film including the above is deposited on the electron supply layer 4, and the drain electrode 7 and the source electrode 8 are formed as shown in FIG. 7 by using a lift-off method or a photolithography method.

Next, a metal such as Ti, Al, Cu, Cr, Mo, W, Pt, Au, Ni, Pd, a silicide such as IrSi, PtSi, NiSi ₂ or TiN using, for example, a vapor deposition method or a sputtering method. A nitride metal such as WN is deposited on the electron supply layer 4, and a gate electrode 9 is formed as shown in FIG. 8 by using a lift-off method or a photolithography method.

  Thereafter, a surface protection film 10 is formed on the surface of the electron supply layer 4 made of an oxide film or a nitride film of Si or Al, using a film forming method having high coverage, such as ALD (Atomic Layer Deposition) method. Then, the surface protective film 10 is patterned by dry etching or the like so that the drain electrode 7, the source electrode 8 and the gate electrode 9 are exposed from the surface protective film 10. Thereby, as shown in FIG. 9, the surface protective film 10 covering the surface of the electron supply layer 4 is formed. The formation method of the surface protective film 10 is not limited to the ALD method, and other methods such as PECVD (Plasma Enhanced Chemical Vapor Deposition) method and sputtering method may be used, or a combination of them may be used.

  Through the above steps, the configuration of the heterojunction field effect transistor shown in FIG. 1 is formed. Thereafter, through processes for forming interconnections, via holes and the like, a heterojunction field effect transistor as a semiconductor device is completed.

  In the above description, the typical structure of the heterojunction field effect transistor is described, but the following modifications can be considered.

Assuming that the size of the band gap of the channel layer 3 is E ₃ and the size of the band gap of the electron supply layer 4 is E ₄ , the heterojunction field effect transistor is operated if the relationship of E ₃ <E ₄ is satisfied. Is enough. Therefore, the nitride semiconductor substrate 1, the buffer layer 2, and the channel layer 3 may not necessarily be formed of GaN, and the electron supply layer 4 may not be formed of Al _0.17 Ga _0.83 N. If the channel layer 3 and the electron supply layer 4 have mutually different compositions of elements constituting them, and are made of a compound composed of two or more types of elements including N of Al, Ga and N Good. For example, the nitride semiconductor substrate 1, the buffer layer 2 and the channel layer 3 may also be formed of a material having Al _x Ga ₁ -xN (0 ≦ x ≦ 1) as a main component.

In order to satisfy the relationship of E ₃ <E ₄ , the nitride semiconductor constituting the channel layer 3 is Al _x Ga _1-x N, and the nitride semiconductor constituting the electron supply layer 4 is Al _y Ga _1-y N. Then, the relationships of 0 ≦ x <1, 0 <y <1, and x <y may be satisfied. Furthermore, the channel layer 3 and the electron supply layer 4 may be made of a nitride semiconductor obtained by adding In to an element of two or more elements including N among Al, Ga and N.

  The channel layer 3 and the electron supply layer 4 made of various nitride semiconductors as described above are, in the growth process thereof, trimethylammonium, trimethylgallium, trimethylindium, ammonia, or n-type dopant which is a raw material gas of the nitride semiconductor The channel layer 3 and the electron supply layer 4 are formed by adjusting the pressure, flow rate, temperature, and introduction time of silane, etc., which is the raw material gas, to obtain desired composition, film thickness, and doping concentration. Can.

  When the channel layer 3 and the electron supply layer 4 are composed of a compound composed of two or more elements including N of Al, Ga and N, a large polarization effect occurs in the electron supply layer 4, so high concentration is achieved. The two-dimensional electron gas 11 can be generated. When the concentration of the two-dimensional electron gas 11 is high, it is advantageous to increase the current of the transistor and further increase the output. However, the binary crystal of AlN can not be adopted only for the channel layer 3. This is because there is no material having a band gap larger than that of AlN in the nitride semiconductor, and there is no material that can be used for the electron supply layer 4.

As the dielectric breakdown field of the channel layer 3 is higher, the breakdown voltage of the heterojunction field effect transistor is higher. Al _x Ga _1-x N, the higher Al composition is higher, the greater the band gap, since the breakdown electric field increases, the _Al x _{Ga 1-x} N to be used for the channel layer 3, Al composition higher (x Is closer to 1). Further, as the band gap of the electron supply layer 4 is larger, the gate leak current flowing from the gate electrode 9 to the hetero interface through the electron supply layer 4 can be suppressed, and therefore Al _y Ga _1-y N used for the electron supply layer 4 is also The higher the Al composition (y is closer to 1), the better.

  The cross-sectional shape of the gate electrode 9 does not have to be rectangular as shown in FIG. 1, and may be, for example, a T-shape, a Y-shape, or a bowl shape. Further, as shown in FIG. 10, a field plate electrode 13 may be provided which is electrically connected to the gate electrode 9 and extends over the surface protective film 10. Although FIG. 10 shows a configuration in which the field plate electrode 13 extends from the gate electrode 9 to the drain electrode 7 side, the field plate electrode 13 may be provided to extend to the source electrode 8 side. It may be provided to extend to both the 7 side and the source electrode 8 side. By providing the field plate electrode 13, it is possible to suppress the concentration of the electric field at the end of the gate electrode 9, which is effective in reducing the current collapse. The material of field plate electrode 13 may be any material as long as it can be electrically connected to gate electrode 9 and can be formed so as not to be in contact with the epitaxial growth layer.

  The field plate electrode 13 is formed by forming the surface protection film 10 and then forming a conductive film to be the material of the field plate electrode 13 by vapor deposition or the like, and using the lift-off method or the like to form the conductive film. It can be carried out by processing into a desired pattern.

  The nitride semiconductor substrate 1 may be formed of AlN, InN, a mixed crystal of these, or the like. However, it is difficult to continuously grow crystals having different lattice constants, and it is necessary to consider the influence on buffer leak current by inserting a lattice strain relaxation layer into an epitaxial growth layer, or the like. Therefore, it is preferable that the lattice constant of the nitride semiconductor substrate 1 and the lattice constant of the buffer layer 2 and the channel layer 3 be equal. Further, from the viewpoint of lattice strain relaxation, the channel layer 3 and the electron supply layer 4 can be formed without forming the buffer layer 2 on the nitride semiconductor substrate 1. That is, the buffer layer 2 need not necessarily be formed on the nitride semiconductor substrate 1 and may not be formed.

Each of the channel layer 3 and the electron supply layer 4 does not necessarily have to be a single layer structure of a single composition, and the channel layer 3 and the electron supply can be provided as long as the band gap size condition (E ₃ <E ₄ ) is satisfied. The In composition, the Al composition, and the Ga composition may be spatially changed in the layer 4, or the channel layer 3 and the electron supply layer 4 may have a multilayer structure including a plurality of layers having different compositions. The channel layer 3 and the electron supply layer 4 may contain an impurity that exhibits n-type or p-type in the nitride semiconductor.

  In FIG. 1, the interface acceptor type impurity 12 is shown only at the interface between the nitride semiconductor substrate 1 and the buffer layer 2, but the introduction site of the interface acceptor type impurity is the nitride semiconductor substrate 1 and the buffer layer 2. Not only at the interface of As described above, when the nitride semiconductor substrate 1 and the buffer layer 2 use materials having different lattice constants, a lattice strain relaxation layer may be inserted into the epitaxial growth layer. In that case, the process may be interrupted during epitaxial growth, and depending on the conditions, aggregation of impurities may occur even at the interface (growth interrupted interface) generated by the interruption. In such a case, it may be better to introduce an acceptor-type impurity also to the interface between the buffer layer 2 and the channel layer 3.

  If the drain electrode 7 and the source electrode 8 form an ohmic contact with the two-dimensional electron gas 11 generated near the interface between the electron supply layer 4 and the channel layer 3, as shown in FIG. The n-type impurity implantation regions 5 and 6 may not be provided below the source electrode 8. The drain electrode 7 and the source electrode 8 may be provided to be in contact with the upper surface of the electron supply layer 4 as shown in FIG. 11, or the electron supply in the recess formed in the electron supply layer 4 as shown in FIG. It may be provided in contact with the layer 4. However, if the n-type impurity-implanted regions 5 and 6 are formed under the drain electrode 7 and the source electrode 8, the resistance between the drain electrode 7 and the source electrode 8 and the two-dimensional electron gas 11 is reduced. Can be used to increase the current and the output of the transistor.

The configuration of FIG. 11 can be formed by omitting the ion implantation of the n-type impurity shown in FIG. Further, the configuration of FIG. 12 can be formed by performing a step of selectively removing the electron supply layer 4 using, for example, a Cl ₂ -based etching gas, instead of the step shown in FIG.

  In addition, each modification mentioned above can also be implemented in combination with each other.

Second Embodiment
FIG. 13 is a diagram showing the structure of the heterojunction field effect transistor according to the second embodiment. In FIG. 13, the arrangement of interface acceptor type impurity 12 present at the interface between nitride semiconductor substrate 1 and buffer layer 2 is different from that of the first embodiment. That is, in the first embodiment, the interface acceptor type impurity 12 for only compensating for the donor type impurity is uniformly added over the entire interface, but in the second embodiment, the lower side of the drain electrode 7 and the source electrode 8 (n The interface acceptor type impurity 12 is added only to the lower part of the type impurity implantation regions 5 and 6). Therefore, in the present embodiment, the relationship between the donor-type impurity concentration and the acceptor-type impurity concentration described above only in the region under the drain electrode 7 and the source electrode 8, ie, 1.6 × 10 ¹⁹ cm ⁻³ NaNa 1 − The relationships of Nd1 ≧ 0, Nd1 / 10 ≧ Nd2, and Na1 / 10 ≧ Na2 are satisfied.

  In the heterojunction field effect transistor of FIG. 13, the buffer leak current from the n-type impurity implanted regions 5 and 6 through the segregated portion of the donor type impurity at the interface between the nitride semiconductor substrate 1 and the buffer layer 2 is an interface acceptor. It is reduced by the type impurity 12. Furthermore, an access region from source electrode 8 to drain electrode 7 (refers to a region between drain electrode 7 and gate electrode 9 in channel layer 3 and a region between source electrode 8 and gate electrode 9) and a channel region Immediately below (the region under the gate electrode 9), the interface acceptor type impurity 12 is absent, so that the electron capture probability can be reduced, whereby current collapse can be suppressed. Therefore, current collapse can be suppressed more than in the first embodiment.

  Further, in FIG. 13, the interface acceptor type impurity 12 is shown only in the region under the drain electrode 7 and the source electrode 8, but the interface acceptor type impurity 12 is at least under the drain electrode 7 and the source electrode 8. It should be covered. In particular, from the viewpoint of suppressing current collapse, it is sufficient to reduce electron capture in a region to which a high electric field is applied, and thus the interface acceptor type impurity 12 is extended to the region between the source electrode 8 and the gate electrode 9. There is no major impact. In addition, the interface acceptor type impurity 12 must not be present at all except in the region under the drain electrode 7 and the source electrode 8, but in the region under the drain electrode 7 and the source electrode 8 and the other regions. If the interface acceptor impurity 12 has a concentration difference, a certain effect can be expected.

  The structure of FIG. 13 is realized, for example, by selectively implanting the acceptor-type impurity element in the formation region of the interface acceptor-type impurity 12 in the nitride semiconductor substrate 1 before the step of forming the epitaxial growth layer. Can. Specifically, it is conceivable to form a resist mask having an opening on the formation region of interface acceptor impurity 12 on nitride semiconductor substrate 1 and implant the acceptor impurity element by ion implantation using the resist mask as a mask. .

  Each modification described in the first embodiment is also applicable to the heterojunction field effect transistor of the second embodiment.

  In the present invention, within the scope of the invention, each embodiment can be freely combined, or each embodiment can be appropriately modified or omitted.

  Reference Signs List 1 nitride semiconductor substrate, 2 buffer layer, 3 channel layer, 4 electron supply layer, 5 n-type impurity injection region, 6 n-type impurity injection region, 7 drain electrode, 8 source electrode, 9 gate electrode, 10 surface protective film, 11 two-dimensional electron gas, 12 interface acceptor type impurity, 13 field plate electrode, 14 resist mask.

Claims (8)

A nitride semiconductor substrate (1),
An epitaxially grown layer (2, 2) formed on the nitride semiconductor substrate (1), comprising an electron supply layer (4) as the uppermost layer and a channel layer (3) under the electron supply layer (4) 3, 4),
A drain electrode (7) and a source electrode (8) formed on the electron supply layer (4);
It is formed on the electron supply layer (4), and it is spaced apart from the drain electrode (7) and the source electrode (8) in the region between the drain electrode (7) and the source electrode (8). A gate electrode (9) provided,
Equipped with
Donor-type impurity concentration Nd1 and acceptor-type impurity concentration Na1 at the interface between the nitride semiconductor substrate (1) and the epitaxial growth layer (2, 3, 4) and donor-type impurity in the epitaxial growth layer (2, 3, 4) and density Nd2 and acceptor-type impurity concentration Na2 is, only in the lower region of the front Symbol drain electrode (7) and the source electrode ^{(8), 1.6 × 10 19} cm -3 ≧ Na1-Nd1 ≧ 0, Nd1 / Satisfy the following relationship: 10 ≧ Nd2, Na1 / 10 ≧ Na2
Heterojunction field effect transistor. The acceptor-type impurity concentration in the epitaxial growth layer (2, 3, 4) is pre-SL only in the region below the drain electrode (7) and the source electrode (8), the epitaxially grown layer and the nitride semiconductor substrate (1) ( 2. A heterojunction field effect transistor according to claim 1, wherein the heterojunction field effect transistor is locally high near the interface with (2, 3, 4). The heterojunction field effect according to claim 1 or 2, wherein the nitride semiconductor substrate (1) and the channel layer (3) contain Al _x Ga _1-x N (0 ≦ x <1) as main components. Type transistor. The epitaxial growth layer (2, 3, 4) further includes a buffer layer (2) located between the nitride semiconductor substrate (1) and the channel layer (3).
The donor-type impurity concentration Nd3 and the acceptor-type impurity concentration Na3 at the interface between the buffer layer (2) and the channel layer (3) satisfy the relationship Na33Nd3.
A heterojunction field effect transistor according to claim 1 or claim 2. The hetero according to claim 4, wherein the nitride semiconductor substrate (1), the buffer layer (2) and the channel layer (3) contain Al _x Ga _1-x N (0 ≦ x <1) as main components. Junction field effect transistor. Epitaxial growth layers (2, 3, 4) made of a nitride semiconductor including a top electron supply layer (4) and a channel layer (3) under the electron supply layer (4) on a nitride semiconductor substrate (1) Forming a)
Forming a drain electrode (7), a source electrode (8) and a gate electrode (9) on the electron supply layer (4),
In the step of forming the epitaxial growth layer (2, 3, 4), a donor-type impurity concentration Nd1 and an acceptor-type impurity concentration Na1 at the interface between the nitride semiconductor substrate (1) and the epitaxial growth layer (2, 3, 4) the epitaxial growth layer (2, 3, 4) and the donor-type impurity concentration Nd2 and acceptor-type impurity concentration Na2 in is only before SL below the region of the formation region of the drain electrode (7) and the source electrode (8), The epitaxial growth layers (2, 3, 4) are formed so as to satisfy the relationship of 1.6 × 10 ¹⁹ cm ⁻³ NaNa 1 −Nd 1 ≦ 0, Nd 1/10 ≦ Nd 2, and Na 1/10 ≦ Na 2.
Method of manufacturing a heterojunction field effect transistor Wherein in the step of forming the epitaxial growth layer (2, 3, 4), the epitaxially grown layer acceptor-type impurity concentration in the (2,3,4), the lower region of the front Symbol drain electrode (7) and the source electrode (8) The epitaxial growth layer (2, 3, 4) is formed so as to be locally high near the interface between the nitride semiconductor substrate (1) and the epitaxial growth layer (2, 3, 4) only in
A method of manufacturing a heterojunction field effect transistor according to claim 6 . The epitaxial growth layer (2, 3, 4) further includes a buffer layer (2) located between the nitride semiconductor substrate (1) and the channel layer (3).
In the step of forming the epitaxial growth layers (2, 3, 4),
Forming a buffer layer (2) on the nitride semiconductor substrate (1);
Forming the channel layer (3) on the buffer layer (2);
Forming the electron supply layer (4) on the channel layer (3);
Contains and
In the step of forming the channel layer (3), the donor type impurity concentration Nd3 and the acceptor type impurity concentration Na3 at the interface between the buffer layer (2) and the channel layer (3) satisfy the relationship Na3 Nd Nd3. , The channel layer (3) is formed
A method of manufacturing a heterojunction field effect transistor according to claim 6 or 7 .

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