WO2017221532A1

WO2017221532A1 - Heterojunction fet transistor and method for manufacturing same

Info

Publication number: WO2017221532A1
Application number: PCT/JP2017/015420
Authority: WO
Inventors: 章文今井; 南條　拓真; 吹田　宗義; 喬松田; 健一郎倉橋; 柳生　栄治
Original assignee: 三菱電機株式会社
Priority date: 2016-06-24
Filing date: 2017-04-17
Publication date: 2017-12-28
Also published as: JPWO2017221532A1; JP6541879B2

Abstract

A heterojunction FET transistor comprises: a nitride semiconductor substrate (1); and epitaxial growth layers including a buffer layer (2) that is formed on the nitride semiconductor substrate (1), a channel layer (3) that is formed on the buffer layer (2), and an electron supply layer (4) that is formed on the channel layer (3). A drain electrode (7), a source electrode (8), and a gate electrode (9) disposed in the region therebetween are formed on the electron supply layer (4). A donor impurity concentration Nd1 and an acceptor impurity concentration Na1, which are at the interface between the nitride semiconductor substrate (1) and the epitaxial growth layers, i.e., the interface between the nitride semiconductor substrate (1) and the buffer layer (2), and a donor impurity concentration Nd2 and an acceptor impurity concentration Na2, which are in the epitaxial growth layers (2, 3, 4), satisfy the following relationships: 1.6×10¹⁹cm^-3 ≥ Na1-Nd1 ≥ 0, Nd1/10 ≥ Nd2, and Na1/10 ≥ Na2.

Description

Heterojunction field effect transistor and method of manufacturing the same

The present invention relates to a heterojunction field effect transistor made of a semiconductor containing nitride (nitride semiconductor) and a method for manufacturing the same.

In a heterojunction field effect transistor made of a nitride semiconductor, the nitride semiconductor basically exhibits an n-type characteristic due to the influence of impurity levels formed during epitaxial growth. Therefore, unless special measures are taken, drain leakage current (also called “buffer leakage current”) occurs through the bulk crystal. Therefore, for the purpose of suppressing the buffer leakage current, acceptor-type impurities that compensate donor-type impurities are generally intentionally introduced into the buffer layer (for example,

Patent Documents

1 and 2 below). At that time, for example, Fe, C, Zn, Mg, or the like is used as an acceptor type impurity to be introduced.

JP 2013-1973357 A JP 2007-251144 A

In a heterojunction field effect transistor made of a nitride semiconductor, in order to suppress buffer leakage current, an acceptor type to be added when an acceptor type impurity is uniformly added (doping) into a buffer layer is adopted. It is necessary to increase the impurity concentration until the buffer leakage current disappears. However, the donor-type impurity level formed during the epitaxial growth of the buffer layer is a high concentration at the interface between the buffer layer and the substrate or when the conditions are changed during epitaxial growth (called the “growth interruption interface”). Tend to segregate. Therefore, even if an acceptor-type impurity is added in a sufficient amount to compensate for the donor-type impurity as a bulk concentration, the donor-type impurity segregated at the interface cannot be completely compensated, and the buffer leakage current is sufficiently eliminated. I can't.

Further, unnecessary acceptor-type impurities form a level in the semiconductor. For this reason, if the doping concentration of the acceptor-type impurity is increased in an effort to eliminate the buffer leak current, electrons are trapped in the level formed by the acceptor-type impurity and current collapse is induced, resulting in high frequency characteristics. Another problem of deteriorating arises.

The present invention has been made to solve the above-described problems, and it is an object of the present invention to provide a heterojunction field effect transistor capable of effectively suppressing the occurrence of buffer leakage current and current collapse and a method for manufacturing the same. And

A heterojunction field effect transistor according to the present invention is formed on a nitride semiconductor substrate (1), the nitride semiconductor substrate (1), and an uppermost electron supply layer (4) and the electron supply layer (4 ) Epitaxial growth layers (2, 3, 4) made of a nitride semiconductor including a channel layer (3) below, and a drain electrode (7) and a source electrode (8) formed on the electron supply layer (4) And formed on the electron supply layer (4) and spaced from the drain electrode (7) and the source electrode (8) in a region between the drain electrode (7) and the source electrode (8). A donor electrode impurity concentration Nd1 and an acceptor impurity concentration Na1 at the interface between the nitride semiconductor substrate (1) and the epitaxial growth layer (2, 3, 4), , Donor-type impurity concentration Nd2 and acceptor-type impurity in the epitaxial growth layer (2, 3, 4) It objects concentration Na2 and is, at least in the lower region of the drain electrode (7) and the source electrode ^{(8), 1.6 × 10 19} cm -3 ≧ Na1-Nd1 ≧ 0, Nd1 / 10 ≧ Nd2, Na1 / The relationship of 10 ≧ Na2 is satisfied.

According to the present invention, since acceptor-type impurities having a sufficient concentration are introduced into the interface between the nitride semiconductor substrate and the epitaxial growth layer, it is possible to suppress the buffer leak current through the segregated portion of the donor-type impurities at the interface. Can do. Further, by introducing acceptor impurities locally at the interface between the nitride semiconductor substrate and the epitaxial growth layer, unnecessary acceptor impurities can be prevented from being introduced, and an increase in current collapse can be prevented. .

1 is a diagram illustrating a structure of a heterojunction field effect transistor according to a first embodiment. It is a figure which shows an example of impurity concentration distribution with respect to the depth direction of an epitaxial growth layer in the conventional heterojunction field effect transistor. It is a figure which shows the relationship between the difference of C-Si peak density | concentration, and a buffer leak current. 6 is a diagram showing an example of an impurity concentration distribution in a depth direction of an epitaxial growth layer in the heterojunction field effect transistor according to the first embodiment. FIG. FIG. 6 is a diagram for explaining the method of manufacturing the heterojunction field effect transistor according to the first embodiment. FIG. 6 is a diagram for explaining the method of manufacturing the heterojunction field effect transistor according to the first embodiment. FIG. 6 is a diagram for explaining the method of manufacturing the heterojunction field effect transistor according to the first embodiment. FIG. 6 is a diagram for explaining the method of manufacturing the heterojunction field effect transistor according to the first embodiment. FIG. 6 is a diagram for explaining the method of manufacturing the heterojunction field effect transistor according to the first embodiment. 6 is a diagram showing a modification of the heterojunction field effect transistor according to the first embodiment. FIG. 6 is a diagram showing a modification of the heterojunction field effect transistor according to the first embodiment. FIG. 6 is a diagram showing a modification of the heterojunction field effect transistor according to the first embodiment. FIG. FIG. 6 is a diagram showing a structure of a heterojunction field effect transistor according to a second embodiment.

<Embodiment 1>
FIG. 1 is a cross-sectional view showing an example of the configuration of a heterojunction field effect transistor according to Embodiment 1 of the present invention. This heterojunction field effect transistor is formed using a semi-insulating nitride semiconductor substrate 1 made of semi-insulating GaN (hereinafter simply referred to as “nitride semiconductor substrate”). A buffer layer 2 made of GaN is formed on the nitride semiconductor substrate 1, and a channel layer 3 made of GaN is also formed on the buffer layer 2. On the channel layer 3, an electron supply layer 4 made of Al _0.17 Ga _0.83 N is formed with a thickness of 32 nm.

In the vicinity of the interface between the electron supply layer 4 and the channel layer 3 (specifically, in the channel layer 3 at a certain depth from the interface with the electron supply layer 4), polarization charges generated by spontaneous polarization and piezoelectric polarization are generated. A two-dimensional electron gas 11 consisting of is induced.

Here, the mixed crystal ratio of Al in the electron supply layer 4 is 0.17, and the thickness of the electron supply layer 4 is 32 nm. However, the composition and thickness of the electron supply layer 4 are not limited to this, and finally the transistor May be adjusted according to the required specifications. For example, in the above configuration, a two-dimensional electron gas 11 of about 6.2 × 10 ¹² cm ⁻² is induced near the interface between the electron supply layer 4 and the channel layer 3, but the sheet carrier concentration may be adjusted to be smaller. For example, the Al mixed crystal ratio of the electron supply layer 4 may be reduced, the thickness may be reduced, or both. Conversely, when it is desired to adjust the sheet carrier concentration of the two-dimensional electron gas 11 higher, the Al mixed crystal ratio of the electron supply layer 4 may be increased, the thickness may be increased, or both.

Hereinafter, the nitride semiconductor layer composed of the buffer layer 2, the channel layer 3, and the electron supply layer 4 is collectively referred to as an “epitaxial growth layer”. That is, the epitaxial growth layer includes an uppermost electron supply layer 4, a channel layer 3 below the electron supply layer 4, and a buffer layer 2 positioned between the nitride semiconductor substrate 1 and the channel layer 3. It is a laminated structure including. For example, the interface between the nitride semiconductor substrate 1 and the epitaxial growth layer indicates the interface between the nitride semiconductor substrate 1 and the buffer layer 2. However, as will be described later, the buffer layer 2 may not be provided in the epitaxial growth layer. In that case, since the channel layer 3 is provided so as to be in contact with the nitride semiconductor substrate 1, the interface between the nitride semiconductor substrate 1 and the epitaxial growth layer becomes the interface between the nitride semiconductor substrate 1 and the channel layer 3.

On the upper surface of the electron supply layer 4 which is the uppermost layer of the epitaxial growth layer, a drain electrode 7 and a source electrode 8 made of a laminated film of Ti and Al (hereinafter referred to as “Ti / Al film”), and Ni and Au A gate electrode 9 made of a laminated film (hereinafter referred to as “Ni / Au film”) is provided. The drain electrode 7 and the source electrode 8 are provided apart from each other, and the gate electrode 9 is provided apart from the drain electrode 7 and the source electrode 8 in a region therebetween.

The drain electrode 7 and the source electrode 8 may be made of a material other than the Ti / Al film as long as ohmic contact with the epitaxial growth layer is obtained. For example, Ti, Al, Nb, Hf, Zr, Sr, Ni , Ta, Au, Pt, Mo, W, or a metal, or a multilayer film composed of two or more thereof. The material of the gate electrode 9 may be other than Ni / Au film, for example, metal such as Ti, Al, Cu, Cr, Mo, W, Pt, Au, Ni, Pd, IrSi, PtSi, NiSi _2. Or a nitride metal such as TiN or WN, or a multilayer film combining them.

In the epitaxial growth layer, n-type

impurity implantation regions

5 and 6 to which an n-type impurity is added are formed at least in the electron supply layer 4 below the drain electrode 7 and the source electrode 8. In the n-type

impurity implantation regions

5 and 6, the upper part reaches the upper surface of the electron supply layer 4, the depth is larger than the thickness of the electron supply layer 4, and the bottom part reaches the channel layer 3. Here, Si is used as an n-type impurity added to the n-type

impurity implantation regions

5 and 6. However, the n-type impurity added to the n-type

impurity implantation regions

5 and 6 is not limited to Si, and other materials that form n-type impurity levels in the nitride semiconductor (O, Ge, N vacancies, etc.) It may be.

The upper surface of the electron supply layer 4 is covered with a surface protective film 10 except for the portion where the drain electrode 7, the source electrode 8 and the gate electrode 9 are formed. Here, the surface protective film 10 is made of ECR (Electron Cyclotron Resonance) -SiN and has a thickness of 80 nm.

Interfacial impurities exist at the interface between nitride semiconductor substrate 1 and the epitaxial growth layer, that is, at the interface between nitride semiconductor substrate 1 and buffer layer 2. FIG. 1 shows only acceptor impurities 12 (hereinafter referred to as “interface acceptor impurities”) among interface impurities. Here, the peak concentration of the interface acceptor impurity 12 is set to 1 × 10 ¹⁹ cm ⁻³ .

FIG. 2 is a diagram schematically showing the results of measuring the impurity concentration distribution in a conventional heterojunction field effect transistor by secondary ion mass spectrometry (Secondary-Ion-Mass-Spectrometry: SIMS). FIG. 2 shows the concentration distribution of Si, which is a donor-type impurity, and C, which is an acceptor-type impurity. The horizontal axis represents the depth from the upper surface of the epitaxial growth layer, and the vertical axis represents the concentration.

In FIG. 2, it can be seen that Si and C are segregated and aggregated at the interface between the substrate and the epitaxial growth layer (the depth is about 1.4 μm). At the interface shown in FIG. 2, the peak concentration of the donor-type impurity (Si) is about two orders of magnitude higher than the peak concentration of the acceptor-type impurity (C). In this case, a buffer leak current at the interface is induced. FIG. 3 shows the relationship between the difference between the peak concentrations of C and Si and the magnitude of the buffer leakage current. It can be seen that the buffer leakage current increases when the Si peak concentration is higher than the C peak concentration.

The aggregation of impurities is considered to be a result of incorporating impurities derived from atmospheric conveyance until the substrate is introduced into the epitaxial growth furnace and impurities derived from the atmosphere when growing the epitaxial growth layer. Therefore, the concentration distribution of each impurity changes by changing the conditions for cleaning the substrate and the conditions for epitaxial growth.

FIG. 4 is a diagram schematically showing the result of actually measuring the impurity concentration distribution in the heterojunction field effect transistor according to the first embodiment by SIMS. Also in FIG. 4, Si and C are segregated and aggregated at the interface between the nitride semiconductor substrate and the epitaxial growth layer (the depth is about 1.2 μm). The peak concentration of the impurity (C) is about an order of magnitude higher than the peak concentration of the donor-type impurity (Si).

The difference between the peak concentration of the acceptor-type impurity and the peak concentration of the donor-type impurity may be no more than one digit, and the acceptor-type impurity may be introduced more than the donor-type impurity. That is, assuming that the donor-type impurity concentration at the interface between the nitride semiconductor substrate 1 and the epitaxial growth layer (the interface between the nitride semiconductor substrate 1 and the buffer layer 2) is Nd1, and the acceptor-type impurity concentration Na1 at the interface is Na1 ≧ Nd1 It is only necessary to satisfy the relationship (that is, the relationship of Na1-Nd1 ≧ 0).

Further, as shown in FIG. 3, when Na1 is increased and the value of Na1-Nd1 is increased, the leakage current can be suppressed. However, when Na1 is extremely increased, an increase in current collapse is inevitable. As a result of repeated examinations by the present inventors on the dependency between Na1-Nd1 and current collapse, when Na1-Nd1> 1.6 × 10 ¹⁹ cm ⁻³ is satisfied, characteristic degradation due to current collapse becomes unacceptable. I understood. That is, from the viewpoint of suppressing current collapse, Na1 and Nd1 are preferably set so as to satisfy the relationship of 1.6 × 10 ¹⁹ cm ⁻³ ≧ Na1−Nd1.

Here, since the donor-type impurity and the acceptor-type impurity are segregated and aggregated at the interface between the nitride semiconductor substrate 1 and the epitaxial growth layer, the concentrations of the donor-type impurity and the acceptor-type impurity at the interface are the epitaxial growth layer. More than an order of magnitude higher than their concentrations in That is, if the donor-type impurity concentration and the acceptor-type impurity concentration in the epitaxial growth layer are Nd2 and Na2, respectively, Nd1 / 10 ≧ Nd2 and Na1 / 10 ≧ Na2.

Whether or not the relationship of Na1 ≧ Nd1 is satisfied also depends on the concentration of the donor-type impurity, so the absolute value of the concentration of the acceptor-type impurity is not significant, but for example, the peak concentration of the acceptor-type impurity is 2 × An acceptor-type impurity is preferably added so as to be 10 ¹⁸ cm ⁻³ . However, if the relationship of impurity concentration is defined only by the bulk peak concentration, the amount of acceptor-type impurities and the amount of donor-type impurities in the vicinity of the interface will be reversed if there is a distribution in the film thickness direction. Is also possible. Therefore, it is desirable that the acceptor-type impurity is added in the same amount as the donor-type impurity or more than the donor-type impurity at the sheet concentration.

Further, as shown in FIG. 4, even in a region shallower than the interface between the nitride semiconductor substrate 1 and the epitaxial growth layer, the concentration of the acceptor impurity (C) is higher than the concentration of the donor impurity (Si). Yes. Therefore, assuming that the donor-type impurity concentration at the interface between the buffer layer 2 and the channel layer 3 is Nd3 and the acceptor-type impurity concentration is Na3, the relationship is Na3 ≧ Nd3.

In FIG. 4, the concentration of C is locally high from the depth of 0.8 μm to 1.2 μm, and the concentration of C has a terrace-like distribution in that region. This is because the buffer layer 2 is intentionally doped with C by 3 × 10 ¹⁶ cm ⁻³ . A GaN-based crystal has N vacancies introduced as crystal defects, and the N vacancies function as donor-type impurities, and therefore exhibit n-type characteristics unless intentional doping is performed. Therefore, C is intentionally introduced as a low-concentration acceptor impurity in order to compensate the donor impurity. In particular, in the present invention, in order to compensate for impurity aggregation at the interface between the substrate and the epitaxially grown layer, the interface is locally doped with acceptor-type impurities at a peak concentration exceeding the concentration of donor-type impurities. This is different from the prior art (for example, Patent Documents 1 and 2).

According to the heterojunction field effect transistor of the present embodiment, the buffer caused by the donor-type impurity aggregated at the interface due to the acceptor-type impurity introduced at a high concentration at the interface between the nitride semiconductor substrate 1 and the epitaxial growth layer. Leakage current can be suppressed. Further, the region where the acceptor-type impurity is introduced at a high concentration is limited to the vicinity of the interface with the epitaxial growth layer (the region having a depth of 0.8 μm to 1.2 μm in FIG. 4). It is possible to prevent the acceptor impurity concentration in the inside from becoming higher than necessary, and to suppress the occurrence of current collapse. Accordingly, it is possible to improve the electrical characteristics of the heterojunction field effect transistor made of a nitride semiconductor.

5 to 9 are views for explaining a method of manufacturing the heterojunction field effect transistor shown in FIG. In these drawings, the same or corresponding elements as those shown in FIG. 1 are denoted by the same reference numerals.

First, the nitride semiconductor substrate 1 is placed in an epitaxial growth apparatus, and an epitaxial growth method such as a MOCVD (Metal Organic Chemical Vapor Deposition) method or MBE (Molecular Beam Epitaxy) method is used to form a nitride semiconductor substrate 1 on the nitride semiconductor substrate 1 from GaN. A buffer layer 2 is formed. At this time, the growth condition of the buffer layer 2 is such that the acceptor type impurity is larger than the donor type impurity at the interface between the nitride semiconductor substrate 1 and the buffer layer 2 (interface between the nitride semiconductor substrate 1 and the epitaxial growth layer). Adjust. Subsequently, the channel layer 3 made of GaN is epitaxially grown on the buffer layer 2. At this time, the growth conditions of the channel layer 3 are adjusted so that the acceptor type impurity is larger than the donor type impurity at the interface between the buffer layer 2 and the channel layer 3. Further, an electron supply layer 4 made of Al _0.17 Ga _0.83 N is epitaxially grown on the channel layer 3. As a result, an epitaxial growth layer including the buffer layer 2, the channel layer 3, and the electron supply layer 4 is formed as shown in FIG.

The nitride semiconductor substrate 1 on which the buffer layer 2, the channel layer 3, and the electron supply layer 4 are formed is taken out from the epitaxial growth apparatus. Then, a resist mask 14 having openings in the formation region of the drain electrode 7 and the source electrode 8 is formed on the electron supply layer 4 by using a photolithography technique. Then, by ion implantation using the resist mask 14 as a mask, an n-type impurity such as Si is applied to the epitaxial growth layer under conditions of an implantation dose of 1 × 10 ¹³ to 1 × 10 ¹⁷ cm ⁻² and an implantation energy of 10 to 1000 keV. Introduce. Thereby, n-type

impurity implantation regions

5 and 6 are formed as shown in FIG.

After removing the resist mask 14, a metal such as Ti, Al, Nb, Hf, Zr, Sr, Ni, Ta, Au, Mo, W, or two or more thereof is used, for example, by vapor deposition or sputtering. A multilayer film including the same is deposited on the electron supply layer 4, and further, the drain electrode 7 and the source electrode 8 are formed as shown in FIG. 7 by using a lift-off method or a photolithography method.

Then, for example, by using a vapor deposition or sputtering, Ti, Al, Cu, Cr , Mo, W, Pt, Au, Ni, metals such as Pd, IrSi, PtSi, silicide such as NiSi ₂ or TiN,, A nitride metal such as WN is deposited on the electron supply layer 4, and a gate electrode 9 is formed as shown in FIG. 8 using a lift-off method or a photolithography method.

Thereafter, the surface protective film 10 is formed on the surface of the electron supply layer 4 made of an oxide film or a nitride film of Si or Al by using a film forming method with high coverage such as an ALD (Atomic Layer Deposition) method. Then, the surface protective film 10 is patterned by dry etching or the like so that the drain electrode 7, the source electrode 8 and the gate electrode 9 are exposed from the surface protective film 10. Thereby, as shown in FIG. 9, a surface protective film 10 covering the surface of the electron supply layer 4 is formed. The formation method of the surface protective film 10 is not limited to the ALD method, and other methods such as PECVD (Plasma Enhanced Chemical Vapor Deposition) method and sputtering method may be used, or a combination thereof may be used.

Through the above steps, the configuration of the heterojunction field effect transistor shown in FIG. 1 is formed. Thereafter, a heterojunction field effect transistor as a semiconductor device is completed through a process of forming wirings, via holes, and the like.

In the above description, a typical structure of a heterojunction field effect transistor has been shown, but the following modifications may be considered.

Assuming that the band gap size of the channel layer 3 is E ₃ and the band gap size of the electron supply layer 4 is E ₄ , the heterojunction field effect transistor is operated as long as the relationship of E ₃ <E ₄ is satisfied. Enough. Therefore, the nitride semiconductor substrate 1, the buffer layer 2, and the channel layer 3 are not necessarily formed of GaN, and the electron supply layer 4 is not necessarily formed of Al _0.17 Ga _0.83 N. If the channel layer 3 and the electron supply layer 4 are composed of compounds composed of two or more elements including N of Al, Ga and N, the compositions of the elements constituting the channel layer 3 and the electron supply layer 4 are different from each other. Good. For example, the nitride semiconductor substrate 1, the buffer layer 2, and the channel layer 3 may also be formed of a material mainly composed of Al _x Ga _1-x N (0 ≦ x ≦ 1).

In order to satisfy the relationship of E ₃ <E ₄ , the nitride semiconductor constituting the channel layer 3 is Al _x Ga _1-x N, and the nitride semiconductor constituting the electron supply layer 4 is Al _y Ga _1-y N. Then, it is only necessary that the relations 0 ≦ x <1, 0 <y <1, and x <y are satisfied. Furthermore, the channel layer 3 and the electron supply layer 4 may be made of a nitride semiconductor obtained by adding In to two or more elements including N among Al, Ga, and N.

In the growth process, the channel layer 3 and the electron supply layer 4 made of various nitride semiconductors as described above are trimethylammonium, trimethylgallium, trimethylindium, ammonia or n-type dopants which are nitride semiconductor source gases. The channel layer 3 and the electron supply layer 4 are formed by adjusting the pressure, flow rate, temperature, and introduction time of silane, which is a raw material gas, to have a desired composition, film thickness, and doping concentration. Can do.

When the channel layer 3 and the electron supply layer 4 are composed of a compound composed of two or more elements including N of Al, Ga, and N, a large polarization effect is generated in the electron supply layer 4, so that the high concentration The two-dimensional electron gas 11 can be generated. When the concentration of the two-dimensional electron gas 11 is high, it is advantageous for increasing the current of the transistor and for increasing the output. However, the AlN binary crystal cannot be adopted only for the channel layer 3. This is because there is no material that can be used for the electron supply layer 4 because there is no material having a band gap exceeding that of AlN in the nitride semiconductor.

The higher the dielectric breakdown electric field of the channel layer 3, the higher the breakdown voltage of the heterojunction field effect transistor. Since Al _x Ga _1-x N has a higher Al composition, the band gap becomes larger and the breakdown electric field becomes higher. Therefore, Al _x Ga _1-x N used for the channel layer 3 has a higher Al composition (x Is closer to 1). In addition, since the gate leakage current flowing from the gate electrode 9 to the heterointerface via the electron supply layer 4 can be suppressed as the band gap of the electron supply layer 4 is larger, Al _y Ga _1-y N used for the electron supply layer 4 It is preferable that the Al composition is higher (y is close to 1).

The cross-sectional shape of the gate electrode 9 does not need to be a rectangle as shown in FIG. Further, as shown in FIG. 10, a field plate electrode 13 that is electrically connected to the gate electrode 9 and extends on the surface protective film 10 may be provided. Although FIG. 10 shows a configuration in which the field plate electrode 13 extends from the gate electrode 9 to the drain electrode 7 side, the field plate electrode 13 may be provided to extend to the source electrode 8 side. It may be provided so as to extend to both the 7 side and the source electrode 8 side. By providing the field plate electrode 13, electric field concentration at the end of the gate electrode 9 can be suppressed, which is effective in reducing current collapse. The material of the field plate electrode 13 may be any material as long as it can be electrically connected to the gate electrode 9 and can be formed so as not to contact the epitaxial growth layer.

The field plate electrode 13 is formed by forming the surface protective film 10 and then forming a conductive film as a material of the field plate electrode 13 by vapor deposition or the like, and then using the lift-off method or the like to form the conductive film. This can be done by processing into a desired pattern.

The nitride semiconductor substrate 1 may be formed of AlN, InN, or a mixed crystal thereof. However, it is difficult to continuously grow crystals having different lattice constants, and it is necessary to consider the influence on the buffer leakage current by inserting a lattice strain relaxation layer into the epitaxial growth layer. Therefore, the lattice constant of nitride semiconductor substrate 1 and the lattice constant of buffer layer 2 and channel layer 3 are preferably aligned. From the viewpoint of relaxation of lattice strain, the channel layer 3 and the electron supply layer 4 can be formed without forming the buffer layer 2 on the nitride semiconductor substrate 1. That is, the buffer layer 2 is not necessarily formed on the nitride semiconductor substrate 1 and may not be formed.

Each of the channel layer 3 and the electron supply layer 4 does not necessarily have a single-layer structure having a single composition. If the condition of the band gap size (E ₃ <E ₄ ) is satisfied, the channel layer 3 and the electron supply layer The In composition, Al composition, and Ga composition may vary spatially in the layer 4, and the channel layer 3 and the electron supply layer 4 may have a multilayer structure including a plurality of layers having different compositions. Further, the channel layer 3 and the electron supply layer 4 may contain an n-type or p-type impurity in the nitride semiconductor.

In FIG. 1, the interface acceptor type impurity 12 is shown only at the interface between the nitride semiconductor substrate 1 and the buffer layer 2, but the interface acceptor type impurity is introduced at the nitride semiconductor substrate 1 and the buffer layer 2. It is not limited to the interface. As described above, when materials having different lattice constants are used for the nitride semiconductor substrate 1 and the buffer layer 2, a lattice strain relaxation layer may be inserted into the epitaxial growth layer. In that case, the process is interrupted during the epitaxial growth, and depending on the conditions, there is a possibility that impurities are aggregated even at the interface (growth interface). In such a case, it may be better to introduce an acceptor-type impurity also at the interface between the buffer layer 2 and the channel layer 3.

If the drain electrode 7 and the source electrode 8 form an ohmic contact with the two-dimensional electron gas 11 generated in the vicinity of the interface between the electron supply layer 4 and the channel layer 3, as shown in FIG. The n-type

impurity implantation regions

5 and 6 may not be provided under the source electrode 8. The drain electrode 7 and the source electrode 8 may be provided so as to be in contact with the upper surface of the electron supply layer 4 as shown in FIG. 11, or the electron supply is performed in the recess formed in the electron supply layer 4 as shown in FIG. It may be provided in contact with the layer 4. However, the resistance between the drain electrode 7 and the source electrode 8 and the two-dimensional electron gas 11 is reduced when the n-type

impurity implantation regions

5 and 6 are formed under the drain electrode 7 and the source electrode 8. Therefore, it is advantageous for increasing the current and output of the transistor.

11 can be formed by omitting the n-type impurity ion implantation shown in FIG. 12 can be formed by performing a process of selectively removing the electron supply layer 4 using, for example, a Cl ₂ -based etching gas instead of the process shown in FIG.

In addition, each modification mentioned above can also be implemented in combination with each other.

<Embodiment 2>
FIG. 13 is a diagram illustrating the structure of the heterojunction field effect transistor according to the second embodiment. In FIG. 13, the arrangement of interface acceptor impurity 12 present at the interface between nitride semiconductor substrate 1 and buffer layer 2 is different from that in the first embodiment. That is, in the first embodiment, the interface acceptor-type impurity 12 is added so as to uniformly compensate the donor-type impurity over the entire interface, but in the second embodiment, below the drain electrode 7 and the source electrode 8 (n The interface acceptor type impurity 12 is added only to the portion below the type

impurity implantation regions

5 and 6. Therefore, in the present embodiment, the relationship between the donor-type impurity concentration and the acceptor-type impurity concentration described above, that is, 1.6 × 10 ¹⁹ cm ⁻³ ≧ Na 1 ⁻ only in the region below the drain electrode 7 and the source electrode 8. The relationship of Nd1 ≧ 0, Nd1 / 10 ≧ Nd2, and Na1 / 10 ≧ Na2 is satisfied.

In the heterojunction field effect transistor of FIG. 13, the buffer leak current from the n-type

impurity implantation regions

5 and 6 through the donor-type impurity segregation portion at the interface between the nitride semiconductor substrate 1 and the buffer layer 2 is reduced to the interface acceptor. Reduced by mold impurities 12. Further, an access region from the source electrode 8 to the drain electrode 7 (refers to a region between the drain electrode 7 and the gate electrode 9 and a region between the source electrode 8 and the gate electrode 9 in the channel layer 3) and a channel region. Immediately below (referring to a region under the gate electrode 9), since there is no interface acceptor impurity 12, the probability of electron capture can be reduced, thereby suppressing current collapse. Therefore, current collapse can be suppressed more than in the first embodiment.

In FIG. 13, the interface acceptor impurity 12 is shown only in the region below the drain electrode 7 and the source electrode 8, but the interface acceptor impurity 12 is at least below the drain electrode 7 and the source electrode 8. It only has to be covered. In particular, from the viewpoint of suppressing current collapse, since it is only necessary to reduce electron capture in a region to which a high electric field is applied, the interface acceptor impurity 12 is extended to a region between the source electrode 8 and the gate electrode 9. But there is no big impact. Further, the interface acceptor type impurity 12 should not exist at all other than the region below the drain electrode 7 and the source electrode 8, but in the region below the drain electrode 7 and the source electrode 8 and other regions. If there is a concentration difference in the interface acceptor type impurity 12, a certain effect can be expected.

The structure of FIG. 13 is realized by, for example, selectively injecting an acceptor-type impurity element into the formation region of the interface acceptor-type impurity 12 in the nitride semiconductor substrate 1 before the epitaxial growth layer forming step. Can do. Specifically, a method may be considered in which a resist mask having an opening for forming the interface acceptor impurity 12 is formed on the nitride semiconductor substrate 1 and an acceptor impurity element is implanted by ion implantation using the resist mask as a mask. .

Each of the modifications described in the first embodiment can be applied to the heterojunction field effect transistor of the second embodiment.

It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

1 nitride semiconductor substrate, 2 buffer layer, 3 channel layer, 4 electron supply layer, 5 n-type impurity implanted region, 6 n-type impurity implanted region, 7 drain electrode, 8 source electrode, 9 gate electrode, 10 surface protective film, 11 2D electron gas, 12 interface acceptor type impurities, 13 field plate electrode, 14 resist mask.

Claims

A nitride semiconductor substrate (1);
An epitaxial growth layer (2, 2) formed on the nitride semiconductor substrate (1) and comprising a nitride semiconductor including an uppermost electron supply layer (4) and a channel layer (3) under the electron supply layer (4). 3,4) and
A drain electrode (7) and a source electrode (8) formed on the electron supply layer (4);
Formed on the electron supply layer (4) and arranged in a region between the drain electrode (7) and the source electrode (8), spaced apart from the drain electrode (7) and the source electrode (8). The provided gate electrode (9),
With
Donor-type impurity concentration Nd1 and acceptor-type impurity concentration Na1 at the interface between the nitride semiconductor substrate (1) and the epitaxially grown layer (2,3,4), and donor-type impurities in the epitaxially grown layer (2,3,4) The concentration Nd2 and the acceptor-type impurity concentration Na2 are 1.6 × 10 19 cm −3 ≧ Na1-Nd1 ≧ 0, Nd1 / 10 at least in the region below the drain electrode (7) and the source electrode (8). Satisfies the relationship of ≧ Nd2 and Na1 / 10 ≧ Na2.
Heterojunction field effect transistor.
The acceptor-type impurity concentration in the epitaxial growth layer (2, 3, 4) is such that at least in the region below the drain electrode (7) and the source electrode (8), the nitride semiconductor substrate (1) and the epitaxial growth layer (2 The heterojunction field effect transistor according to claim 1, which is locally high in the vicinity of the interface with.
The heterojunction field effect according to claim 1 or 2, wherein the nitride semiconductor substrate (1) and the channel layer (3) are mainly composed of Al x Ga 1-x N (0 ≦ x <1). Type transistor.
The epitaxial growth layer (2, 3, 4) further includes a buffer layer (2) positioned between the nitride semiconductor substrate (1) and the channel layer (3),
The donor-type impurity concentration Nd3 and the acceptor-type impurity concentration Na3 at the interface between the buffer layer (2) and the channel layer (3) satisfy the relationship of Na3 ≧ Nd3.
The heterojunction field effect transistor according to claim 1.
5. The heterostructure according to claim 4, wherein the nitride semiconductor substrate (1), the buffer layer (2), and the channel layer (3) are mainly composed of Al x Ga 1-x N (0 ≦ x <1). Junction field effect transistor.
An n-type impurity implantation region (5, 6) into which an n-type impurity is implanted is formed in a portion of the electron supply layer (4) below the drain electrode (7) and the source electrode (8). The heterojunction field effect transistor according to any one of claims 1 to 5.
The relationship of 1.6 × 10 19 cm −3 ≧ Na1-Nd1 ≧ 0, Nd1 / 10 ≧ Nd2, Na1 / 10 ≧ Na2 only in the region below the drain electrode (7) and the source electrode (8). The heterojunction field effect transistor according to any one of claims 1 to 6, wherein:
On the nitride semiconductor substrate (1), an epitaxial growth layer (2, 3, 4) made of a nitride semiconductor including an uppermost electron supply layer (4) and a channel layer (3) under the electron supply layer (4). )
Forming a drain electrode (7), a source electrode (8) and a gate electrode (9) on the electron supply layer (4), and
In the step of forming the epitaxial growth layer (2, 3, 4), the donor-type impurity concentration Nd1 and the acceptor-type impurity concentration Na1 at the interface between the nitride semiconductor substrate (1) and the epitaxial growth layer (2, 3, 4) The donor-type impurity concentration Nd2 and the acceptor-type impurity concentration Na2 in the epitaxial growth layer (2, 3, 4) are at least in the region below the formation region of the drain electrode (7) and the source electrode (8). .6 × 10 19 cm −3 ≧ Na1-Nd1 ≧ 0, Nd1 / 10 ≧ Nd2, and Na1 / 10 ≧ Na2 are formed to form the epitaxial growth layer (2,3,4).
A method of manufacturing a heterojunction field effect transistor.
In the step of forming the epitaxial growth layer (2, 3, 4), the acceptor-type impurity concentration in the epitaxial growth layer (2, 3, 4) is at least a region below the drain electrode (7) and the source electrode (8). In claim 8, the epitaxial growth layer (2, 3, 4) is formed so as to be locally high in the vicinity of the interface between the nitride semiconductor substrate (1) and the epitaxial growth layer (2, 3, 4). A method for producing a heterojunction field effect transistor according to 1.
The epitaxial growth layer (2, 3, 4) further includes a buffer layer (2) positioned between the nitride semiconductor substrate (1) and the channel layer (3),
The step of forming the epitaxial growth layer (2, 3, 4)
Forming a buffer layer (2) on the nitride semiconductor substrate (1);
Forming the channel layer (3) on the buffer layer (2);
Forming the electron supply layer (4) on the channel layer (3);
Contains
In the step of forming the channel layer (3), the donor-type impurity concentration Nd3 and the acceptor-type impurity concentration Na3 at the interface between the buffer layer (2) and the channel layer (3) satisfy the relationship of Na3 ≧ Nd3. The method of manufacturing a heterojunction field effect transistor according to claim 8 or 9, wherein the channel layer (3) is formed.
Prior to the step of forming the epitaxially grown layers (2, 3, 4), the nitride semiconductor substrate (1) is selected in a portion below the formation region of the drain electrode (7) and the source electrode (8). And further introducing an acceptor-type impurity,
The relationship of 1.6 × 10 19 cm −3 ≧ Na1-Nd1 ≧ 0, Nd1 / 10 ≧ Nd2, Na1 / 10 ≧ Na2 only in the region below the drain electrode (7) and the source electrode (8). The method of manufacturing a heterojunction field effect transistor according to any one of claims 8 to 10, wherein: