JP2012514909A - 前置加算器段を備えたデジタル信号処理ブロック - Google Patents
前置加算器段を備えたデジタル信号処理ブロック Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
- G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
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- H—ELECTRICITY
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- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
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Abstract
Description
本発明は、集積回路装置(integrated circuit device:IC)に関する。より特定的には、本発明は、ICのための前置加算器段を備えたデジタル信号処理ブロックに関する。
プログラマブルロジックデバイス(programmable logic device:PLD)は、特定の論理関数を実行するようプログラム可能な周知のタイプの集積回路である。PLDの一種であるフィールドプログラマブルゲートアレイ(field programmable gate array:FPGA)は典型的にはプログラム可能なタイルのアレイを含む。これらのプログラム可能なタイルは、たとえば、入出力ブロック(input/output block:IOB)、構成可能論理ブロック(configurable logic block:CLB)、専用のランダムアクセスメモリブロック(random access memory block:BRAM)、乗算器、デジタル信号処理ブロック(digital signal processing block:DSP)、プロセッサ、クロックマネージャ、遅延ロックループ(delay lock loop:DLL)などを含み得る。本明細書においては、「含む」および「含んでいる」は、限定を伴わずに含むことを意味する。
1つ以上の実施例は、概して、集積回路装置(IC)に関し、より特定的には、ICのための前置加算器段を備えたデジタル信号処理ブロックに関する。
添付の図面は、本発明の1つ以上の局面に従った具体的な実施例を示す。しかしながら、添付の図面は、本発明を図示した実施例に限定するものとみなされるべきではなく、説明および理解のみを目的としたものである。
以下の説明においては、本発明の具体的な実施例をより十分に説明するために多くの具体的な詳細が述べられる。しかしながら、当業者にとっては、以下に述べるすべての具体的な詳細がなくても本発明が実施可能であることが明らかになるはずである。他の例においては、本発明を不明瞭にすることを避けるために周知の特徴は詳細には記載されていない。例示を容易にするために、異なる図においても同じ参照符号が付いていれば同じ要素を指すものとする。しかしながら、代替的な実施例においては、要素は異なっている可能性がある。
Claims (15)
- 集積回路であって、
デジタル信号処理ブロックと、
前置加算器段および制御バスを含むデジタル信号処理ブロックと、
前置加算器段の演算を動的に制御するために前置加算器段に結合された制御バスとを含み、
前記前置加算器段は、
制御バスに結合された第1のマルチプレクサの第1の入力ポートと、
制御バスに結合された第1の論理ゲートの第2の入力ポートと、
制御バスに結合された第2の論理ゲートの第3の入力ポートと、
制御バスに結合された加算器/減算器の第4の入力ポートとを含む、集積回路。 - 前置加算器段は、第2の入力ポートへの入力に応じて第1の論理ゲートの出力を介して0の値を受取るよう加算器/減算器の第1のデータ入力を動的に設定するように構成される、請求項1に記載の集積回路。
- 前置加算器段は、第3の入力ポートへの入力に応じて第2の論理ゲートの出力を介して0の値を受取るよう加算器/減算器の第2のデータ入力を動的に設定するように構成される、請求項2に記載の集積回路。
- 前置加算器段は、第1の入力ポートへの入力に応じて0−、1−または2−レジスタ遅延を有する入力データを動的に選択するように構成される、請求項3に記載の集積回路。
- 前置加算器段は、第4の入力ポートへの入力に応じて加算または減算するよう加算器/減算器を動的に設定するように構成される、請求項4に記載の集積回路。
- デジタル信号処理ブロックに入力データを与えるためにインスタンス化された回路関数を与えるよう、構成ビットストリームに応じて構成されたフィールドプログラマブル論理ゲートをさらに含む、請求項5に記載の集積回路。
- 前置加算器段は、入力データを与えるためにフィールドプログラマブル論理ゲートを再構成する必要なしに、第1の入力ポート、第2の入力ポート、第3の入力ポートおよび第4の入力ポートからなる群のうち少なくとも1つのポートを介して動的に再構成可能であり、
前置加算器段は、絶対値関数、連続する複素共役関数、連続する乗算関数、連続する虚数乗法、多重化関数、レジスタファイル関数、シフトレジスタ論理関数、およびパイプライン・リバランシング関数を与えるよう動的に再構成可能である、請求項6に記載の集積回路。 - 複数の遅延素子と、
複数の遅延素子のうち第1の遅延素子を介してフィルタの第1のタップ、および複数の遅延素子のうち第2の遅延素子を介してフィルタの第2のタップを受取るよう結合された前置加算器段とを含む、請求項1に記載の集積回路であって、前記第1のタップおよび前記第2のタップは共通の係数を有し、前記集積回路はさらに、
第1の入力における第1のタップと第2タップとの和および第2の入力における共通の係数を含む前置加算器段の出力を受取るよう結合された乗算器と、
乗算器の出力を受取るよう結合された加算器とを含む、請求項1に記載の集積回路。 - 集積回路において実現されるべき回路においてフィルタを構成する方法であって、
回路の高水準設計を受取るステップと、
高水準設計でフィルタを識別するステップと、
フィルタの係数を分析するステップと、
高水準設計のフィルタを、共通の係数に対応するよう構成された回路の処理ブロックを用いるフィルタに変換するステップとを含み、処理ブロックは共通の係数に関連付けられるタップを受取るよう結合される、方法。 - 高水準設計のフィルタを、共通の係数に対応するよう構成された処理ブロックを用いるフィルタに変換するステップは、フィルタを対称的な転置コンボリューションフィルタとして構成するステップを含む、請求項9に記載の方法。
- 係数を分析するステップは、高水準設計でフィルタの対称的な係数を識別するステップを含む、請求項9に記載の方法。
- 共通の係数を第1の入力として処理ブロックの乗算器に与えるステップをさらに含む、請求項9に記載の方法。
- 共通の係数に関連付けられるタップの和を第2の入力として乗算器に与えるステップをさらに含む、請求項12に記載の方法。
- 共通の係数に関連付けられるタップの和を第2の入力として乗算器に与えるステップは、DSPブロックの前置加算器回路を用いて和を生成するステップを含む、請求項13に記載の方法。
- 共通の係数に関連付けられるタップの差を第2の入力として乗算器に与えるステップをさらに含む、請求項12に記載の方法。
Applications Claiming Priority (5)
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US12/360,836 US8543635B2 (en) | 2009-01-27 | 2009-01-27 | Digital signal processing block with preadder stage |
US12/360,836 | 2009-01-27 | ||
US12/418,979 US8479133B2 (en) | 2009-01-27 | 2009-04-06 | Method of and circuit for implementing a filter in an integrated circuit |
US12/418,979 | 2009-04-06 | ||
PCT/US2010/020565 WO2010088017A1 (en) | 2009-01-27 | 2010-01-08 | Digital signal processing block with preadder stage |
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JP5356537B2 JP5356537B2 (ja) | 2013-12-04 |
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