FR2819073B1 - Microarchitecture d'unite arithmetique - Google Patents
Microarchitecture d'unite arithmetiqueInfo
- Publication number
- FR2819073B1 FR2819073B1 FR0017240A FR0017240A FR2819073B1 FR 2819073 B1 FR2819073 B1 FR 2819073B1 FR 0017240 A FR0017240 A FR 0017240A FR 0017240 A FR0017240 A FR 0017240A FR 2819073 B1 FR2819073 B1 FR 2819073B1
- Authority
- FR
- France
- Prior art keywords
- microarchitecture
- arithmetic unit
- arithmetic
- unit
- unit microarchitecture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
- G06F7/5095—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators word-serial, i.e. with an accumulator-register
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
- G06F7/5443—Sum of products
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0017240A FR2819073B1 (fr) | 2000-12-28 | 2000-12-28 | Microarchitecture d'unite arithmetique |
US10/035,033 US6925480B2 (en) | 2000-12-28 | 2001-12-28 | Microarchitecture of an arithmetic unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0017240A FR2819073B1 (fr) | 2000-12-28 | 2000-12-28 | Microarchitecture d'unite arithmetique |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2819073A1 FR2819073A1 (fr) | 2002-07-05 |
FR2819073B1 true FR2819073B1 (fr) | 2003-02-28 |
Family
ID=8858358
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0017240A Expired - Fee Related FR2819073B1 (fr) | 2000-12-28 | 2000-12-28 | Microarchitecture d'unite arithmetique |
Country Status (2)
Country | Link |
---|---|
US (1) | US6925480B2 (fr) |
FR (1) | FR2819073B1 (fr) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6976049B2 (en) * | 2002-03-28 | 2005-12-13 | Intel Corporation | Method and apparatus for implementing single/dual packed multi-way addition instructions having accumulation options |
JP2004021573A (ja) * | 2002-06-17 | 2004-01-22 | Hitachi Ltd | データ処理装置 |
US7051062B2 (en) * | 2002-09-10 | 2006-05-23 | Analog Devices, Inc. | Apparatus and method for adding multiple-bit binary-strings |
US20070088774A1 (en) * | 2003-04-17 | 2007-04-19 | Zhizhong Li | Computer technical solution of mixed q-nary and carry line digital engineering method |
JP2005011272A (ja) * | 2003-06-23 | 2005-01-13 | Oki Electric Ind Co Ltd | 演算回路 |
US7840627B2 (en) * | 2003-12-29 | 2010-11-23 | Xilinx, Inc. | Digital signal processing circuit having input register blocks |
US7567997B2 (en) * | 2003-12-29 | 2009-07-28 | Xilinx, Inc. | Applications of cascading DSP slices |
US7853632B2 (en) | 2003-12-29 | 2010-12-14 | Xilinx, Inc. | Architectural floorplan for a digital signal processing circuit |
US7853636B2 (en) * | 2003-12-29 | 2010-12-14 | Xilinx, Inc. | Digital signal processing circuit having a pattern detector circuit for convergent rounding |
US7467177B2 (en) * | 2003-12-29 | 2008-12-16 | Xilinx, Inc. | Mathematical circuit with dynamic rounding |
US7860915B2 (en) * | 2003-12-29 | 2010-12-28 | Xilinx, Inc. | Digital signal processing circuit having a pattern circuit for determining termination conditions |
US8495122B2 (en) * | 2003-12-29 | 2013-07-23 | Xilinx, Inc. | Programmable device with dynamic DSP architecture |
US7840630B2 (en) | 2003-12-29 | 2010-11-23 | Xilinx, Inc. | Arithmetic logic unit circuit |
US7467175B2 (en) * | 2003-12-29 | 2008-12-16 | Xilinx, Inc. | Programmable logic device with pipelined DSP slices |
US7870182B2 (en) | 2003-12-29 | 2011-01-11 | Xilinx Inc. | Digital signal processing circuit having an adder circuit with carry-outs |
US7472155B2 (en) * | 2003-12-29 | 2008-12-30 | Xilinx, Inc. | Programmable logic device with cascading DSP slices |
US7849119B2 (en) | 2003-12-29 | 2010-12-07 | Xilinx, Inc. | Digital signal processing circuit having a pattern detector circuit |
US7844653B2 (en) | 2003-12-29 | 2010-11-30 | Xilinx, Inc. | Digital signal processing circuit having a pre-adder circuit |
US7853634B2 (en) | 2003-12-29 | 2010-12-14 | Xilinx, Inc. | Digital signal processing circuit having a SIMD circuit |
US7882165B2 (en) * | 2003-12-29 | 2011-02-01 | Xilinx, Inc. | Digital signal processing element having an arithmetic logic unit |
US7480690B2 (en) * | 2003-12-29 | 2009-01-20 | Xilinx, Inc. | Arithmetic circuit with multiplexed addend inputs |
US7865542B2 (en) * | 2003-12-29 | 2011-01-04 | Xilinx, Inc. | Digital signal processing block having a wide multiplexer |
JP5133693B2 (ja) | 2004-11-08 | 2013-01-30 | 志 中 李 | ハイブリッド数字繰上げ方式および繰上げラインのデジタルエンジニアリング方法のコンピュータ技術的解法 |
US8479133B2 (en) | 2009-01-27 | 2013-07-02 | Xilinx, Inc. | Method of and circuit for implementing a filter in an integrated circuit |
US8543635B2 (en) | 2009-01-27 | 2013-09-24 | Xilinx, Inc. | Digital signal processing block with preadder stage |
GB2617159B (en) * | 2022-03-31 | 2024-06-12 | Imagination Tech Ltd | Accumulator hardware |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3529622B2 (ja) * | 1998-05-08 | 2004-05-24 | 株式会社東芝 | 演算回路 |
US6542915B1 (en) * | 1999-06-17 | 2003-04-01 | International Business Machines Corporation | Floating point pipeline with a leading zeros anticipator circuit |
US6415311B1 (en) * | 1999-06-24 | 2002-07-02 | Ati International Srl | Sign extension circuit and method for unsigned multiplication and accumulation |
-
2000
- 2000-12-28 FR FR0017240A patent/FR2819073B1/fr not_active Expired - Fee Related
-
2001
- 2001-12-28 US US10/035,033 patent/US6925480B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US6925480B2 (en) | 2005-08-02 |
FR2819073A1 (fr) | 2002-07-05 |
US20020143837A1 (en) | 2002-10-03 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20070831 |