JP2012510742A - クロックデューティサイクル適合による半導体デバイスの性能の低下の補償 - Google Patents

クロックデューティサイクル適合による半導体デバイスの性能の低下の補償 Download PDF

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JP2012510742A
JP2012510742A JP2011537892A JP2011537892A JP2012510742A JP 2012510742 A JP2012510742 A JP 2012510742A JP 2011537892 A JP2011537892 A JP 2011537892A JP 2011537892 A JP2011537892 A JP 2011537892A JP 2012510742 A JP2012510742 A JP 2012510742A
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Japan
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integrated circuit
duty cycle
performance
clock signal
parameter
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JP2011537892A
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Japanese (ja)
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JP2012510742A5 (enExample
Inventor
パパジョルジュ ヴァシリオス
ヴィアタ マチェイ
ホエンチェル ジャン
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2012510742A publication Critical patent/JP2012510742A/ja
Publication of JP2012510742A5 publication Critical patent/JP2012510742A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/008—Reliability or availability analysis
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Pulse Circuits (AREA)
JP2011537892A 2008-11-28 2009-11-27 クロックデューティサイクル適合による半導体デバイスの性能の低下の補償 Pending JP2012510742A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE102008059502A DE102008059502A1 (de) 2008-11-28 2008-11-28 Kompensation der Leistungsbeeinträchtigung von Halbleiterbauelementen durch Anpassung des Tastgrades des Taktsignals
DE102008059502.0 2008-11-28
US12/604,532 US8018260B2 (en) 2008-11-28 2009-10-23 Compensation of degradation of performance of semiconductor devices by clock duty cycle adaptation
US12/604,532 2009-10-23
PCT/EP2009/008470 WO2010060638A1 (en) 2008-11-28 2009-11-27 Compensation of degradation of performance of semiconductor devices by clock duty cycle adaptation

Publications (2)

Publication Number Publication Date
JP2012510742A true JP2012510742A (ja) 2012-05-10
JP2012510742A5 JP2012510742A5 (enExample) 2013-01-17

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ID=42145369

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JP2011537892A Pending JP2012510742A (ja) 2008-11-28 2009-11-27 クロックデューティサイクル適合による半導体デバイスの性能の低下の補償

Country Status (6)

Country Link
US (1) US8018260B2 (enExample)
JP (1) JP2012510742A (enExample)
KR (1) KR20110138209A (enExample)
CN (1) CN102308283A (enExample)
DE (1) DE102008059502A1 (enExample)
WO (1) WO2010060638A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014203775A1 (ja) * 2013-06-17 2014-12-24 ピーエスフォー ルクスコ エスエイアールエル 半導体装置
JP2015228265A (ja) * 2010-12-21 2015-12-17 インテル コーポレイション マイクロプロセッサにおける熱設計電力を設定する方法及び装置

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US8578143B2 (en) * 2011-05-17 2013-11-05 Apple Inc. Modifying operating parameters based on device use
US9465373B2 (en) 2013-09-17 2016-10-11 International Business Machines Corporation Dynamic adjustment of operational parameters to compensate for sensor based measurements of circuit degradation
KR102197943B1 (ko) 2014-04-04 2021-01-05 삼성전자주식회사 메모리 컨트롤러와 이를 포함하는 시스템
US9251890B1 (en) 2014-12-19 2016-02-02 Globalfoundries Inc. Bias temperature instability state detection and correction
US9704598B2 (en) * 2014-12-27 2017-07-11 Intel Corporation Use of in-field programmable fuses in the PCH dye
KR102235521B1 (ko) 2015-02-13 2021-04-05 삼성전자주식회사 특정 패턴을 갖는 저장 장치 및 그것의 동작 방법
US11605416B1 (en) * 2021-11-10 2023-03-14 Micron Technology, Inc. Reducing duty cycle degradation for a signal path
CN119231931B (zh) * 2024-12-03 2025-04-01 浙江绿力智能科技有限公司 一种转换器智能调控方法及系统

Citations (7)

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JPH04274100A (ja) * 1991-03-01 1992-09-30 Nec Corp テスト回路内蔵のメモリーｌｓｉ
JP2000012639A (ja) * 1998-06-24 2000-01-14 Toshiba Corp モニターｔｅｇのテスト回路
JP2002006003A (ja) * 2000-04-20 2002-01-09 Texas Instr Inc <Ti> 位相ロック・ループ用全ディジタル内蔵自己検査回路および検査方法
JP2004004049A (ja) * 2002-04-24 2004-01-08 Semiconductor Energy Lab Co Ltd 半導体装置の検査方法及び検査装置
JP2005063414A (ja) * 2003-08-19 2005-03-10 Internatl Business Mach Corp <Ibm> 経年変化電子コンポーネントを補償するために動作周波数を調整する周波数変更技法
WO2008132033A1 (en) * 2007-04-30 2008-11-06 International Business Machines Corporation Monitoring reliability of a digital system
JP2009510793A (ja) * 2005-10-04 2009-03-12 インターナショナル・ビジネス・マシーンズ・コーポレーション チップ性能を最大にするように負荷サイクル回路を自動的に自己較正するための装置及び方法

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Publication number Priority date Publication date Assignee Title
US6903564B1 (en) * 2003-11-12 2005-06-07 Transmeta Corporation Device aging determination circuit
US7333905B2 (en) * 2006-05-01 2008-02-19 International Business Machines Corporation Method and apparatus for measuring the duty cycle of a digital signal
US7330061B2 (en) * 2006-05-01 2008-02-12 International Business Machines Corporation Method and apparatus for correcting the duty cycle of a digital signal

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04274100A (ja) * 1991-03-01 1992-09-30 Nec Corp テスト回路内蔵のメモリーｌｓｉ
JP2000012639A (ja) * 1998-06-24 2000-01-14 Toshiba Corp モニターｔｅｇのテスト回路
JP2002006003A (ja) * 2000-04-20 2002-01-09 Texas Instr Inc <Ti> 位相ロック・ループ用全ディジタル内蔵自己検査回路および検査方法
JP2004004049A (ja) * 2002-04-24 2004-01-08 Semiconductor Energy Lab Co Ltd 半導体装置の検査方法及び検査装置
JP2005063414A (ja) * 2003-08-19 2005-03-10 Internatl Business Mach Corp <Ibm> 経年変化電子コンポーネントを補償するために動作周波数を調整する周波数変更技法
JP2009510793A (ja) * 2005-10-04 2009-03-12 インターナショナル・ビジネス・マシーンズ・コーポレーション チップ性能を最大にするように負荷サイクル回路を自動的に自己較正するための装置及び方法
WO2008132033A1 (en) * 2007-04-30 2008-11-06 International Business Machines Corporation Monitoring reliability of a digital system
JP2010527174A (ja) * 2007-04-30 2010-08-05 インターナショナル・ビジネス・マシーンズ・コーポレーション ディジタル・システムの信頼性を監視するシステム、およびその監視する方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015228265A (ja) * 2010-12-21 2015-12-17 インテル コーポレイション マイクロプロセッサにおける熱設計電力を設定する方法及び装置
US9898067B2 (en) 2010-12-21 2018-02-20 Intel Corporation Method and apparatus to configure thermal design power in a microprocessor
US9898066B2 (en) 2010-12-21 2018-02-20 Intel Corporation Method and apparatus to configure thermal design power in a microprocessor
WO2014203775A1 (ja) * 2013-06-17 2014-12-24 ピーエスフォー ルクスコ エスエイアールエル 半導体装置

Also Published As

Publication number Publication date
DE102008059502A1 (de) 2010-06-10
US20100134167A1 (en) 2010-06-03
CN102308283A (zh) 2012-01-04
KR20110138209A (ko) 2011-12-26
US8018260B2 (en) 2011-09-13
WO2010060638A1 (en) 2010-06-03

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